SG153011A1 - Methods for adjusting critical dimension uniformity in an etch process - Google Patents

Methods for adjusting critical dimension uniformity in an etch process

Info

Publication number
SG153011A1
SG153011A1 SG200808450-1A SG2008084501A SG153011A1 SG 153011 A1 SG153011 A1 SG 153011A1 SG 2008084501 A SG2008084501 A SG 2008084501A SG 153011 A1 SG153011 A1 SG 153011A1
Authority
SG
Singapore
Prior art keywords
gas
substrate
methods
critical dimension
etching
Prior art date
Application number
SG200808450-1A
Other languages
English (en)
Inventor
Guowen Ding
Changhun Lee
Teh-Tien Su
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Publication of SG153011A1 publication Critical patent/SG153011A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Plasma & Fusion (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
SG200808450-1A 2007-11-28 2008-11-13 Methods for adjusting critical dimension uniformity in an etch process SG153011A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/946,562 US20100003828A1 (en) 2007-11-28 2007-11-28 Methods for adjusting critical dimension uniformity in an etch process with a highly concentrated unsaturated hydrocarbon gas

Publications (1)

Publication Number Publication Date
SG153011A1 true SG153011A1 (en) 2009-06-29

Family

ID=40437052

Family Applications (1)

Application Number Title Priority Date Filing Date
SG200808450-1A SG153011A1 (en) 2007-11-28 2008-11-13 Methods for adjusting critical dimension uniformity in an etch process

Country Status (7)

Country Link
US (1) US20100003828A1 (ja)
EP (1) EP2065923A3 (ja)
JP (1) JP2009135498A (ja)
KR (1) KR101046818B1 (ja)
CN (1) CN101452881A (ja)
SG (1) SG153011A1 (ja)
TW (1) TW200947560A (ja)

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US8546263B2 (en) 2011-04-27 2013-10-01 Applied Materials, Inc. Method of patterning of magnetic tunnel junctions
US8647977B2 (en) 2011-08-17 2014-02-11 Micron Technology, Inc. Methods of forming interconnects
US9368368B2 (en) * 2014-07-21 2016-06-14 Tokyo Electron Limited Method for increasing oxide etch selectivity
US12080561B2 (en) * 2022-01-26 2024-09-03 Nanya Technology Corporation Method of processing substrate

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Also Published As

Publication number Publication date
TW200947560A (en) 2009-11-16
EP2065923A2 (en) 2009-06-03
EP2065923A3 (en) 2010-03-10
JP2009135498A (ja) 2009-06-18
KR101046818B1 (ko) 2011-07-06
US20100003828A1 (en) 2010-01-07
KR20090055469A (ko) 2009-06-02
CN101452881A (zh) 2009-06-10

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