SG128440A1 - Silicon-rich oxide for copper damascene interconnect incorporating low dielectric constant dielectrics - Google Patents

Silicon-rich oxide for copper damascene interconnect incorporating low dielectric constant dielectrics

Info

Publication number
SG128440A1
SG128440A1 SG200302467A SG200302467A SG128440A1 SG 128440 A1 SG128440 A1 SG 128440A1 SG 200302467 A SG200302467 A SG 200302467A SG 200302467 A SG200302467 A SG 200302467A SG 128440 A1 SG128440 A1 SG 128440A1
Authority
SG
Singapore
Prior art keywords
layer
dielectric
low
silicon
dielectric constant
Prior art date
Application number
SG200302467A
Other languages
English (en)
Inventor
Liu Huang
Joh Sudijono
Simon Chooi
Original Assignee
Chartered Semiconductor Mfg
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chartered Semiconductor Mfg filed Critical Chartered Semiconductor Mfg
Publication of SG128440A1 publication Critical patent/SG128440A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604—Deposition from a gas or vapour
    • H01L21/31608—Deposition of SiO2
    • H01L21/31612—Deposition of SiO2 on a silicon body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
SG200302467A 2002-06-20 2003-05-02 Silicon-rich oxide for copper damascene interconnect incorporating low dielectric constant dielectrics SG128440A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/177,855 US7186640B2 (en) 2002-06-20 2002-06-20 Silicon-rich oxide for copper damascene interconnect incorporating low dielectric constant dielectrics

Publications (1)

Publication Number Publication Date
SG128440A1 true SG128440A1 (en) 2007-01-30

Family

ID=29720386

Family Applications (1)

Application Number Title Priority Date Filing Date
SG200302467A SG128440A1 (en) 2002-06-20 2003-05-02 Silicon-rich oxide for copper damascene interconnect incorporating low dielectric constant dielectrics

Country Status (4)

Country Link
US (1) US7186640B2 (fr)
EP (1) EP1378937A3 (fr)
SG (1) SG128440A1 (fr)
TW (1) TW200406853A (fr)

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JP4015510B2 (ja) * 2002-09-09 2007-11-28 日本エー・エス・エム株式会社 半導体集積回路の多層配線用層間絶縁膜及びその製造方法
US20040185674A1 (en) * 2003-03-17 2004-09-23 Applied Materials, Inc. Nitrogen-free hard mask over low K dielectric
KR100591183B1 (ko) * 2004-12-23 2006-06-19 동부일렉트로닉스 주식회사 구리 다마신 공정을 이용하는 반도체 소자의 층간 절연막형성 방법
KR100680499B1 (ko) * 2005-11-02 2007-02-08 동부일렉트로닉스 주식회사 반도체 소자 및 그 제조 방법
US20070205516A1 (en) * 2006-03-01 2007-09-06 Taiwan Semiconductor Manufacturing Co., Ltd. Low-k dielectric layer, semiconductor device, and method for fabricating the same
TW200742076A (en) * 2006-03-17 2007-11-01 Sumitomo Chemical Co Semiconductor field effect transistor and method of manufacturing the same
US8067292B2 (en) * 2008-01-23 2011-11-29 Macronix International Co., Ltd. Isolation structure, non-volatile memory having the same, and method of fabricating the same
US7863176B2 (en) * 2008-05-13 2011-01-04 Micron Technology, Inc. Low-resistance interconnects and methods of making same
JP5173863B2 (ja) * 2009-01-20 2013-04-03 パナソニック株式会社 半導体装置およびその製造方法
US20170287834A1 (en) * 2016-03-29 2017-10-05 Microchip Technology Incorporated Contact Expose Etch Stop
US11521945B2 (en) * 2019-11-05 2022-12-06 Nanya Technology Corporation Semiconductor device with spacer over bonding pad
US20210143114A1 (en) * 2019-11-08 2021-05-13 Nanya Technology Corporation Semiconductor device with edge-protecting spacers over bonding pad

Family Cites Families (21)

* Cited by examiner, † Cited by third party
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TW337608B (en) 1997-10-29 1998-08-01 United Microelectronics Corp Process for producing unlanded via
WO2000002235A1 (fr) * 1998-07-06 2000-01-13 Strasbaugh Procede pour rendre plans des circuits integres
TW405223B (en) 1998-07-28 2000-09-11 United Microelectronics Corp Method for avoiding the poisoning at the trench of the dual damascene structure and the dielectric hole
US6166427A (en) 1999-01-15 2000-12-26 Advanced Micro Devices, Inc. Integration of low-K SiOF as inter-layer dielectric for AL-gapfill application
US6133143A (en) 1999-06-28 2000-10-17 United Semiconductor Corp. Method of manufacturing interconnect
US6207556B1 (en) 1999-07-09 2001-03-27 United Microelectronics Corp. Method of fabricating metal interconnect
US6228756B1 (en) 1999-08-10 2001-05-08 United Microelectronics Corp. Method of manufacturing inter-metal dielectric layer
US6727588B1 (en) * 1999-08-19 2004-04-27 Agere Systems Inc. Diffusion preventing barrier layer in integrated circuit inter-metal layer dielectrics
US6365327B1 (en) * 1999-08-30 2002-04-02 Agere Systems Guardian Corp. Process for manufacturing in integrated circuit including a dual-damascene structure and an integrated circuit
US6174797B1 (en) 1999-11-08 2001-01-16 Taiwan Semiconductor Manufacturing Company Silicon oxide dielectric material with excess silicon as diffusion barrier layer
TW439188B (en) 1999-11-18 2001-06-07 Taiwan Semiconductor Mfg Manufacturing method of fluorinated dielectric layer for integrated circuits
JP3464956B2 (ja) * 1999-12-09 2003-11-10 Ｎｅｃエレクトロニクス株式会社 半導体装置
US6541367B1 (en) 2000-01-18 2003-04-01 Applied Materials, Inc. Very low dielectric constant plasma-enhanced CVD films
JP2001223269A (ja) * 2000-02-10 2001-08-17 Nec Corp 半導体装置およびその製造方法
GB2367426A (en) * 2000-04-04 2002-04-03 Agere Syst Guardian Corp Silicon rich oxides and fluorinated silicon oxide insulating layers
US6475925B1 (en) * 2000-04-10 2002-11-05 Motorola, Inc. Reduced water adsorption for interlayer dielectric
US6232217B1 (en) * 2000-06-05 2001-05-15 Chartered Semiconductor Manufacturing Ltd. Post treatment of via opening by N-containing plasma or H-containing plasma for elimination of fluorine species in the FSG near the surfaces of the via opening
US6458722B1 (en) 2000-10-25 2002-10-01 Applied Materials, Inc. Controlled method of silicon-rich oxide deposition using HDP-CVD
TW473924B (en) 2000-12-08 2002-01-21 Taiwan Semiconductor Mfg Method for reducing leakage current of interconnect dielectric layer in dual damascene process
TW476106B (en) * 2001-03-26 2002-02-11 Taiwan Semiconductor Mfg Method for removing residual fluorine gas from high density plasma chemical vapor phase deposition chamber
US6696222B2 (en) * 2001-07-24 2004-02-24 Silicon Integrated Systems Corp. Dual damascene process using metal hard mask

Also Published As

Publication number Publication date
EP1378937A2 (fr) 2004-01-07
TW200406853A (en) 2004-05-01
EP1378937A3 (fr) 2008-03-26
US20030235980A1 (en) 2003-12-25
US7186640B2 (en) 2007-03-06

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