4 3 91 8 8 A7 B7 五、發明説明（1 ) 發明領域： 本發明係揭露-種積難财含氟介電層 特別是指开)成一多矽氧化犀（Si h 王法， 名〇 層（h oxlde; SR〇)以隔絕含 氟魏璃中之氟向外概舆錢反應的方法。 .發明背景： 近年來’騎频電路元件杨輕、薄、短、小的特性 遊進’但是元件積集度的快速增加及極小化，卻 度增加，進而產生衫如電子遷移或應力導致的空洞問ς， 影響到元件的可靠歧產品喊率。故錢漸進 領域的同時’低電阻銅（〇0因具有優於傳統積體電2 鋁CA1)金屬製程的特性，如⑴低電阻特性；⑺良好的抗 電子遷移性；（3)良好的抗應力致空洞形成性質等，可提供 較快的傳輸速度，並且具有較小的電阻_電容延遲時間(RC delay time)，將可減少上述問題的產生，而成為未來金屬 化的一種趨勢。此外，因為高積集度及小尺寸使得晶片的表 面無法提供足夠面積來製作所需的導線結構，是以積體電路 的内連線設計，由以往簡單的二、三層結構，發展成為四層 以上的多重金屬内連線（Multilevel Interconnects)製程。 經濟部智慧財產局員工消費合作社印製 目箾，在深次微来領域之多重金屬内連線中，其元件製 程上常常會應用到有機低介電係數G〇wk)介電層（例如： 利用化學氣相沉積法（Chemical Vapor Deposition; CVD)形 成之含氟矽玻璃（Fluorinated Silicate Glass; FSG)及利用旋 塗方式形成之HSQ (Hydrogen SilsesQuioxane)等氧化珍材 料）來降低電阻-電容延遲時間（RC delay time )，就當前 本紙張尺度適用中國國家榇準（CNS ) Μ規格U!OX2i>7公釐） 8 A7 B7 五、發明説明（>) 常被製作的鋁銅（AlCu)金屬及銅（Cu)金屬堆疊之多重 金屬内連線而言，主要係先製作多層以含氟矽玻璃（FSG) 為層間介電層（Inter-Metal Dielectrics; IMD)之AlCu導線， 再於上製作以未摻雜矽玻璃（Und〇ped Silicate 〇1咖； 為層間介電層之鋼金屬導線。其中所述銅金屬溝填製程步驟 中需具備一氮化矽層或一氮氧化矽層（Si〇N)來作為開啟 所述溝槽時的蝕刻終止層，但是，當Cu/USG結構需形成在4 3 91 8 8 A7 B7 V. Description of the invention (1) Field of the invention: The present invention discloses-a kind of difficult-to-finish fluorine-containing dielectric layer, especially refers to a polysilicon oxide rhino (Sih Wang method, name. Layer (hoxlde; SR〇) in order to isolate the fluorine reaction in the fluorine-containing glass. The background of the invention: In recent years, the 'riding frequency circuit components Yang light, thin, short, small characteristics swim in' but components The rapid increase and minimization of the degree of accumulation, but the degree of increase, which in turn causes holes such as electron migration or stress, which affects the reliability of the product. The low-resistance copper (〇 0Because it has better properties than traditional integrated aluminum 2Al CA1) metal process, such as ⑴low resistance characteristics; ⑺good resistance to electron migration; (3) good resistance to stress-induced void formation, etc., can provide faster The transmission speed and smaller RC delay time will reduce the above problems and become a trend of metallization in the future. In addition, because of the high concentration and small size, the surface of the wafer Unable to provide enough area The wire structure required for the production is based on the interconnection design of integrated circuits. From the simple two-layer and three-layer structure in the past, it has developed into a multi-level multiconnect process with more than four layers. Intellectual Property Bureau, Ministry of Economic Affairs Employee consumer cooperatives print headings. In the multi-metal interconnects in the deep sub-micron field, their component processes are often applied to organic low-dielectric coefficients (Gowk) dielectric layers (eg, using chemical vapor deposition). Method (Chemical Vapor Deposition; CVD) to reduce the resistance-capacitance delay time (RC delay time) of Fluorinated Silicate Glass (FSG) formed by spin coating and HSQ (Hydrogen SilsesQuioxane) formed by spin coating. For the current paper size, the Chinese National Standard (CNS) M specification U! OX2i > 7 mm) 8 A7 B7 V. Description of the invention (>) Aluminum and copper (AlCu) metals and copper (Cu) which are often produced For multi-metal interconnects of metal stacks, it is mainly to produce multiple layers of AlCu wires with FSG as the inter-layer dielectric layer (Inter-Metal Dielectrics; IMD). Undoped silica glass (Undoped Silicate 〇 coffee; steel metal wire as an interlayer dielectric layer. In the copper metal trench filling process steps need to have a silicon nitride layer or a silicon oxynitride layer (Si 〇N) as an etch stop layer when the trench is opened, but when the Cu / USG structure needs to be formed on
AlCu/FSG結構上時或具氮化層之護層需形成於FSG介電層 上時，由於所述氮化層或所述氮氧化層含有之氫易與 所述含氟矽玻璃中矽-氟鍵（Si_F)上穩定度不佳之氟反應’ 而且在钱刻開啟溝槽時將必須面臨其易吸濕反應的問題，所 述含氟矽玻璃中之氟與水分子中之氫反應的方程式係如下所 示： 2H20+{Si-F+Si-F}—{Si-0H...Si-0H}+2HF {Si-OH.. .Si-OH 卜 Si-0-Si+H2 將造成層間（係指所述含氟矽玻璃與作為蝕刻終止層之用的 氮化層或氮氧化層之間）附著力變差或形成氣泡狀空隙，導 致IMD結構不穩固甚至剝離（peeiing)的現象，亦可能造成 銅金屬層結構與鎢插塞間之接觸不良，因而降低元件良率及 產品可靠度。故本發明利用一多矽氧化層（SR〇)以隔絕所 述含氟矽玻璃中之氟向外擴散與水氣反應，降低氟對層間結 構的影響。 ~ 發明之概述： 本發明之主要目的係提供一種積體電路中含氟介電層之 本紙張尺度適用中國國家標準（CNS ) A4規輅（21〇χ297公釐> (請先聞讀背面之注意事項再填寫本頁} ο 裝· 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明説明（ 製程方法’可避免層間附著力降低及層間介電層剝離現象。 本發明之另一目的係形成一多石夕氧化層（Si rich oxide; SRO)以隔絕含氟介電層中之氟向外擴散與水氣反應。 本發明係使用下列步驟來達到上述之目的：首先，提供 一半導體基板，所述基板上已形成有一層或數層鋁金屬層， 並於所述鋁金屬層上形成—含氟矽玻璃（FSG);接著，於 所述含氟砍玻璃中開啟數個溝槽以製作金屬鎢插塞；再接 著，先形成一多矽氧化層（SR0)，再形成一蝕刻終止層， 所述银刻終止層係作為開啟銅金屬内連線之溝槽時終止蝕刻 之用；最後，開啟預備製作銅金屬導線之溝槽，並進行後續 銅金屬溝填製程。其巾所述乡⑪氧化層將可有效防止所述含 氟石夕玻璃之氟向外擴散與氫反應的情形產生，可降低元件缺 陷並提高產品良率。 圖式簡要說明： 圖一A為本發明第一實施例中一已於含复石夕玻璃中 形成金屬鶴插塞之基板的剖面示意圖。 經濟部智慧財產局員工消費合作社印製 圖一B為本發明第一實施例令形成一多石夕氣化層（sr〇)、 —蝕刻終止層及一層間介電層的剖面示意圖。 圖—C為本發明第一實施例中開啟預備製作銅金屬導線之溝 槽的剖面示意圖。 圖-A為本發明第二實施例於含氟石夕玻璃（fsg)上形成有 多石夕氧化層（SRO)及—働彳終止層的剖面示音' 圖。 '如 圖-B為本發料二實闕巾形成金屬絲塞的剖面示意When the AlCu / FSG structure is used or a protective layer with a nitride layer needs to be formed on the FSG dielectric layer, the hydrogen contained in the nitrided layer or the oxynitride layer can easily interact with the silicon in the fluorine-containing silicon glass. The fluorine reaction with poor stability on the fluorine bond (Si_F) 'and the problem of moisture absorption reaction when the groove is opened by money engraving. The equation of the reaction of fluorine in the fluorine-containing silicon glass with hydrogen in water molecules The system is as follows: 2H20 + {Si-F + Si-F} — {Si-0H ... Si-0H} + 2HF {Si-OH .. .Si-OH Bu Si-0-Si + H2 will cause interlayer (Referring to the phenomenon between the fluorine-containing silicate glass and the nitrided layer or oxynitride layer used as an etching stop layer) the adhesion is deteriorated or bubble-like voids are formed, resulting in an unstable IMD structure or even peeling, It may also cause poor contact between the copper metal layer structure and the tungsten plug, thereby reducing component yield and product reliability. Therefore, the present invention utilizes a poly-silicon oxide layer (SR0) to isolate the fluorine in the fluorine-containing silicon glass from outward diffusion and water vapor reaction, thereby reducing the effect of fluorine on the interlayer structure. ~ Summary of the invention: The main purpose of the present invention is to provide a paper with fluorine-containing dielectric layers in integrated circuits. The paper size is applicable to the Chinese National Standard (CNS) A4 Regulation (21〇 × 297 mm) (Please read the back first) Please pay attention to this page before filling in this page} ο Printing · A7 B7 printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (Processing method 'can avoid the decrease of interlayer adhesion and the interlayer dielectric layer peeling phenomenon. The purpose is to form a Si rich oxide (SRO) layer to isolate the fluorine in the fluorine-containing dielectric layer from outward diffusion and water vapor reaction. The present invention uses the following steps to achieve the above purpose: First, a A semiconductor substrate on which one or more aluminum metal layers have been formed, and a fluorine-containing silicon glass (FSG) is formed on the aluminum metal layer; then, several grooves are opened in the fluorine-containing chopped glass. Grooves to make metal tungsten plugs; then, a polysilicon oxide layer (SR0) is formed first, and then an etching stop layer is formed, and the silver etch stop layer is used to stop etching when the copper metal interconnect is opened. Use; most , Open the trench for preparing copper metal wire, and carry out the subsequent copper metal trench filling process. The oxidized layer of the village will effectively prevent the fluorine of the fluorite glass from diffusing outward and reacting with hydrogen. It can reduce component defects and improve product yield. Brief description of the drawings: Figure 1A is a schematic cross-sectional view of a substrate in which a metal crane plug has been formed in glass containing compound stone in the first embodiment of the present invention. Wisdom of the Ministry of Economic Affairs The printed figure 1B of the employee's consumer cooperative of the Property Bureau is a schematic cross-sectional view of the first embodiment of the present invention to form a multi-stone gasification layer (SR0), an etching stop layer and an interlayer dielectric layer. In the first embodiment of the present invention, a schematic cross-sectional view of a trench for preparing a copper metal wire is opened. FIG. -A is a second embodiment of the present invention in which a stony oxide layer (SRO) is formed on a fluorite-containing glass (fsg) and —The cross section of the 働 彳 stop layer is shown in the picture. 'Figure-B is a cross-sectional view of the wire plug formed by the two solid towels of the hair material.
經濟部智慧財產局員工消費合作社印製 4° ? 8 A7 ___ B7 1 · ____ 五、發明説明（tf ) '圖。 圖二<:為本發明第二實施例中形成一餘刻終止層及一層間 介電層，並開啟預備製作銅金屬導線之溝槽的二面 示意圖。 .圖二A為習知技藝中具氮化層護層結構形成於含氟矽玻璃 (FSG)上的剖面示意圖。 圖三B為本發明第三實施例於具氮化層護層結構中形成一 多矽氧化層（SRO)的剖面示意圖。 圖號說明： ---------------IT------ ί ) (請先聞請背面之注$項再填寫本頁) 10-基板 12-第一氮化鈦層 14-銘金屬層 16-第二氮化鈦層 18-含象介電層 20-氧化層 22-金屬鶴插塞 24-多矽氧化層（SR0) 26-蝕刻終止層 28-層間介電層（IMD) 30-溝槽 32-多矽氧化層（SR〇) 34-氧化層 36-氮氧化層 38-金屬鶴插塞 40-氮氧化層 42-氧化層 44-溝槽 50-已完成電路之基板 60-含氟介電層 70-氧化層 75-多矽氧化層（SRO) 80-氮化層 發明詳細說明： 以下之實施例係闡述本發明之詳細實施内容，請同時參 閱本發明第一實施例所附圖 一A〜圖一C、第二實施例所附 本紙張尺度適用中國國家標孪（CNS ) A4規格（2丨OX297公釐）Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 °? 8 A7 ___ B7 1 · ____ V. Description of the Invention (tf). Fig. 2 is a schematic diagram of two sides of a trench stop layer and an interlayer dielectric layer formed in a second embodiment of the present invention, and a trench for preparing a copper metal wire is opened. Figure 2A is a schematic cross-sectional view of a nitrided layer protective structure formed on a fluorine-containing silicon glass (FSG) in the conventional art. FIG. 3B is a schematic cross-sectional view of forming a polysilicon oxide layer (SRO) in a nitride-based protective layer structure according to a third embodiment of the present invention. Description of drawing number: --------------- IT ------ ί) (please listen to the note on the back before filling in this page) 10- 板 12- 第一Titanium nitride layer 14-metal layer 16-second titanium nitride layer 18-containing dielectric layer 20-oxide layer 22-metal crane plug 24-polysilicon oxide layer (SR0) 26-etch stop layer 28- Interlayer dielectric layer (IMD) 30-trench 32-polysilicon oxide layer (SR〇) 34-oxide layer 36-nitrogen oxide layer 38-metal crane plug 40-nitrogen oxide layer 42-oxide layer 44-trench 50 -Substrate 60 of the completed circuit-Fluoride-containing dielectric layer 70-Oxidation layer 75-Polysilicon oxide layer (SRO) 80-Nitriding layer Detailed description of the invention: The following examples explain the detailed implementation of the present invention, please also Refer to the attached drawings 1A to 1C of the first embodiment of the present invention, and the paper size attached to the second embodiment is applicable to the Chinese National Standard (CNS) A4 specification (2 丨 OX297 mm)
43 91 8 B A7 _____ B7_ 五、發明説明（ί ) 圖二1A〜圖二C及第三實施例所附圖三A〜圖三B之剖面示 意圖： 第一實施例 首先，請參閱圖一A ’提供一已完成前段製程之半導體 '基板10，並於所述基板10上形成有一層或數層金屬内連線， 而所述金屬内連線係以含氟介電層為層間介電層，其製作方 法係皆依序形成第一氮化鈦層12、鋁金屬層14及第二氮化鈦 層16 ’其中所述鋁金屬層16係可具有少量銅及矽成分;接著， 於所述第二氮化鈦層16上形成一含氟介電層18及一氧化層 20 ’並於所述含氟介電層18中利用微影技術及非均向之乾式 蝕刻技術開啟一個或數個溝槽以製作金屬鎢（w)插塞 (plug)22’其中所述含氟介電層is係為一具低介電係數(i〇w k)之介電材質，其介電係數係介於3.3至37之間，其係利用 化學虱相沉積法（Chemical Vapor Deposition; CVD)所形成 一含氟矽玻璃（Fluorinated Silicate Glass; FSG)或一含說氧 化層；所述金屬鎢（W)插塞22之製作過程係先於開啟之溝 槽中充填金屬鎢，再利用化學機械研磨法（chemical Mechanical Polish; CMP)回蝕刻（etchhg back)至所述含 氟介電層18表面。 再接著，晴參閱圖-B，於上述銘金屬内連線上繼續製 作鋼金屬内連線，而在所述銅金屬内連線製程步驟中需具備 二氮化石夕層或-氮氧化销（Sl〇N)來作為開啟所述溝槽3〇 時的铜終讀26，林發日狀重要概係在職所述侧 ”止層26之月利用化學氣相沉積法先形成一多石夕氧化層 ( CNS ) A4CiT^7〇^97^i )--~-- 43 9VB 8 A7 ------------B7 五、發明説明~~ (silicon rich 0xide; SR〇) 24，再形成所述飯刻終止層冗及 層間介電層28，其中所述多石夕氧化層24係用以阻隔所述含 氟介電層18及所述餘刻終止層26，可有效防止所述含氟介電 層18之氟向外擴散與氫反應的情形產生，所述多矽氧化層％ 係在沉積氧化矽材質時調整矽（Si)之供應比例，使最後之 形成氧化矽層中矽的比例較高，而其厚度係介於2〇〇人至 1000人之間；所述蝕刻終止層26係作為開啟鋼金屬内連線溝 槽30時之蝕刻終止層26，係為一氮化矽層或一氮氧化矽層 (SiON) ’其厚度係介於2⑻A至5〇〇A之間；所述層間介電 層28係為一氧化材質’如：未摻雜矽玻璃（Und叩ed Silicate Glass; USG)。 最後，請參閱圖一C，利用微影技術及非均向之乾式蝕 刻技術開啟—個或數個預備製作銅金屬内連線之溝槽30 ’並 以所述說化層或氮氧化層為蝕刻之終止層，再於後進行後續 之銅金屬溝填製程’所述銅金屬溝填製程係包括利用化學氣 相沉積法或物理氣相沉積法（ptlysical Vap〇r Dep〇siti〇n; PVD)形成一氮化鈕（TaN)金屬阻障層、利用化學氣相沉 經濟部智慧財產局員工消費合作社印製 積法或物理氣相沉積法沉積一銅金屬成核層（nudeati〇n layer)、利用電化學沉積法（Electro-Chemical Deposition; ECD)沉積一鋼金屬層填滿所述溝槽3〇及後續之銅金屬之 CMP處理。 第二實施例 首先，请參閱圖二A，提供一已完成前段製程之半導體 基板10 ’並於所述基板10上形成有一層或數層金屬内連線，43 91 8 B A7 _____ B7_ V. Explanation of the Invention (ί) Figure 2A ~ Figure 2C and the schematic cross-sections of Figure 3A ~ Figure 3B of the third embodiment: First Embodiment First, please refer to Figure 1A 'Provide a semiconductor that has completed the previous process' substrate 10, and one or more layers of metal interconnects are formed on the substrate 10, and the metal interconnects use a fluorine-containing dielectric layer as an interlayer dielectric layer The manufacturing method is to sequentially form the first titanium nitride layer 12, the aluminum metal layer 14, and the second titanium nitride layer 16 ', wherein the aluminum metal layer 16 may have a small amount of copper and silicon components; then, A fluorine-containing dielectric layer 18 and an oxide layer 20 ′ are formed on the second titanium nitride layer 16, and one or more of them are opened in the fluorine-containing dielectric layer 18 using lithography technology and non-uniform dry etching technology. Grooves to make a metal tungsten (w) plug 22 ', wherein the fluorine-containing dielectric layer is a dielectric material with a low dielectric constant (iowk), and the dielectric constant is Between 3.3 and 37, it is a Fluorinated S glass (Fluorinated S) formed by Chemical Vapor Deposition (CVD). ilicate Glass (FSG) or an oxide layer; the manufacturing process of the metal tungsten (W) plug 22 is first filled with metal tungsten in the opened trench, and then chemical mechanical polishing (CMP) is used. Etch back to the surface of the fluorine-containing dielectric layer 18. Then, referring to Figure-B, continue to make steel-metal interconnects on the above-mentioned metal-metal interconnects, and in the copper metal interconnect process steps, it is necessary to have a dinitride layer or -nitrogen oxide pins ( SlON) is used as the final reading of copper 26 when the groove is opened 30. The important state of Lin Fa ’s sun is that the side "stop layer 26" is used to form a multi-stone oxidation first by chemical vapor deposition. Layer (CNS) A4CiT ^ 7〇 ^ 97 ^ i)-~-43 9VB 8 A7 ------------ B7 V. Description of the invention ~~ (silicon rich 0xide; SR〇) 24 Then, the redundant and interlayer dielectric layer 28 is formed, and the rocky oxide layer 24 is used to block the fluorine-containing dielectric layer 18 and the remaining stop layer 26, which can effectively prevent The fluorine of the fluorine-containing dielectric layer 18 is caused by the outward diffusion of hydrogen and the reaction of the hydrogen. The polysilicon oxide layer% is adjusted by the supply ratio of silicon (Si) when the silicon oxide material is deposited, so that the final silicon oxide layer is formed. The proportion of silicon is relatively high, and its thickness is between 200 and 1,000 people; the etch stop layer 26 is used as the etch stop layer 26 when the steel metal interconnect trench 30 is opened, Is a silicon nitride layer or a silicon oxynitride layer (SiON) 'its thickness is between 2⑻A and 500A; the interlayer dielectric layer 28 is an oxide material' such as: undoped silicon Glass (Und 叩 ed Silicate Glass; USG). Finally, please refer to FIG. 1C, using photolithography technology and non-uniform dry etching technology to open one or several trenches 30 'for preparing copper metal interconnects. Take said chemical layer or oxynitride layer as the stop layer for etching, and then perform the subsequent copper metal trench filling process. The copper metal trench filling process includes the use of chemical vapor deposition or physical vapor deposition ( ptlysical Vap〇r Dep〇siti〇n; PVD) to form a nitride barrier (TaN) metal barrier layer, using the chemical vapor deposition of the Intellectual Property Bureau of the Ministry of Economic Affairs, the Intellectual Property Bureau employee consumer cooperative printing method or physical vapor deposition method A copper metal nucleation layer (nudeation layer), an electrochemical deposition method (Electro-Chemical Deposition; ECD) is used to deposit a steel metal layer to fill the trenches 30 and subsequent CMP of copper metal. Second implementation Example First, please refer to Figure 2A, provide a completed pre-stage system The semiconductor substrate 10 'is formed on the substrate and metal wires have one or several layers 10,
本紙張跋 it 财 _ 2i〇xt^T 43 91 88 Α7 Β7 五 、齊明説明（ 經濟部智慧財產局員工消費合作社印製 而所述金屬内連線係以含氟介電層為層間介電層，其製作方 法係皆依序形成第一氤化鈦層12、鋁金屬層14及第二氮化鈦 層16’其中所述鋁金屬層16係可具有少量銅及矽成分;接著， 於所述第二氮化鈦層16上形成一含氟介電層18、一多矽氧化 層（SRO) 32、一氧化層34及一蝕刻終止層，其中所述含氟 ^1 %層18係為一具低介電係數（i〇w k)之介電材質，其介 屯係數係介於3.3至3.7之間’其係利用化學氣相沉積法所形 成之一含氟矽玻璃（FSG)或為一含氟氧化層；所述多矽氧 化層（SRO)係為本發明之重要特徵，其係利用化學氣相沉 積法所开>成，乃用以阻隔所述含氟介電層18及後續製作之银 刻終止層36，可有效防止所述含氟介電層18之氟向外擴散與 氫反應的情形產生’其厚度係介於2〇〇a至ιοοοΑ之間；所述 氧化層34之厚度係介於3〇〇A至1〇〇〇人之間，可以不成長此層 結構；所述蝕刻終止層36係作為後續製作金屬鎢插塞時，進 行回蝕刻處理之終止層，其麵—氮姆層或—氮氧化石夕層 (SlON) ’其厚度係介於3〇〇A至ιοοοΑ之間。 接著，請參閱圖二B ,利用微影技術及非均向之乾式蝕 刻技術開啟一個或數個溝槽以製作金屬鎢插塞38，而所述金 屬鎢插塞38之製作過程係先於開啟之溝槽中充填金屬鎢，再 利用化學機械研磨法回蝕刻金屬鎢至完全移除所述蝕刻終止 層36為止。 再接著，請參閱圖二C ’於上述以金屬鎢插塞相連接之 多重鋁金屬内連線上繼續製作銅金屬内連線，在所述鋼金屬 内連線製財射係先糊化學氣相_法形成—開啟銅金This paper is _ 2i〇xt ^ T 43 91 88 Α7 Β7 V. Qi Ming's description (printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs and the metal interconnects are based on a fluorine-containing dielectric layer as interlayer dielectric Layer, the manufacturing method is to sequentially form the first titanium halide layer 12, the aluminum metal layer 14, and the second titanium nitride layer 16 ', wherein the aluminum metal layer 16 may have a small amount of copper and silicon components; then, in A fluorine-containing dielectric layer 18, a polysilicon oxide layer (SRO) 32, an oxide layer 34, and an etch stop layer are formed on the second titanium nitride layer 16, wherein the fluorine-containing ^ 1% layer 18 is It is a dielectric material with a low dielectric constant (iowk). Its dielectric coefficient is between 3.3 and 3.7. It is a fluorine-containing silicon glass (FSG) or Is a fluorine-containing oxide layer; the polysilicon oxide layer (SRO) is an important feature of the present invention, which is formed by using a chemical vapor deposition method to block the fluorine-containing dielectric layer 18 And the subsequent silver etch stop layer 36 can effectively prevent the fluorine of the fluorine-containing dielectric layer 18 from diffusing outward and reacting with hydrogen to produce its thickness. Between 200a and ιοοοΑ; the thickness of the oxide layer 34 is between 300A and 10,000 people, and this layer structure may not be grown; the etch stop layer 36 is used as a follow-up When making a tungsten tungsten plug, the termination layer that is etched back, its surface—the nitrogen layer or the oxynitride layer (SlON) —has a thickness between 300A and ιοοοΑ. Next, please refer to FIG. 2B, the lithography technology and the non-uniform dry etching technology are used to open one or several trenches to make a metal tungsten plug 38, and the metal tungsten plug 38 is manufactured in the opened trench before Fill the metal tungsten, and then etch back the metal tungsten by chemical mechanical polishing method until the etch stop layer 36 is completely removed. Then, please refer to FIG. 2C ′ for the multiple aluminum metal interconnections connected by the metal tungsten plugs described above. Continue to produce copper metal interconnects on the line, and the system of metal-to-metal interconnects is first paste the chemical vapor phase _ formation-open copper gold
先 聞 讀 背 I裝· 頁 訂 線 4391 33 A7 ___: _B7 五、發明獅（？ ) ' " ~ ' 屬内連線溝槽44時需具備之姓刻終止層4〇，再形成一層間介 電層42，其中所述蝕刻終止層40係為一氮化矽層或一氮氧化 石夕層（SiON)，其厚度係介於200入至5〇〇入之間；所述層間 介電層42係為一氧化材質，如：未摻雜矽玻璃（Und叩如 Silicate Glass; USG)。 、最後’請同樣參閱圖二C ’利用微影技術及非均向之乾 式蝕刻技術開啟一個或數個預備製作鋼金屬内連線之溝槽 44，並以所述氣化層或氮氧化層為姓刻終止層，再於後進 行後續之銅金屬溝填製程，所述鋼金屬溝填製程係包括利用 化學氣相沉積法或物理氣相沉積法（IJhysical Vap〇r Deposition; PVD)形成一氮化鈕（TaN)金屬阻障層、利用 化學氣相沉積法或物理氣相沉積法沉積一銅金屬成核層 (nucleation layer)、利用電化學沉積法（Electr〇-ChemicalFirst read and read I installed · page binding line 4391 33 A7 ___: _B7 V. The invention of the lion (?) '&Quot; ~' It belongs to the inner connecting groove 44 and has a last name engraving termination layer 40, and then forms a layer. The dielectric layer 42, wherein the etch stop layer 40 is a silicon nitride layer or a silicon oxynitride layer (SiON), and the thickness thereof is between 200 Å and 500 Å; the interlayer dielectric The layer 42 is made of an oxidized material, such as: undoped silicon glass (Und) such as Silicone Glass (USG). Finally, please refer to FIG. 2C. 'Using lithography and non-uniform dry etching technology, one or more trenches 44 for preparing steel-metal interconnects are opened, and the gasification layer or oxynitride layer is used. The final layer is engraved with a surname, and then a subsequent copper metal trench filling process is performed. The steel metal trench filling process includes using chemical vapor deposition or physical vapor deposition (IJhysical Vapor Deposition; PVD) to form a layer. TaN button metal barrier layer, deposition of a copper metal nucleation layer using chemical vapor deposition or physical vapor deposition, and Electro-Chemical
Deposition; ECD)沉積一銅金屬層填滿所述溝槽44及後續之 鋼金屬之CMP處理。 、 第三實施例 首先’請參卿三八，-般在積體電路製程的最後都會 於積體電路元件的表社形成—保護層（passivati〇n)，用以 保護下方之電路。最常見之保護層係由一氧化層7〇與一氮化 層80堆疊而成的結構，但是當所述保護層形成於含說介電層 上時’將因為所述含銳介電層中砍_就鍵（si_F)上穩定度不 佳之敦易與所述氮化層中含有之氫（H)反應，而其產生之 空氣洞隙會降低堆疊結翻之附著力，破壞所述保護層之穩 固性’故本發明提供—種具有多魏化層（sr〇)之保護層 &張尺度適财_雜準（哪---- (請先閔讀背面之注意事項再填寫本頁) .裝. 訂 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 4 ^ 91 B 8 ' A7 ______B7_ 五、發明説明（"f ) 的製作方法來避免上述之問題產生，如圖三B所示。本發明 之第三實施例係於一已完成積體電路製程之半導體基板50上 形成一保護層’再利用微影银刻技術開啟打線塾片（pad) 之窗口。所述形成於一含氟介電層60上之保護層係包括一氧 化層70、一多矽氧化層75及一氮化層80，其中所述氧化層70 係利用高密度電槳·化學氣相沉積法（High Density Plasma Chemical Vapor Deposition; HDPCVD)所形成之未摻雜矽玻 璃（USG)，其厚度係介於8000A至12000A之間；所述多矽 氧化層75則為本發明中用以避免氟與氫反應問題的主要特 徵，所述多矽氧化層75係亦是利用HDPCVD所形成之未摻 雜矽玻璃，其厚度係介於1000A至3000人之間；所述氮化層80 係利用電槳增強式化學氣相沉積法（Plasma Enhanced Chemical Vapor Deposition; PECVD)所形成，其厚度係介於 5000入至8000A之間。其中所述氧化層70與所述多矽氧化層75 之差異係在於所述氧化層70之折射率約在1.46，而石夕含量增 加之所述多矽氧化層75之折射率則約在1.5。 在具有含氟介電層製程之習知技藝中，當所述含氟介電 層與銅金屬系統或含氮化;5夕層之護層結構相堆疊時，例如： Cu/USG結構需形成在AlCy/FSG結構上時、製作Cu/FSG結構 時或具氮化層之護層需形成於FSG介電層上時…等，在這些 積體電路製程中將面臨一嚴重之問題，此係因為所述含說石夕 玻璃中矽-氟鍵（Si-F)上穩定度不佳之氟易與水氣中之氢反 應’或氟與氮化矽材質中所含之氫反應，將會造成層間附著 力變差或形成氣泡狀空隙，導致IMD結構不穩固甚至剝離的 一 本紙張尺度逋用中國國家標準（CNS) A4規格（210x297公釐） (諳先閣讀背面之注意事碩再镇寫本Κ) 裝· 、π 4 3 91 8 8 A7 -----------B7 五、發明説明（" " 現象，亦可能造成銅金屬層結構與鎢插塞間之接觸不良，因 而降低元件良率及產品可靠度。是以在利用氣化層為银刻終 止層之鋼金屬内連線製程及元件最上層包含氮化矽層之護層 、'、°構製私中，其除了所述氮化層無法有效阻撞含氟介電層中 之氟向外擴散，使得其與不斷與製程過程中之水氣相接觸而 產生反應之外，所述氮化層材質中含有之氫同樣會與氟反 應，而產生上述之問題，所以本發明揭露一種利用多矽氧化 層（SRO)以隔絕所述含氟介電層及所述氮化層，有抑制氟 向外擴散與氫反應，降低氟對層間結構的影響。 以上所述係利用較佳實施例詳細說明本發明，而非限制 本發明的範圍，因此熟知此技藝的人士應能明暸，適當而作 些被的改變與調整，仍將不失本發明之要義所在，亦不脫離 本發明之精神和範圍’故都應視為本發明的進一步實施狀 況。謹請貴審查委員明鑑’並祈惠准，是所至禱。 經濟部智慧財產局員工消費合作社印製 一適 度 尺 I私 準 榡 f家 ! ί釐 公Deposition; ECD) A copper metal layer is deposited to fill the trench 44 and subsequent CMP of the steel metal. Third Embodiment First of all, please refer to the third and third parties. Generally, at the end of the integrated circuit manufacturing process, a protective layer (passivating layer) is formed on the surface of the integrated circuit components, to protect the underlying circuit. The most common protective layer is a structure in which an oxide layer 70 and a nitride layer 80 are stacked. However, when the protective layer is formed on a dielectric layer, it will be because of the sharp dielectric layer. The poorly stabilized Dun Yi on the bond (si_F) reacts with the hydrogen (H) contained in the nitride layer, and the air voids generated by it will reduce the adhesion of the stacking junction and destroy the protective layer. 'Stableness' Therefore, the present invention provides a protective layer with multiple layers (sr0) & Zhang Jiao Shi Shi Cai _ Miscellaneous (Where ---- (Please read the notes on the back before filling this page) .Order. Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs and printed by the Consumers’ Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 4 ^ 91 B 8 'A7 ______B7_ V. Method of making the invention (" f) to avoid the above problems As shown in FIG. 3B. A third embodiment of the present invention is to form a protective layer on a semiconductor substrate 50 that has completed the integrated circuit manufacturing process, and then use the lithographic silver engraving technology to open the window of the wire pad. The protective layer formed on a fluorine-containing dielectric layer 60 includes an oxygen The chemical layer 70, a poly-silicon oxide layer 75, and a nitride layer 80, wherein the oxide layer 70 is an undoped layer formed by using a high density electric pad and chemical vapor deposition method (High Density Plasma Chemical Vapor Deposition; HDPCVD). Hybrid silicon glass (USG), the thickness of which is between 8000A and 12000A; the polysilicon oxide layer 75 is the main feature used in the present invention to avoid the problem of reaction between fluorine and hydrogen. The polysilicon oxide layer 75 is It is also undoped silicate glass formed by HDPCVD, and its thickness is between 1000A and 3,000; the nitride layer 80 is made by Plasma Enhanced Chemical Vapor Deposition; PECVD ), The thickness is between 5000 and 8000 A. The difference between the oxide layer 70 and the polysilicon oxide layer 75 is that the refractive index of the oxide layer 70 is about 1.46, and the content of stone The refractive index of the increased polysilicon oxide layer 75 is about 1.5. In the conventional technique of manufacturing a fluorine-containing dielectric layer, when the fluorine-containing dielectric layer is in a system with copper metal or contains nitride; When the protective structure of each layer is stacked, for example: Cu / USG structure When forming on the AlCy / FSG structure, when making the Cu / FSG structure, or when the protective layer with a nitride layer needs to be formed on the FSG dielectric layer, etc., there will be a serious problem in these integrated circuit manufacturing processes. This is because the fluorine with poor stability on the silicon-fluorine bond (Si-F) in Shi Xi glass contains easily reacts with hydrogen in water and gas or fluorine reacts with hydrogen contained in silicon nitride materials. A paper size that causes poor adhesion between layers or the formation of bubble-like voids, causing the IMD structure to be unstable or even peeled. Use Chinese National Standard (CNS) A4 size (210x297 mm). Town copybook K) Installation, π 4 3 91 8 8 A7 ----------- B7 V. Description of the invention (" " The phenomenon may also cause the copper metal layer structure and the tungsten plug Poor contact, which reduces component yield and product reliability. In the steel metal interconnect process using a gasification layer as a silver etch stop layer and the top layer of the component, which includes a silicon nitride layer, a protective layer, the structure is not limited except for the nitride layer. The fluorine in the fluorine-containing dielectric layer diffuses outward, so that it reacts with the continuous contact with the water vapor phase in the manufacturing process. The hydrogen contained in the material of the nitride layer also reacts with fluorine to produce The above problems, therefore, the present invention discloses a method using polysilicon oxide (SRO) to isolate the fluorine-containing dielectric layer and the nitrided layer, which can inhibit the outward diffusion of fluorine and the reaction of hydrogen, and reduce the effect of fluorine on the interlayer structure. . The above description uses the preferred embodiments to explain the present invention in detail, but not to limit the scope of the present invention. Therefore, those skilled in the art should be able to understand that making appropriate changes and adjustments will still not lose the essence of the present invention. Where it does not depart from the spirit and scope of the present invention, it should be regarded as a further implementation status of the present invention. I would like to ask your reviewer ’s clear reference, ’and to pray for your sincere prayer. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, a moderate scale