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Priority to TW95122710ApriorityCriticalpatent/TW200802698A/en
Publication of TW200802698ApublicationCriticalpatent/TW200802698A/en
Internal Circuitry In Semiconductor Integrated Circuit Devices
(AREA)
Abstract
The present invention provides a method of fabricating at least one damascene opening, which comprises the following steps: providing a structure including at least an exposed conductive structure; forming a dielectric barrier layer on the structure and the exposed conductive structure; forming a lower dielectric layer having a low dielectric constant on the dielectric barrier layer; forming an upper dielectric layer having a low dielectric constant on the lower dielectric layer; forming a silicon-rich oxide (SRO) etching barrier layer between the upper and lower dielectric layers and/or forming a SRO rigid mask layer on the upper dielectric layer having a low dielectric constant; and patterning at least the upper and lower dielectric layers having a low dielectric constant to form at least a damascene opening to expose at least a portion of the conductive structure, in which at least a SRO layer corresponding to the upper and lower dielectric layers having a low dielectric constant has a high etching selectivity.
TW95122710A2006-06-232006-06-23A method of fabricating at least one damascene opening
TW200802698A
(en)