473924 五、發明說明（1) 發明領域： 本發明係有關於半導體製程，特別是指一種需 Si LK/Cu雙鑲嵌製程中以碳化矽/氮化矽結合做為蝕刻終止 層以漏低漏電流之方法。 發明背景： 積體 積小，以 之其他的 尺寸縮小 的金屬導 表現，除 介電常數 之阻值R 容C存在 表較低之 電路之製程之目標，除了係使得晶片内元件的體 達到高密度、高良率及降低單位成本之外，元件 性能更是關鍵，例如元件的速度表現。然而元件 的同時，隨著元件的密集，將也使後繼元件連接 線相對變細，而提高阻值，而變得不利於其速度 此之外，内連接金屬導線乃至内連線間介電層的 大小都是元件速度表現的重要關鍵，這是因導線 ，與上層導線和下層導線及相鄰導線之間會有電 ，一如熟悉相關技術之人士所共知’ R C值愈低代 時間延遲，與愈快的反應速度。 因此業界無不朝開發低阻值的金屬導線及低介電常數 内連線間介電層而努力。在金屬導線方面，目前内連線已 有使用銅製程代替鋁製程的報告，例如I BM在1 9 9 7年的宣 告，已說明銅製程時代的到來。銅製程除了可以降低阻 值，而加強速度外，對於電遷移的問題，銅導線已有研究473924 V. Description of the invention (1) Field of the invention: The present invention relates to semiconductor processes, especially to a Si LK / Cu dual damascene process in which a silicon carbide / silicon nitride combination is used as an etching stopper to reduce low leakage current. Method. Background of the invention: Small volume, other dimensions of metal conductivity performance, in addition to the dielectric constant of the resistance value R capacitance C exists in the lower circuit of the process of the goal, except to make the body of the chip in the chip achieve high density In addition to high yield and reduced unit cost, component performance is even more critical, such as the speed performance of the component. However, at the same time as the components are dense, the connection lines of the subsequent components will be relatively thinner, which will increase the resistance value and become unfavorable to the speed. In addition, the interconnect metal wires and even the dielectric layer between interconnects The size of the element is an important key for the speed performance of the component. This is because there will be electricity between the conductor, the upper conductor, the lower conductor, and the adjacent conductor. As everyone familiar with the relevant technology knows, the lower the RC value, the longer the time delay. , With faster response speed. Therefore, the industry has been working hard to develop low-resistance metal wires and low-k dielectric interconnects. In terms of metal conductors, there have been reports of using copper instead of aluminum for internal interconnects. For example, I BM's announcement in 1977 has shown the arrival of the copper process era. In addition to reducing the resistance and enhancing the speed of copper, copper wires have been studied for electromigration.
第5頁 473924 五、發明說明（2) 報告證實小於鋁導線。因此，低阻值導線部分已暫時獲得 > 解決。而低介電常數（low-k)介電層方面，已有多種產品 開發成功，例如以化學氣相沉積法沉積之1 〇 w - k黑鑽石、 coral或以旋塗式方法沉積之low-k的SiLK、Flare H0SP 等等，各家產品各有利弊，因此各大半導體廠皆有其擁護 的對象。 除此之外，另有一影響因素，也是各半導體大廠所關 切的。不是別的，正是雙鑲後（dual damascene)製程所 必須使用的蝕刻終止層，用以達到溝渠導線及介層洞的蝕 刻控制。蝕刻終止層的介電常數高低，將影響整體内連線 _ 介電層之寄生電容大小。雙鑲嵌中最常使用的蝕刻終止層 _ 材料是氮化矽S i N x，氮化矽具有對各種内連線介電層高蝕 刻選擇比的性質，只可惜，氮化矽層的介電常數高達7左 右，相較於low-k内連線介電層的3以下，顯然太大了 ，因 此，具有較低介電常數的碳化矽以做為蝕刻終止層已逐漸 流行。 然而發明人研究發現，當使用有機low-k的Si LK做為 介電層，且若蝕刻終止層為碳化矽則將比以氮化矽層為蝕 刻終止層時高一個數量級的漏電流，例如，在2 0伏的電壓 下碳化矽會有漏電流lx 1 0 _9A而如果是氮化矽則僅有lx 1 0 _1QA而已。因此以漏電流做為考量的要素，碳化石夕是不 利的。 473924 五、發明說明（3) 有鑑於如上所述蝕刻終止層造成漏電流及介電常數之 間的衝突，本發明之動機便是提出一種解決上述問題的方 法。 發明目的及概述： 本發明之目的在提供一種新蝕刻終止層用於雙鑲嵌製 程，以達到降低介電常數，同時也降低漏電流的效果。 本發明係一種以碳化矽/氮化矽結合做為雙鑲後製程 蝕刻終止層，以降低漏電流之方法，包含以下步驟：首 先，提供一基板，基板已完成元件部分，但未形成介電層 並且至少一含連接之金屬導線於其中。接著，形成一含有 碳化矽及氮化矽材料之第一蝕刻終止層；第一蝕刻終止層 的形成法，可以是先形成碳化矽層再形成氮化矽層的 e X - s i t u方法，或碳化石夕層與氮化石夕層同步形成的i η - s i t u 方法，或者是碳化矽層先形成再予以氮化處理以形成氮化 石夕層。三種形成第一姓刻終止層的方法皆可，第一钱刻終 止層中要注意的是碳化層要厚一些，氮化層則較薄即可。 之後，再形成一第一 S i LK層於第一蝕刻終止層上，再形成 如第一蝕刻終止層的第二蝕刻終止層。 接著，再形成一第二S i LK層於第二蝕刻終止層上；然Page 5 473924 5. Description of the invention (2) The report confirms that it is smaller than the aluminum wire. Therefore, the low-resistance wire portion has been temporarily resolved >. As for the low-k dielectric layer, various products have been successfully developed, such as 10W-k black diamond deposited by chemical vapor deposition, coral, or low-k deposited by spin-coating. K's SiLK, Flare H0SP, etc., each product has its own advantages and disadvantages, so major semiconductor factories have their support. In addition, another influencing factor is also concerned by major semiconductor manufacturers. Nothing else, it is the etch stop layer that must be used in the dual damascene process to achieve the etch control of the trench wires and vias. The dielectric constant of the etch stop layer will affect the overall parasitic capacitance of the interconnect _ dielectric layer. The most commonly used etch stop layer in dual damascene _ material is silicon nitride Si N x. Silicon nitride has a high etching selectivity for various interconnect dielectric layers. Unfortunately, the dielectric properties of silicon nitride layers The constant is as high as about 7, which is obviously too large compared to 3 or less in the low-k interconnect dielectric layer. Therefore, silicon carbide with a lower dielectric constant has become popular as an etch stop layer. However, the inventor's research found that when using organic low-k Si LK as the dielectric layer, and if the etch stop layer is silicon carbide, the leakage current is an order of magnitude higher than when the silicon nitride layer is used as the etch stop layer, for example At a voltage of 20 volts, silicon carbide will have a leakage current lx 1 0 _9A, and if it is silicon nitride, it will only have lx 1 0 _1QA. Therefore, taking leakage current as a factor for consideration, carbonized fossils are not favorable. 473924 V. Description of the invention (3) In view of the conflict between the leakage current and the dielectric constant caused by the etching stop layer as described above, the motivation of the present invention is to propose a method for solving the above problems. Object and Summary of the Invention The object of the present invention is to provide a new etch stop layer for a dual damascene process, so as to achieve the effect of reducing the dielectric constant and reducing the leakage current. The invention relates to a method for reducing leakage current by using a silicon carbide / silicon nitride combination as an etching stop layer after a dual damascene process. The method includes the following steps: First, a substrate is provided, and the component part is completed but no dielectric is formed. Layer and at least one containing metal wire therein. Next, a first etch stop layer containing silicon carbide and silicon nitride materials is formed. The method for forming the first etch stop layer may be an e X-situ method of forming a silicon carbide layer and then forming a silicon nitride layer, or carbon The i η-situ method in which the fossil evening layer and the nitride nitride layer are formed simultaneously, or the silicon carbide layer is formed first and then subjected to nitriding treatment to form the nitride nitride layer. The three methods of forming the first engraved termination layer are all acceptable. The first layer of engraved termination layer should be noted that the carbonized layer is thicker and the nitrided layer is thinner. After that, a first Si LK layer is formed on the first etch stop layer, and a second etch stop layer such as the first etch stop layer is formed. Then, a second Si LK layer is formed on the second etch stop layer;
第7頁 473924 五、發明說明（4) $ ’再形成一硬式罩幕層於第二s i LK層上；再形成一定義 ^ &洞的光阻圖案於硬式罩幕層，隨後轉移光阻圖案至硬 =罩幕層’在去除光阻圖案後，以硬式罩幕為罩幕，蝕刻 # 一 S 1 LK層、第二蝕刻終止層、及第一 s丨LK層，停止於該 J 姓刻終止層上；再形成一光阻圖案於硬式罩幕層上以 疋義導線溝渠，再蝕刻該第二S丨並停止於第二蝕刻終 層上’同時姓刻介層洞内之該第一蝕刻終止層以露出金 麗導，再去除光阻圖案，回填介層洞及導線溝渠以金 磨終ί彳ί施以化學/機械式研磨的製程以第三介電層為研 先以Ξίΐ:洞的步驟也可以在第二姓刻終止層形成時就 後再=’即予圖：化以形成介層洞開口，之 成介声if一具有圖案之硬式罩幕層。最後再完 式研及導線溝渠的製程及回填金屬與化學/機械 發明詳細說明： φ 鐘於上述發明背景所述，雙鑲嵌製 線連接結構存在右祝μ μ uφ ^ 乂達成多層金屬 ;題有待克服。本發明為此提供有效流的衝突 去。以下之製程詳細說明，將佐以圖示以=問題的方 4,?3924 五、發明說明（5) ^ -- 請_參考如圖一所示的橫截面示意圖。提供一且有元件 ^未圖示）之基板’並覆以介電層105於其上，此外並有一 no埋入該介電層105之中，其上表面和介電層1〇5的 、面同平面。或者是一導線突出於介電層1〇5之上也可 〇 —仍請參考圖一，接著一第一蝕刻終止層115，包含一 =二碳化矽層115a及一第一氮化矽層115晚又序沉積。豆中 二，化矽層l15a厚度約100_1〇〇〇埃，典型值約5〇〇埃， ——氮化矽層115b厚約1 0 - 5 0 0埃，典型值約8〇埃。苴 蝕刻終止層Π 5的沉積方法，有三種沉積方法可以選 先沉ί :第一種方法，電漿輔助化學氣相沉積法（PE:) 積弟一碳化矽層11 5 a，接者再以相同的方、、如、_ 氮化矽層115b。 去>儿積第一 三種沉積方法中的第二種方法，係第—碳化矽声 氮化石夕層1 1 5 b同步沉積（in - situ)的方式& =終止層115。此時可以調配氣體的比例，例如 1、1^3)4;或稱4113氣體以 1 0 0- 5 0 0 0 3(：(：111的流量，另_ 體則以1 0 0 - 5 0 0 0 Sccm的流量，做適當的調配以使得^⑽氣 及氣化矽混層中之碳化矽的比例比氮化矽的比例^灭化石夕 到；|電常數接近碳化石夕，但可以達到類似氮化石夕盘而達 的有機介電層結合時，低漏電流之效果。 ” l〇w〜kPage 7 473924 V. Description of the invention (4) $ 'Another hard mask layer is formed on the second Si LK layer; a photoresist pattern defining a & hole is formed on the hard mask layer, and then the photoresist is transferred. Pattern to hard = mask layer 'After removing the photoresist pattern, the hard mask is used as the mask to etch # 1 S 1 LK layer, the second etch stop layer, and the first s 丨 LK layer, and stop at the J A photoresist pattern is formed on the hard mask layer to define a wire channel, and then the second S is stopped and stopped on the second etching final layer. At the same time, the first An etching stop layer is exposed to expose the Jin Lidao, and then the photoresist pattern is removed. The interlayer holes and wire trenches are backfilled with gold grinding. The process of chemical / mechanical polishing is performed with the third dielectric layer as the first step. The step of hole can also be done at the time of the formation of the second layer to terminate the layer formation == that is to pre-map: to form the opening of the interstitial hole, to form the intermediary sound if a hard mask layer with a pattern. Finally, we will complete the research and the process of conducting wire trenches and backfill metal and chemical / mechanical inventions in detail: φ As described in the background of the above invention, there is a right-side μ μ uφ ^ in the dual-mosaic wire connection structure to achieve multilayer metal; get over. The present invention provides efficient flow collisions for this purpose. The detailed description of the following process will be accompanied by illustrations with = question 4, 4, 3924 V. Description of the invention (5) ^-Please refer to the cross-sectional diagram shown in Figure 1. Provide a substrate with a component (not shown) and cover it with a dielectric layer 105. In addition, a substrate is buried in the dielectric layer 105, its upper surface and the dielectric layer 105, Faces are the same. Alternatively, a wire may protrude above the dielectric layer 105. Still referring to FIG. 1, a first etch stop layer 115 includes a silicon carbide layer 115a and a first silicon nitride layer 115. Late and sequential deposition. Second, the thickness of the silicon layer 115a is about 100-1000 Angstroms, a typical value is about 500 Angstroms.-The silicon nitride layer 115b is about 10-50 Angstroms thick, and the typical value is about 80 Angstroms.苴 The deposition method of the etching stop layer Π 5 can be selected from three deposition methods: the first method, plasma-assisted chemical vapor deposition (PE :), a silicon carbide layer 11 5 a, and then In the same manner, the silicon nitride layer 115b is, for example, _. The second method among the first three deposition methods is the > silicon carbide acoustic nitride nitride layer 1 1 5 b synchronous deposition (in-situ) method & = stop layer 115. At this time, the ratio of gas can be adjusted, such as 1, 1 ^ 3) 4; or 4113 gas with 1 0 0-5 0 0 0 3 (: (: 111 flow rate, and _ system with 1 0 0-5 0 The flow rate of 0 0 Sccm is appropriately adjusted so that the ratio of silicon carbide in the mixed layer of thoron gas and gasified silicon is higher than the ratio of silicon nitride ^ Fossils are coming; | The electric constant is close to that of carbides, but it can reach similar The effect of low leakage current when combined with the organic dielectric layer of nitride nitride. "L0w ~ k
第9頁 473924 五、發明說明（6) 最後的第三種沉積方法是先將 法（PECVD)先沉積第_碳化矽層u水 化學氣相沉積 。接者，在含氣氣氣= '化石夕層115a約為 .笼Μ M # a 下，施以氮化處理溫度 形成一薄層的亂化矽層丄丨5b於碳化矽層i丨5让。 在第一蝕刻終止層形成之後，以旋塗法形成一 i〇w — k 的有機介電層於上述的第一蝕刻終止層i丨5上，以一較俨 的實施例而言，係一第一 SiLI^ 12〇。第一 SiLIU| 12〇厚^ 約為 5 0 0 0 - 1 0 0 0 0埃。 接著再應用相同的方法再沉積一第二蝕刻終止層 1 2 5，第二#刻終止層1 2 5包含一第二碳化矽層1 2 5 a及一第 二氮化矽層1 2 5 b。如同第一蝕刻終止層11 5一樣，可以採 用上述的三種沉積方法進行沉積。第二蝕刻終止層的厚+度 可以猶為比第一蝕刻終止層厚一些。例如第二碳化矽層 1 2 5 a厚度約100-100 0埃’而第二氮化石夕層125 b厚約為 1 0- 5 0 0埃。 接著’再形成第二介電層’同樣也是S i LK材料的介電 層1 3 0於第二姓刻終止層1 2 5上。之後，一做為硬式罩幕材 料層1 4 0接者沉積’以^一較佳的貫施例而言，硬式罩幕材 料層140可以選用氮化矽層、氮矽氧化層、碳化矽層或cvd 氧化層其中之一種，或二種。一用以定義介層洞丨5〇的光 阻圖案1 4 5接著形成於硬式罩幕1 4 0上。Page 9 473924 V. Description of the invention (6) The last third deposition method is the first method (PECVD) to deposit the silicon carbide layer u water chemical vapor deposition first. Then, under the gas containing gas = 'fossil evening layer 115a is about. Cage M M # a, a thin layer of disordered silicon layer is formed by applying a nitriding treatment temperature 5b to the silicon carbide layer i 5 . After the first etch stop layer is formed, an organic dielectric layer of iw-k is formed on the first etch stop layer i5 by the spin coating method. First SiLI ^ 12. The first SiLIU | 12〇 thick ^ is about 5 0 0-1 0 0 0 0 Angstroms. Then, a second etching stop layer 1 2 5 is deposited again using the same method. The second #etch stop layer 1 2 5 includes a second silicon carbide layer 1 2 5 a and a second silicon nitride layer 1 2 5 b. . As with the first etch stop layer 115, the three deposition methods described above can be used for deposition. The thickness of the second etch stop layer may be thicker than the first etch stop layer. For example, the second silicon carbide layer 12 5 a has a thickness of about 100-100 Angstroms' and the second silicon nitride layer 125 b has a thickness of about 10-50 Angstroms. Next, "re-form a second dielectric layer" which is also a dielectric layer 130 of Si LK material on the second etch stop layer 1 25. After that, as a hard mask material layer 1,400, it is deposited. In a preferred embodiment, the hard mask material layer 140 may be a silicon nitride layer, a silicon nitride oxide layer, or a silicon carbide layer. Either one or two cvd oxide layers. A photoresist pattern 1 45 for defining the vias 50 is then formed on the hard mask 140.
第10頁 473924 五、發明說明（7) 仍請參考圖一所示的橫截面示意圖，利用光阻圖案 1 4 5為罩幕，先施以非等向性蝕刻、硬式罩幕材料層丨4 〇， 以轉移圖案至硬式罩幕材料層1 4 0。隨後剝除光阻圖案 145。 接著，再以硬式罩幕材料層1 40為罩幕，蝕刻第二介 電層130、第二蝕刻終止層125、及第一介電層12〇，並停 止於第一蝕刻終止層115,以形成介層洞15〇。 之後’請參考圖二，再形成一光阻圖案1 5 5於硬式罩 幕上’以定義金屬連接線溝渠丨6 0，及連接介層洞1 5 〇的金 屬連接線溝渠1 6 0。以光阻圖案1 5 5為罩幕再蝕刻介層洞 1 5 0内之第一蝕刻終止層11 5，用以露出金屬導線^ 1 〇及第 二介電層，以第二蝕刻終止層125為終止層，以分別完成 介層洞150及金屬連接線溝渠16〇。最後再沉積内連線及介 層洞的金屬而完成雙鑲嵌製程。 當然，上述的介層洞1 5 〇也可以以在第二蝕刻終止層 1 2 5形成時就先以微影及蝕刻技術，即予圖案化以形成介 層洞開口，之後再形成第二SiLi^ 13〇，具有圖案之硬式 罩幕層。最後再完成介層洞丨5 〇姓刻及導線溝渠1 7 〇的製程 及回填金屬1 3 0與進行化學/機械式研磨的製程。 473924 五、發明說明（8) 圖四係根據本發明之方法，形成之蝕刻終止層材料 (厚碳化矽層結合薄氮化矽層）搭配S i L K介電層和傳統方法 的氮化矽層或碳化矽層的漏電流比較，其中電壓約2 0伏， 可以發現本發明之蝕刻終止層之材料（厚碳化矽層結合薄 氮化矽層）的漏電流程度與氮化矽層相當，而低於以碳化 矽做為蝕刻終止層一個數量級。 以上所述僅為本發明之較佳實施例而已，並非用以限 定本發明之申請專利範圍；凡其它未脫離本發明所揭示之 精神下所完成之等效改變或修飾，均應包含在下述之申請 專利範圍内。 ❹Page 10 473924 V. Description of the invention (7) Still refer to the schematic cross-section diagram shown in Figure 1. Using the photoresist pattern 1 4 5 as the mask, first apply anisotropic etching and hard mask material layer 丨 4 〇 to transfer the pattern to the hard mask material layer 14 0. The photoresist pattern 145 is then stripped. Then, using the hard mask material layer 140 as a mask, the second dielectric layer 130, the second etch stop layer 125, and the first dielectric layer 120 are etched, and stopped at the first etch stop layer 115. Formation of a via hole 15. After that, please refer to FIG. 2, and then form a photoresist pattern 1 5 5 on the hard mask to define a metal connection line trench 60 and a metal connection line trench 160 connected to the via hole 150. The photoresist pattern 15 5 is used as a mask to re-etch the first etch stop layer 115 in the interlayer hole 150 to expose the metal wire ^ 1 〇 and the second dielectric layer, and the second etch stop layer 125 As the termination layer, the via hole 150 and the metal connection line trench 16 are completed respectively. Finally, the metal of interconnects and vias is deposited to complete the dual damascene process. Of course, the above-mentioned via hole 150 can also be patterned to form a via hole opening by lithography and etching technology when the second etch stop layer 125 is formed, and then a second SiLi is formed. ^ 13〇, patterned hard cover curtain layer. Finally, the manufacturing process of the interlayer vias and the conductive trenches and the backfill metal 130 and the chemical / mechanical polishing process are completed. 473924 V. Description of the invention (8) Figure 4 shows the etch stop layer material (thick silicon carbide layer combined with thin silicon nitride layer) formed according to the method of the present invention, with Si LK dielectric layer and the conventional method of silicon nitride layer. Or compare the leakage current of the silicon carbide layer, where the voltage is about 20 volts. It can be found that the material of the etch stop layer of the present invention (thick silicon carbide layer combined with thin silicon nitride layer) has a leakage current comparable to that of the silicon nitride layer, and An order of magnitude lower than using SiC as an etch stop. The above are merely preferred embodiments of the present invention, and are not intended to limit the scope of patent application for the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention shall be included in the following Within the scope of patent application. ❹
第12頁 473924 年/ 曰婊正/吏止/補爲 圖式簡單說明 列 下 以 輔 中 字 文 明 說 之 後 往 於 將 例 施： 實述 佳闡 較的 的細 明詳 發更 本做 形 圖一顯示依據本發明之方法形成蝕刻終止層、介電層 硬 式 罩 幕 及 光 阻 圖 案以進 行 介 層 洞 的 橫截 面 示 意圖。 圖 二 顯 示 依 據 本發明 之 方 法 形 成 光阻 圖 案 以定義 金屬 内 連 線 溝 渠 的 橫 截 面不意 圖 〇 圖 三 顯 示 依 據 以非等 向 性 Μ 刻 形 成導 線 溝 渠及介 層洞 再 完 填 的 金 屬 層 及 化學/機械式研磨製程後的橫截面示意 圖 〇 圖 四 顯 示 依 據 本發明 之 方 法 1 形 成之 名虫 刻 終止層 材料 (厚碳化矽層結合薄氮化矽層）搭 配 SiLK 介 電 層 和傳統 方法 的 氮 化 矽 層 或 碳 化 矽層的 漏 電 流 比 較 〇 圖 號 對 昭 /、、、 表 : 介 電 層 105 導 線 110 第 一 1虫 刻 終 止 層 115 第 一 介 電 層 120 第 一 碳 化 矽 層 115a 第 一 氮 化 矽 層 115b 第 二 Μ 刻 終 止 層 125 第 二 SiLK 層 130 第 二 碳 化 矽 層 125a 第 二 氮 化 矽 層 125b 光 阻 圖 案 145、 155介 層 洞 150 硬 式 罩 幕 材 料 層 140 金 屬 連 接 線 溝渠 160Page 12 473924 / Yue Zheng / Li Zhi / Supplement is a simple explanation. After the list is supplemented by the Chinese civilization theory, I will apply it to the following examples: A schematic cross-sectional view of forming an etch stop layer, a hard mask of a dielectric layer, and a photoresist pattern to perform a via hole according to the method of the present invention is shown. Figure 2 shows the photoresist pattern formed according to the method of the present invention to define the cross-section of the metal interconnecting trenches. Figure 3 shows the metal layer formed by forming the trenches and vias of the vias and filling the vias with anisotropic M inscription and Schematic cross-section view after chemical / mechanical grinding process. Figure 4 shows the etched stop layer material (thick silicon carbide layer combined with thin silicon nitride layer) formed according to the method 1 of the present invention combined with the SiLK dielectric layer and the traditional method. Comparison of the leakage current of the silicon nitride layer or silicon carbide layer. Figure No. to Zhao ,,,,, Table: Dielectric layer 105, lead 110, first 1 etch stop layer 115, first dielectric layer 120, first silicon carbide layer 115a, A silicon nitride layer 115b, a second etch stop layer 125, a second SiLK layer 130, a second silicon carbide layer 125a, a second silicon nitride layer 125b, a photoresist pattern 145, a 155 interlayer hole 150, a hard mask material Layer 140 metal connection line trench 160
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