SG121686A1 - A method to create a copper dual damascene structure with less dishing and erosion - Google Patents
A method to create a copper dual damascene structure with less dishing and erosionInfo
- Publication number
- SG121686A1 SG121686A1 SG200001290A SG200001290A SG121686A1 SG 121686 A1 SG121686 A1 SG 121686A1 SG 200001290 A SG200001290 A SG 200001290A SG 200001290 A SG200001290 A SG 200001290A SG 121686 A1 SG121686 A1 SG 121686A1
- Authority
- SG
- Singapore
- Prior art keywords
- erosion
- create
- dual damascene
- damascene structure
- copper dual
- Prior art date
Links
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title 1
- 229910052802 copper Inorganic materials 0.000 title 1
- 239000010949 copper Substances 0.000 title 1
- 230000009977 dual effect Effects 0.000 title 1
- 230000003628 erosive effect Effects 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/390,783 US6251786B1 (en) | 1999-09-07 | 1999-09-07 | Method to create a copper dual damascene structure with less dishing and erosion |
Publications (1)
Publication Number | Publication Date |
---|---|
SG121686A1 true SG121686A1 (en) | 2006-05-26 |
Family
ID=23543923
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG200001290A SG121686A1 (en) | 1999-09-07 | 2000-03-09 | A method to create a copper dual damascene structure with less dishing and erosion |
Country Status (4)
Country | Link |
---|---|
US (1) | US6251786B1 (ja) |
EP (1) | EP1083596B1 (ja) |
JP (1) | JP4266502B2 (ja) |
SG (1) | SG121686A1 (ja) |
Families Citing this family (41)
Publication number | Priority date | Publication date | Assignee | Title |
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US6455425B1 (en) * | 2000-01-18 | 2002-09-24 | Advanced Micro Devices, Inc. | Selective deposition process for passivating top interface of damascene-type Cu interconnect lines |
CN1358329A (zh) * | 2000-01-20 | 2002-07-10 | 皇家菲利浦电子有限公司 | 镶嵌结构及其制作方法 |
US6368953B1 (en) * | 2000-05-09 | 2002-04-09 | International Business Machines Corporation | Encapsulated metal structures for semiconductor devices and MIM capacitors including the same |
KR100671610B1 (ko) | 2000-10-26 | 2007-01-18 | 주식회사 하이닉스반도체 | 반도체 소자의 금속 배선 형성 방법 |
US6709874B2 (en) * | 2001-01-24 | 2004-03-23 | Infineon Technologies Ag | Method of manufacturing a metal cap layer for preventing damascene conductive lines from oxidation |
US6586326B2 (en) * | 2001-03-13 | 2003-07-01 | Lsi Logic Corporation | Metal planarization system |
JP4350337B2 (ja) * | 2001-04-27 | 2009-10-21 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置 |
KR100435784B1 (ko) * | 2001-12-21 | 2004-06-12 | 동부전자 주식회사 | 반도체 소자의 금속배선 형성 방법 |
KR100444301B1 (ko) * | 2001-12-29 | 2004-08-16 | 주식회사 하이닉스반도체 | 질화막 cmp를 이용한 다마신 금속 게이트 형성 방법 |
JP4088120B2 (ja) * | 2002-08-12 | 2008-05-21 | 株式会社ルネサステクノロジ | 半導体装置 |
US6670274B1 (en) | 2002-10-01 | 2003-12-30 | Taiwan Semiconductor Manufacturing Company | Method of forming a copper damascene structure comprising a recessed copper-oxide-free initial copper structure |
US6940108B2 (en) * | 2002-12-05 | 2005-09-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Slot design for metal interconnects |
US7825516B2 (en) * | 2002-12-11 | 2010-11-02 | International Business Machines Corporation | Formation of aligned capped metal lines and interconnections in multilevel semiconductor structures |
US6975032B2 (en) * | 2002-12-16 | 2005-12-13 | International Business Machines Corporation | Copper recess process with application to selective capping and electroless plating |
KR20040060563A (ko) * | 2002-12-30 | 2004-07-06 | 동부전자 주식회사 | 반도체 소자 제조방법 및 구조 |
US7294241B2 (en) * | 2003-01-03 | 2007-11-13 | Chartered Semiconductor Manufacturing Ltd. | Method to form alpha phase Ta and its application to IC manufacturing |
US20040185992A1 (en) * | 2003-03-18 | 2004-09-23 | Tisdale Lucien E. | Method and apparatus for making a packaging article and packaging article made by the method and apparatus |
JP4638140B2 (ja) * | 2003-07-09 | 2011-02-23 | マグナチップセミコンダクター有限会社 | 半導体素子の銅配線形成方法 |
US20050079703A1 (en) * | 2003-10-09 | 2005-04-14 | Applied Materials, Inc. | Method for planarizing an interconnect structure |
US7183199B2 (en) * | 2003-12-01 | 2007-02-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of reducing the pattern effect in the CMP process |
US20050139292A1 (en) * | 2003-12-31 | 2005-06-30 | Suresh Ramarajan | Method and apparatus for minimizing thickness-to-planarity and dishing in CMP |
US20060113675A1 (en) * | 2004-12-01 | 2006-06-01 | Chung-Liang Chang | Barrier material and process for Cu interconnect |
DE102005004384A1 (de) * | 2005-01-31 | 2006-08-10 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zur Herstellung einer definierten Vertiefung in einer Damaszener-Struktur unter Verwendung eines CMP Prozesses und eine Damaszener-Struktur |
US20060205204A1 (en) * | 2005-03-14 | 2006-09-14 | Michael Beck | Method of making a semiconductor interconnect with a metal cap |
US20070080455A1 (en) * | 2005-10-11 | 2007-04-12 | International Business Machines Corporation | Semiconductors and methods of making |
KR100729126B1 (ko) * | 2005-11-15 | 2007-06-14 | 동부일렉트로닉스 주식회사 | 반도체 소자의 금속 배선 및 그 형성 방법 |
US7432205B2 (en) * | 2005-12-15 | 2008-10-07 | United Microelectronics Corp. | Method for controlling polishing process |
US7863183B2 (en) * | 2006-01-18 | 2011-01-04 | International Business Machines Corporation | Method for fabricating last level copper-to-C4 connection with interfacial cap structure |
US7619310B2 (en) * | 2006-11-03 | 2009-11-17 | Infineon Technologies Ag | Semiconductor interconnect and method of making same |
US7893459B2 (en) * | 2007-04-10 | 2011-02-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Seal ring structures with reduced moisture-induced reliability degradation |
US20090039512A1 (en) * | 2007-08-08 | 2009-02-12 | International Business Machines Corporation | Electromigration resistant interconnect structure |
US20090200668A1 (en) * | 2008-02-07 | 2009-08-13 | International Business Machines Corporation | Interconnect structure with high leakage resistance |
EP2345069B1 (en) * | 2008-10-27 | 2016-02-17 | Nxp B.V. | Method of manufacturing a biocompatible electrode |
US8629063B2 (en) | 2011-06-08 | 2014-01-14 | International Business Machines Corporation | Forming features on a substrate having varying feature densities |
KR102085086B1 (ko) | 2013-10-29 | 2020-03-05 | 삼성전자주식회사 | 반도체 장치 및 그 제조방법 |
US10211278B2 (en) * | 2017-07-11 | 2019-02-19 | Texas Instruments Incorporated | Device and method for a thin film resistor using a via retardation layer |
US11018087B2 (en) | 2018-04-25 | 2021-05-25 | International Business Machines Corporation | Metal interconnects |
US11282788B2 (en) | 2019-07-25 | 2022-03-22 | International Business Machines Corporation | Interconnect and memory structures formed in the BEOL |
US11195751B2 (en) | 2019-09-13 | 2021-12-07 | International Business Machines Corporation | Bilayer barrier for interconnect and memory structures formed in the BEOL |
FR3113125B1 (fr) * | 2020-07-29 | 2022-07-29 | Lynred | Procede de realisation d’un micro-bolometre d’imagerie infrarouge et micro-bolometre associe |
TW202225649A (zh) * | 2020-07-29 | 2022-07-01 | 法商林銳股份有限公司 | 紅外線成像微測輻射熱計及相關形成方法 |
Family Cites Families (16)
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JP3297220B2 (ja) * | 1993-10-29 | 2002-07-02 | 株式会社東芝 | 半導体装置の製造方法および半導体装置 |
KR0138305B1 (ko) * | 1994-11-30 | 1998-06-01 | 김광호 | 반도체소자 배선형성방법 |
US5674787A (en) | 1996-01-16 | 1997-10-07 | Sematech, Inc. | Selective electroless copper deposited interconnect plugs for ULSI applications |
US5744376A (en) | 1996-04-08 | 1998-04-28 | Chartered Semiconductor Manufacturing Pte, Ltd | Method of manufacturing copper interconnect with top barrier layer |
US5741626A (en) | 1996-04-15 | 1998-04-21 | Motorola, Inc. | Method for forming a dielectric tantalum nitride layer as an anti-reflective coating (ARC) |
US5814557A (en) | 1996-05-20 | 1998-09-29 | Motorola, Inc. | Method of forming an interconnect structure |
US5723387A (en) | 1996-07-22 | 1998-03-03 | Industrial Technology Research Institute | Method and apparatus for forming very small scale Cu interconnect metallurgy on semiconductor substrates |
US5818110A (en) | 1996-11-22 | 1998-10-06 | International Business Machines Corporation | Integrated circuit chip wiring structure with crossover capability and method of manufacturing the same |
US6069068A (en) * | 1997-05-30 | 2000-05-30 | International Business Machines Corporation | Sub-quarter-micron copper interconnections with improved electromigration resistance and reduced defect sensitivity |
US5893752A (en) * | 1997-12-22 | 1999-04-13 | Motorola, Inc. | Process for forming a semiconductor device |
US5920790A (en) * | 1997-08-29 | 1999-07-06 | Motorola, Inc. | Method of forming a semiconductor device having dual inlaid structure |
US6103625A (en) * | 1997-12-31 | 2000-08-15 | Intel Corporation | Use of a polish stop layer in the formation of metal structures |
US6017803A (en) * | 1998-06-24 | 2000-01-25 | Chartered Semiconductor Manufacturing, Ltd. | Method to prevent dishing in chemical mechanical polishing |
US6083835A (en) * | 1998-07-24 | 2000-07-04 | Taiwan Semiconductor Manufacturing Company | Self-passivation of copper damascene |
US6114246A (en) * | 1999-01-07 | 2000-09-05 | Vlsi Technology, Inc. | Method of using a polish stop film to control dishing during copper chemical mechanical polishing |
US6157081A (en) * | 1999-03-10 | 2000-12-05 | Advanced Micro Devices, Inc. | High-reliability damascene interconnect formation for semiconductor fabrication |
-
1999
- 1999-09-07 US US09/390,783 patent/US6251786B1/en not_active Expired - Lifetime
-
2000
- 2000-03-09 SG SG200001290A patent/SG121686A1/en unknown
- 2000-07-18 EP EP00640007A patent/EP1083596B1/en not_active Expired - Lifetime
- 2000-08-17 JP JP2000247159A patent/JP4266502B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
EP1083596A1 (en) | 2001-03-14 |
EP1083596B1 (en) | 2012-08-22 |
JP4266502B2 (ja) | 2009-05-20 |
JP2001176879A (ja) | 2001-06-29 |
US6251786B1 (en) | 2001-06-26 |
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