SG116499A1 - Dual-gate structure and method of fabricating integrated circuits having dual-gate structures. - Google Patents

Dual-gate structure and method of fabricating integrated circuits having dual-gate structures.

Info

Publication number
SG116499A1
SG116499A1 SG200303967A SG200303967A SG116499A1 SG 116499 A1 SG116499 A1 SG 116499A1 SG 200303967 A SG200303967 A SG 200303967A SG 200303967 A SG200303967 A SG 200303967A SG 116499 A1 SG116499 A1 SG 116499A1
Authority
SG
Singapore
Prior art keywords
dual
integrated circuits
gate
fabricating integrated
gate structure
Prior art date
Application number
SG200303967A
Other languages
English (en)
Inventor
Ho Tuo-Hung
Wang Ming-Fang
Chen Chi-Chun
Yang Chin-Wei
Yao Liang-Gi
Chen Chih-Chang
Original Assignee
Taiwan Semiconductor Mfg
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Mfg filed Critical Taiwan Semiconductor Mfg
Publication of SG116499A1 publication Critical patent/SG116499A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Weting (AREA)
SG200303967A 2002-08-23 2003-07-03 Dual-gate structure and method of fabricating integrated circuits having dual-gate structures. SG116499A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/226,617 US7030024B2 (en) 2002-08-23 2002-08-23 Dual-gate structure and method of fabricating integrated circuits having dual-gate structures

Publications (1)

Publication Number Publication Date
SG116499A1 true SG116499A1 (en) 2005-11-28

Family

ID=31887285

Family Applications (1)

Application Number Title Priority Date Filing Date
SG200303967A SG116499A1 (en) 2002-08-23 2003-07-03 Dual-gate structure and method of fabricating integrated circuits having dual-gate structures.

Country Status (4)

Country Link
US (2) US7030024B2 (ja)
JP (1) JP4002868B2 (ja)
KR (1) KR100623584B1 (ja)
SG (1) SG116499A1 (ja)

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US5651855A (en) * 1992-07-28 1997-07-29 Micron Technology, Inc. Method of making self aligned contacts to silicon substrates during the manufacture of integrated circuits
KR100621542B1 (ko) * 2004-09-13 2006-09-19 삼성전자주식회사 미세 전자 소자의 다층 유전체막 및 그 제조 방법
US7588989B2 (en) 2001-02-02 2009-09-15 Samsung Electronic Co., Ltd. Dielectric multilayer structures of microelectronic devices and methods for fabricating the same
US7371633B2 (en) * 2001-02-02 2008-05-13 Samsung Electronics Co., Ltd. Dielectric layer for semiconductor device and method of manufacturing the same
US7087480B1 (en) 2002-04-18 2006-08-08 Taiwan Semiconductor Manufacturing Company, Ltd. Process to make high-k transistor dielectrics
US6706581B1 (en) * 2002-10-29 2004-03-16 Taiwan Semiconductor Manufacturing Company Dual gate dielectric scheme: SiON for high performance devices and high k for low power devices
US7019351B2 (en) * 2003-03-12 2006-03-28 Micron Technology, Inc. Transistor devices, and methods of forming transistor devices and circuit devices
JP4229762B2 (ja) * 2003-06-06 2009-02-25 Ｎｅｃエレクトロニクス株式会社 半導体装置の製造方法
JP4101130B2 (ja) * 2003-07-24 2008-06-18 Ｎｅｃエレクトロニクス株式会社 半導体装置の製造方法
JP2005085822A (ja) * 2003-09-04 2005-03-31 Toshiba Corp 半導体装置
US7071122B2 (en) * 2003-12-10 2006-07-04 International Business Machines Corporation Field effect transistor with etched-back gate dielectric
JP4546201B2 (ja) * 2004-03-17 2010-09-15 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US8399934B2 (en) * 2004-12-20 2013-03-19 Infineon Technologies Ag Transistor device
DE102004040943B4 (de) * 2004-08-24 2008-07-31 Qimonda Ag Verfahren zur selektiven Abscheidung einer Schicht mittels eines ALD-Verfahrens
US7384880B2 (en) * 2004-10-12 2008-06-10 Intel Corporation Method for making a semiconductor device having a high-k gate dielectric
US7564108B2 (en) * 2004-12-20 2009-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Nitrogen treatment to improve high-k gate dielectrics
JP2006179635A (ja) * 2004-12-22 2006-07-06 Nec Electronics Corp Ｃｍｏｓ半導体装置
US8404594B2 (en) * 2005-05-27 2013-03-26 Freescale Semiconductor, Inc. Reverse ALD
US20070066021A1 (en) * 2005-09-16 2007-03-22 Texas Instruments Inc. Formation of gate dielectrics with uniform nitrogen distribution
JP2007088301A (ja) * 2005-09-22 2007-04-05 Toshiba Corp 半導体装置および半導体装置の製造方法
JP5234301B2 (ja) * 2005-10-03 2013-07-10 Ｎｌｔテクノロジー株式会社 薄膜トランジスタ、薄膜トランジスタアレイ基板、液晶表示装置およびそれらの製造方法
KR100827435B1 (ko) * 2006-01-31 2008-05-06 삼성전자주식회사 반도체 소자에서 무산소 애싱 공정을 적용한 게이트 형성방법
US20080237694A1 (en) * 2007-03-27 2008-10-02 Michael Specht Integrated circuit, cell, cell arrangement, method for manufacturing an integrated circuit, method for manufacturing a cell, memory module
US7998820B2 (en) 2007-08-07 2011-08-16 Taiwan Semiconductor Manufacturing Company, Ltd. High-k gate dielectric and method of manufacture
US7709331B2 (en) * 2007-09-07 2010-05-04 Freescale Semiconductor, Inc. Dual gate oxide device integration
US20090137119A1 (en) * 2007-11-28 2009-05-28 Taiwan Semiconductor Manufacturing Co., Ltd. Novel seal isolation liner for use in contact hole formation
JP2009141168A (ja) * 2007-12-07 2009-06-25 Panasonic Corp 半導体装置及びその製造方法
JP2010147104A (ja) * 2008-12-16 2010-07-01 Toshiba Corp 半導体装置の製造方法
US8105892B2 (en) * 2009-08-18 2012-01-31 International Business Machines Corporation Thermal dual gate oxide device integration
JP2010118677A (ja) * 2010-01-15 2010-05-27 Renesas Technology Corp 半導体装置
JP5521726B2 (ja) * 2010-04-16 2014-06-18 富士通セミコンダクター株式会社 半導体装置及びその製造方法
US9373501B2 (en) * 2013-04-16 2016-06-21 International Business Machines Corporation Hydroxyl group termination for nucleation of a dielectric metallic oxide
KR102365687B1 (ko) 2015-04-21 2022-02-21 삼성전자주식회사 집적회로 소자 및 그 제조 방법
CN105845623B (zh) * 2016-04-19 2019-02-22 昆山龙腾光电有限公司 Tft阵列基板上多次开接触孔的制作方法

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US6030862A (en) * 1998-10-13 2000-02-29 Advanced Micro Devices, Inc. Dual gate oxide formation with minimal channel dopant diffusion
US6063670A (en) * 1997-04-30 2000-05-16 Texas Instruments Incorporated Gate fabrication processes for split-gate transistors
KR20010038795A (ko) * 1999-10-27 2001-05-15 윤종용 반도체 소자의 두께가 서로 다른 이중 게이트 산화막 형성 방법
US6261978B1 (en) * 1999-02-22 2001-07-17 Motorola, Inc. Process for forming semiconductor device with thick and thin films
US6268251B1 (en) * 2000-07-12 2001-07-31 Chartered Semiconductor Manufacturing Inc. Method of forming MOS/CMOS devices with dual or triple gate oxide
US6368923B1 (en) * 2000-04-20 2002-04-09 United Microelectronics Corp. Method of fabricating a dual metal gate having two different gate dielectric layers

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JP3407204B2 (ja) * 1992-07-23 2003-05-19 オリンパス光学工業株式会社 強誘電体集積回路及びその製造方法
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US6262456B1 (en) 1998-11-06 2001-07-17 Advanced Micro Devices, Inc. Integrated circuit having transistors with different threshold voltages
US6210999B1 (en) 1998-12-04 2001-04-03 Advanced Micro Devices, Inc. Method and test structure for low-temperature integration of high dielectric constant gate dielectrics into self-aligned semiconductor devices
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US6297103B1 (en) 2000-02-28 2001-10-02 Micron Technology, Inc. Structure and method for dual gate oxide thicknesses
US6475911B1 (en) * 2000-08-16 2002-11-05 Micron Technology, Inc. Method of forming noble metal pattern
US6518106B2 (en) * 2001-05-26 2003-02-11 Motorola, Inc. Semiconductor device and a method therefor
US6524908B2 (en) * 2001-06-01 2003-02-25 International Business Machines Corporation Method for forming refractory metal-silicon-nitrogen capacitors and structures formed
US6656852B2 (en) * 2001-12-06 2003-12-02 Texas Instruments Incorporated Method for the selective removal of high-k dielectrics
US6660578B1 (en) * 2002-04-08 2003-12-09 Advanced Micro Devices, Inc. High-K dielectric having barrier layer for P-doped devices and method of fabrication
US6764898B1 (en) * 2002-05-16 2004-07-20 Advanced Micro Devices, Inc. Implantation into high-K dielectric material after gate etch to facilitate removal

Patent Citations (6)

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US6063670A (en) * 1997-04-30 2000-05-16 Texas Instruments Incorporated Gate fabrication processes for split-gate transistors
US6030862A (en) * 1998-10-13 2000-02-29 Advanced Micro Devices, Inc. Dual gate oxide formation with minimal channel dopant diffusion
US6261978B1 (en) * 1999-02-22 2001-07-17 Motorola, Inc. Process for forming semiconductor device with thick and thin films
KR20010038795A (ko) * 1999-10-27 2001-05-15 윤종용 반도체 소자의 두께가 서로 다른 이중 게이트 산화막 형성 방법
US6368923B1 (en) * 2000-04-20 2002-04-09 United Microelectronics Corp. Method of fabricating a dual metal gate having two different gate dielectric layers
US6268251B1 (en) * 2000-07-12 2001-07-31 Chartered Semiconductor Manufacturing Inc. Method of forming MOS/CMOS devices with dual or triple gate oxide

Also Published As

Publication number Publication date
US7030024B2 (en) 2006-04-18
KR20040018225A (ko) 2004-03-02
JP2004253767A (ja) 2004-09-09
JP4002868B2 (ja) 2007-11-07
KR100623584B1 (ko) 2006-09-18
US20060091469A1 (en) 2006-05-04
US7271450B2 (en) 2007-09-18
US20040038538A1 (en) 2004-02-26

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