SG11202109929XA - Process for transferring a useful layer to a carrier substrate - Google Patents

Process for transferring a useful layer to a carrier substrate

Info

Publication number
SG11202109929XA
SG11202109929XA SG11202109929XA SG11202109929XA SG 11202109929X A SG11202109929X A SG 11202109929XA SG 11202109929X A SG11202109929X A SG 11202109929XA SG 11202109929X A SG11202109929X A SG 11202109929XA
Authority
SG
Singapore
Prior art keywords
transferring
carrier substrate
useful layer
useful
layer
Prior art date
Application number
Other languages
English (en)
Inventor
Didier Landru
Oleg Kononchuk
Mohamed Nadia Ben
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Publication of SG11202109929XA publication Critical patent/SG11202109929XA/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/7806Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices involving the separation of the active layers from a substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Recrystallisation Techniques (AREA)
  • Laminated Bodies (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
SG11202109929X 2019-03-15 2020-02-26 Process for transferring a useful layer to a carrier substrate SG11202109929XA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1902671A FR3093860B1 (fr) 2019-03-15 2019-03-15 Procédé de transfert d’une couche utile sur un substrat support
PCT/FR2020/050368 WO2020188168A1 (fr) 2019-03-15 2020-02-26 Procede de transfert d'une couche utile sur un substrat support

Publications (1)

Publication Number Publication Date
SG11202109929XA true SG11202109929XA (en) 2021-10-28

Family

ID=67384009

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11202109929X SG11202109929XA (en) 2019-03-15 2020-02-26 Process for transferring a useful layer to a carrier substrate

Country Status (9)

Country Link
US (1) US11881429B2 (fr)
EP (1) EP3939077A1 (fr)
JP (1) JP7510434B2 (fr)
KR (1) KR20210134783A (fr)
CN (1) CN113491005A (fr)
FR (1) FR3093860B1 (fr)
SG (1) SG11202109929XA (fr)
TW (1) TW202036783A (fr)
WO (1) WO2020188168A1 (fr)

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070277269A1 (en) * 2006-04-17 2007-11-29 Ceres, Inc. Nucleotide sequences and polypeptides encoded thereby useful for modifying plant characteristics
FR2861497B1 (fr) 2003-10-28 2006-02-10 Soitec Silicon On Insulator Procede de transfert catastrophique d'une couche fine apres co-implantation
US20060014363A1 (en) * 2004-03-05 2006-01-19 Nicolas Daval Thermal treatment of a semiconductor layer
FR2910179B1 (fr) 2006-12-19 2009-03-13 Commissariat Energie Atomique PROCEDE DE FABRICATION DE COUCHES MINCES DE GaN PAR IMPLANTATION ET RECYCLAGE D'UN SUBSTRAT DE DEPART
JP5703853B2 (ja) 2011-03-04 2015-04-22 信越半導体株式会社 貼り合わせウェーハの製造方法
FR2982071B1 (fr) 2011-10-27 2014-05-16 Commissariat Energie Atomique Procede de lissage d'une surface par traitement thermique
JP2013143407A (ja) * 2012-01-06 2013-07-22 Shin Etsu Handotai Co Ltd 貼り合わせsoiウェーハの製造方法
FR2995441B1 (fr) * 2012-09-07 2015-11-06 Soitec Silicon On Insulator Dispositif de separation de deux substrats
FR3020175B1 (fr) * 2014-04-16 2016-05-13 Soitec Silicon On Insulator Procede de transfert d'une couche utile

Also Published As

Publication number Publication date
JP2022525162A (ja) 2022-05-11
US11881429B2 (en) 2024-01-23
US20220157651A1 (en) 2022-05-19
KR20210134783A (ko) 2021-11-10
FR3093860B1 (fr) 2021-03-05
WO2020188168A1 (fr) 2020-09-24
CN113491005A (zh) 2021-10-08
EP3939077A1 (fr) 2022-01-19
FR3093860A1 (fr) 2020-09-18
TW202036783A (zh) 2020-10-01
JP7510434B2 (ja) 2024-07-03

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