SG11202109934RA - Process for fabricating a semiconductor-on-insulator substrate - Google Patents
Process for fabricating a semiconductor-on-insulator substrateInfo
- Publication number
- SG11202109934RA SG11202109934RA SG11202109934RA SG11202109934RA SG 11202109934R A SG11202109934R A SG 11202109934RA SG 11202109934R A SG11202109934R A SG 11202109934RA SG 11202109934R A SG11202109934R A SG 11202109934RA
- Authority
- SG
- Singapore
- Prior art keywords
- fabricating
- semiconductor
- insulator substrate
- insulator
- substrate
- Prior art date
Links
- 239000012212 insulator Substances 0.000 title 1
- 239000000758 substrate Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
- H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Pressure Welding/Diffusion-Bonding (AREA)
- Recrystallisation Techniques (AREA)
- Element Separation (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1903387A FR3094563A1 (en) | 2019-03-29 | 2019-03-29 | MANUFACTURING PROCESS OF A SEMICONDUCTOR SUBSTRATE ON INSULATION |
PCT/EP2020/058529 WO2020201003A1 (en) | 2019-03-29 | 2020-03-26 | Method for manufacturing a semiconductor-on-insulator substrate |
Publications (1)
Publication Number | Publication Date |
---|---|
SG11202109934RA true SG11202109934RA (en) | 2021-10-28 |
Family
ID=67742638
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG11202109934R SG11202109934RA (en) | 2019-03-29 | 2020-03-26 | Process for fabricating a semiconductor-on-insulator substrate |
Country Status (9)
Country | Link |
---|---|
US (1) | US20220139768A1 (en) |
EP (1) | EP3948941B1 (en) |
JP (1) | JP7535058B2 (en) |
KR (1) | KR20210139456A (en) |
CN (1) | CN113597668B (en) |
FR (1) | FR3094563A1 (en) |
SG (1) | SG11202109934RA (en) |
TW (1) | TWI828893B (en) |
WO (1) | WO2020201003A1 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR3135820B1 (en) * | 2022-05-18 | 2024-04-26 | Commissariat Energie Atomique | Method for transferring a layer from a source substrate to a destination substrate |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2839147B1 (en) | 2002-04-30 | 2004-07-09 | Soitec Silicon On Insulator | DEVICE AND METHOD FOR AUTOMATICALLY CONTROLLING THE CONDITION OF THE PLATE SURFACE BY MEASURING THE ADHESIVE SPEED |
WO2007047536A2 (en) | 2005-10-14 | 2007-04-26 | Silicon Genesis Corporation | Method and apparatus for flag-less wafer bonding tool |
FR2894067B1 (en) * | 2005-11-28 | 2008-02-15 | Soitec Silicon On Insulator | METHOD OF BONDING BY MOLECULAR ADHESION |
US7601271B2 (en) | 2005-11-28 | 2009-10-13 | S.O.I.Tec Silicon On Insulator Technologies | Process and equipment for bonding by molecular adhesion |
FR2912839B1 (en) * | 2007-02-16 | 2009-05-15 | Soitec Silicon On Insulator | IMPROVING THE QUALITY OF COLD CLEANING INTERFACE BY COLD CLEANING AND HOT COLLAGE |
JP2011029609A (en) * | 2009-06-26 | 2011-02-10 | Semiconductor Energy Lab Co Ltd | Method for manufacturing soi substrate, and soi substrate |
FR2963157B1 (en) | 2010-07-22 | 2013-04-26 | Soitec Silicon On Insulator | METHOD AND APPARATUS FOR BONDING BY MOLECULAR ADHESION OF TWO PLATES |
FR2990054B1 (en) * | 2012-04-27 | 2014-05-02 | Commissariat Energie Atomique | METHOD FOR BONDING IN A GAS ATMOSPHERE HAVING A NEGATIVE JOULE-THOMSON COEFFICIENT |
KR20230136681A (en) * | 2013-05-29 | 2023-09-26 | 에베 그룹 에. 탈너 게엠베하 | Device and method for bonding substrates |
US9837291B2 (en) * | 2014-01-24 | 2017-12-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer processing method and apparatus |
FR3020175B1 (en) * | 2014-04-16 | 2016-05-13 | Soitec Silicon On Insulator | METHOD OF TRANSFERRING A USEFUL LAYER |
TW201826333A (en) * | 2016-11-16 | 2018-07-16 | 日商尼康股份有限公司 | Bonding method, bonding device, and holding member |
-
2019
- 2019-03-29 FR FR1903387A patent/FR3094563A1/en active Pending
-
2020
- 2020-03-26 WO PCT/EP2020/058529 patent/WO2020201003A1/en unknown
- 2020-03-26 TW TW109110307A patent/TWI828893B/en active
- 2020-03-26 EP EP20713004.8A patent/EP3948941B1/en active Active
- 2020-03-26 KR KR1020217035050A patent/KR20210139456A/en active Search and Examination
- 2020-03-26 SG SG11202109934R patent/SG11202109934RA/en unknown
- 2020-03-26 CN CN202080021426.9A patent/CN113597668B/en active Active
- 2020-03-26 JP JP2021557505A patent/JP7535058B2/en active Active
- 2020-03-26 US US17/435,017 patent/US20220139768A1/en active Pending
Also Published As
Publication number | Publication date |
---|---|
JP2022526167A (en) | 2022-05-23 |
EP3948941A1 (en) | 2022-02-09 |
FR3094563A1 (en) | 2020-10-02 |
JP7535058B2 (en) | 2024-08-15 |
US20220139768A1 (en) | 2022-05-05 |
TW202103263A (en) | 2021-01-16 |
CN113597668B (en) | 2024-09-13 |
TWI828893B (en) | 2024-01-11 |
EP3948941B1 (en) | 2023-03-22 |
KR20210139456A (en) | 2021-11-22 |
CN113597668A (en) | 2021-11-02 |
WO2020201003A1 (en) | 2020-10-08 |
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