SG11202109934RA - Process for fabricating a semiconductor-on-insulator substrate - Google Patents

Process for fabricating a semiconductor-on-insulator substrate

Info

Publication number
SG11202109934RA
SG11202109934RA SG11202109934RA SG11202109934RA SG 11202109934R A SG11202109934R A SG 11202109934RA SG 11202109934R A SG11202109934R A SG 11202109934RA SG 11202109934R A SG11202109934R A SG 11202109934RA
Authority
SG
Singapore
Prior art keywords
fabricating
semiconductor
insulator substrate
insulator
substrate
Prior art date
Application number
Inventor
Marcel Broekaart
Arnaud Castex
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Publication of SG11202109934RA publication Critical patent/SG11202109934RA/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185Joining of semiconductor bodies for junction formation
    • H01L21/187Joining of semiconductor bodies for junction formation by direct bonding

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Recrystallisation Techniques (AREA)
  • Element Separation (AREA)
SG11202109934R 2019-03-29 2020-03-26 Process for fabricating a semiconductor-on-insulator substrate SG11202109934RA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1903387A FR3094563A1 (en) 2019-03-29 2019-03-29 MANUFACTURING PROCESS OF A SEMICONDUCTOR SUBSTRATE ON INSULATION
PCT/EP2020/058529 WO2020201003A1 (en) 2019-03-29 2020-03-26 Method for manufacturing a semiconductor-on-insulator substrate

Publications (1)

Publication Number Publication Date
SG11202109934RA true SG11202109934RA (en) 2021-10-28

Family

ID=67742638

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11202109934R SG11202109934RA (en) 2019-03-29 2020-03-26 Process for fabricating a semiconductor-on-insulator substrate

Country Status (9)

Country Link
US (1) US20220139768A1 (en)
EP (1) EP3948941B1 (en)
JP (1) JP7535058B2 (en)
KR (1) KR20210139456A (en)
CN (1) CN113597668B (en)
FR (1) FR3094563A1 (en)
SG (1) SG11202109934RA (en)
TW (1) TWI828893B (en)
WO (1) WO2020201003A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3135820B1 (en) * 2022-05-18 2024-04-26 Commissariat Energie Atomique Method for transferring a layer from a source substrate to a destination substrate

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2839147B1 (en) 2002-04-30 2004-07-09 Soitec Silicon On Insulator DEVICE AND METHOD FOR AUTOMATICALLY CONTROLLING THE CONDITION OF THE PLATE SURFACE BY MEASURING THE ADHESIVE SPEED
WO2007047536A2 (en) 2005-10-14 2007-04-26 Silicon Genesis Corporation Method and apparatus for flag-less wafer bonding tool
FR2894067B1 (en) * 2005-11-28 2008-02-15 Soitec Silicon On Insulator METHOD OF BONDING BY MOLECULAR ADHESION
US7601271B2 (en) 2005-11-28 2009-10-13 S.O.I.Tec Silicon On Insulator Technologies Process and equipment for bonding by molecular adhesion
FR2912839B1 (en) * 2007-02-16 2009-05-15 Soitec Silicon On Insulator IMPROVING THE QUALITY OF COLD CLEANING INTERFACE BY COLD CLEANING AND HOT COLLAGE
JP2011029609A (en) * 2009-06-26 2011-02-10 Semiconductor Energy Lab Co Ltd Method for manufacturing soi substrate, and soi substrate
FR2963157B1 (en) 2010-07-22 2013-04-26 Soitec Silicon On Insulator METHOD AND APPARATUS FOR BONDING BY MOLECULAR ADHESION OF TWO PLATES
FR2990054B1 (en) * 2012-04-27 2014-05-02 Commissariat Energie Atomique METHOD FOR BONDING IN A GAS ATMOSPHERE HAVING A NEGATIVE JOULE-THOMSON COEFFICIENT
KR20230136681A (en) * 2013-05-29 2023-09-26 에베 그룹 에. 탈너 게엠베하 Device and method for bonding substrates
US9837291B2 (en) * 2014-01-24 2017-12-05 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer processing method and apparatus
FR3020175B1 (en) * 2014-04-16 2016-05-13 Soitec Silicon On Insulator METHOD OF TRANSFERRING A USEFUL LAYER
TW201826333A (en) * 2016-11-16 2018-07-16 日商尼康股份有限公司 Bonding method, bonding device, and holding member

Also Published As

Publication number Publication date
JP2022526167A (en) 2022-05-23
EP3948941A1 (en) 2022-02-09
FR3094563A1 (en) 2020-10-02
JP7535058B2 (en) 2024-08-15
US20220139768A1 (en) 2022-05-05
TW202103263A (en) 2021-01-16
CN113597668B (en) 2024-09-13
TWI828893B (en) 2024-01-11
EP3948941B1 (en) 2023-03-22
KR20210139456A (en) 2021-11-22
CN113597668A (en) 2021-11-02
WO2020201003A1 (en) 2020-10-08

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