SG11202101776XA - Process for fabricating a cfet device - Google Patents

Process for fabricating a cfet device

Info

Publication number
SG11202101776XA
SG11202101776XA SG11202101776XA SG11202101776XA SG11202101776XA SG 11202101776X A SG11202101776X A SG 11202101776XA SG 11202101776X A SG11202101776X A SG 11202101776XA SG 11202101776X A SG11202101776X A SG 11202101776XA SG 11202101776X A SG11202101776X A SG 11202101776XA
Authority
SG
Singapore
Prior art keywords
fabricating
cfet device
cfet
Prior art date
Application number
SG11202101776XA
Inventor
Walter Schwarzenbach
Ludovic Ecarnot
Nicolas Daval
Bich-Yen Nguyen
Guillaume Besnard
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Publication of SG11202101776XA publication Critical patent/SG11202101776XA/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H01L21/845Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H01L21/3247Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering for altering the shape, e.g. smoothing the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H01L27/1211Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
  • Weting (AREA)
SG11202101776XA 2018-09-03 2019-09-03 Process for fabricating a cfet device SG11202101776XA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1857894A FR3085536A1 (en) 2018-09-03 2018-09-03 CFET DEVICE AND METHOD FOR MANUFACTURING SUCH A DEVICE
PCT/FR2019/052026 WO2020049251A1 (en) 2018-09-03 2019-09-03 Method for manufacturing a cfet device

Publications (1)

Publication Number Publication Date
SG11202101776XA true SG11202101776XA (en) 2021-03-30

Family

ID=67262345

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11202101776XA SG11202101776XA (en) 2018-09-03 2019-09-03 Process for fabricating a cfet device

Country Status (8)

Country Link
US (2) US11876020B2 (en)
EP (1) EP3847693B1 (en)
KR (1) KR20210049910A (en)
CN (1) CN112640090B (en)
FR (1) FR3085536A1 (en)
SG (1) SG11202101776XA (en)
TW (1) TWI814897B (en)
WO (1) WO2020049251A1 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12080608B2 (en) 2020-07-17 2024-09-03 Synopsys, Inc. Self-limiting manufacturing techniques to prevent electrical shorts in a complementary field effect transistor (CFET)
US11915984B2 (en) 2020-07-17 2024-02-27 Synopsys, Inc. Forming a wrap-around contact to connect a source or drain epitaxial growth of a complimentary field effect transistor (CFET) to a buried power rail (BPR) of the CFET
US11710634B2 (en) 2020-07-17 2023-07-25 Synopsys, Inc. Fabrication technique for forming ultra-high density integrated circuit components
US11742247B2 (en) 2020-07-17 2023-08-29 Synopsys, Inc. Epitaxial growth of source and drain materials in a complementary field effect transistor (CFET)
US11444180B2 (en) * 2020-08-09 2022-09-13 Nanya Technology Corporation Method of forming uniform fin features
US11837604B2 (en) 2021-09-22 2023-12-05 International Business Machine Corporation Forming stacked nanosheet semiconductor devices with optimal crystalline orientations around devices

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3214631B2 (en) * 1992-01-31 2001-10-02 キヤノン株式会社 Semiconductor substrate and method of manufacturing the same
EP1158581B1 (en) 1999-10-14 2016-04-27 Shin-Etsu Handotai Co., Ltd. Method for producing soi wafer
KR100668340B1 (en) * 2005-06-28 2007-01-12 삼성전자주식회사 Fin FET CMOS and method of manufacturing and memory device comprising the same
JP4604981B2 (en) * 2005-11-24 2011-01-05 ソニー株式会社 Semiconductor device and light detection method
FR2895563B1 (en) * 2005-12-22 2008-04-04 Soitec Silicon On Insulator METHOD FOR SIMPLIFYING A FINISHING SEQUENCE AND STRUCTURE OBTAINED BY THE METHOD
US7545008B2 (en) * 2006-02-03 2009-06-09 The Hong Kong University Of Science And Technology Complementary metal-oxide-semiconductor transistor structure for high density and high performance integrated circuits
US7989322B2 (en) * 2007-02-07 2011-08-02 Micron Technology, Inc. Methods of forming transistors
FR2943458B1 (en) * 2009-03-18 2011-06-10 Soitec Silicon On Insulator METHOD FOR FINISHING A "SILICON ON INSULATION" TYPE SUBSTRATE
US11374118B2 (en) * 2009-10-12 2022-06-28 Monolithic 3D Inc. Method to form a 3D integrated circuit
FR3027451B1 (en) * 2014-10-21 2016-11-04 Soitec Silicon On Insulator SUBSTRATE AND METHOD FOR MANUFACTURING SUBSTRATE
US10790281B2 (en) * 2015-12-03 2020-09-29 Intel Corporation Stacked channel structures for MOSFETs
US9755015B1 (en) * 2016-05-10 2017-09-05 Globalfoundries Inc. Air gaps formed by porous silicon removal
US9812575B1 (en) * 2016-09-15 2017-11-07 Globalfoundries Inc. Contact formation for stacked FinFETs

Also Published As

Publication number Publication date
US11876020B2 (en) 2024-01-16
CN112640090B (en) 2024-10-15
TW202018825A (en) 2020-05-16
EP3847693A1 (en) 2021-07-14
WO2020049251A1 (en) 2020-03-12
US20210202326A1 (en) 2021-07-01
CN112640090A (en) 2021-04-09
FR3085536A1 (en) 2020-03-06
EP3847693B1 (en) 2024-04-24
US20240145314A1 (en) 2024-05-02
KR20210049910A (en) 2021-05-06
TWI814897B (en) 2023-09-11

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