SG11202109798UA - Process for transferring a useful layer to a carrier substrate - Google Patents
Process for transferring a useful layer to a carrier substrateInfo
- Publication number
- SG11202109798UA SG11202109798UA SG11202109798UA SG11202109798UA SG 11202109798U A SG11202109798U A SG 11202109798UA SG 11202109798U A SG11202109798U A SG 11202109798UA SG 11202109798U A SG11202109798U A SG 11202109798UA
- Authority
- SG
- Singapore
- Prior art keywords
- transferring
- carrier substrate
- useful layer
- useful
- layer
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Recrystallisation Techniques (AREA)
- Pressure Welding/Diffusion-Bonding (AREA)
- Laminated Bodies (AREA)
- Macromolecular Compounds Obtained By Forming Nitrogen-Containing Linkages In General (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR1902668A FR3093858B1 (en) | 2019-03-15 | 2019-03-15 | Method of transferring a useful layer onto a support substrate |
| PCT/FR2020/050367 WO2020188167A1 (en) | 2019-03-15 | 2020-02-26 | Method for transferring a useful layer onto a support substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| SG11202109798UA true SG11202109798UA (en) | 2021-10-28 |
Family
ID=67384006
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| SG11202109798U SG11202109798UA (en) | 2019-03-15 | 2020-02-26 | Process for transferring a useful layer to a carrier substrate |
Country Status (9)
| Country | Link |
|---|---|
| US (1) | US20220172983A1 (en) |
| EP (1) | EP3939076A1 (en) |
| JP (1) | JP2022526250A (en) |
| KR (1) | KR20210138051A (en) |
| CN (1) | CN113574654A (en) |
| FR (1) | FR3093858B1 (en) |
| SG (1) | SG11202109798UA (en) |
| TW (1) | TWI811528B (en) |
| WO (1) | WO2020188167A1 (en) |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2861497B1 (en) | 2003-10-28 | 2006-02-10 | Soitec Silicon On Insulator | METHOD FOR CATASTROPHIC TRANSFER OF A FINE LAYER AFTER CO-IMPLANTATION |
| US8845859B2 (en) * | 2011-03-15 | 2014-09-30 | Sunedison Semiconductor Limited (Uen201334164H) | Systems and methods for cleaving a bonded wafer pair |
| CN104025277A (en) * | 2011-10-31 | 2014-09-03 | Memc电子材料有限公司 | Clamping apparatus for cleaving a bonded wafer structure and methods for cleaving |
| JP2013143407A (en) * | 2012-01-06 | 2013-07-22 | Shin Etsu Handotai Co Ltd | Method of manufacturing laminated soi wafer |
| FR2995441B1 (en) * | 2012-09-07 | 2015-11-06 | Soitec Silicon On Insulator | DEVICE FOR SEPARATING TWO SUBSTRATES |
| FR3020175B1 (en) * | 2014-04-16 | 2016-05-13 | Soitec Silicon On Insulator | METHOD OF TRANSFERRING A USEFUL LAYER |
| JP6396852B2 (en) * | 2015-06-02 | 2018-09-26 | 信越化学工業株式会社 | Method for manufacturing composite wafer having oxide single crystal thin film |
| WO2017142849A1 (en) * | 2016-02-19 | 2017-08-24 | Sunedison Semiconductor Limited | Semiconductor on insulator structure comprising a buried high resistivity layer |
-
2019
- 2019-03-15 FR FR1902668A patent/FR3093858B1/en active Active
-
2020
- 2020-02-24 TW TW109105909A patent/TWI811528B/en active
- 2020-02-26 KR KR1020217032705A patent/KR20210138051A/en unknown
- 2020-02-26 EP EP20713728.2A patent/EP3939076A1/en active Pending
- 2020-02-26 JP JP2021555272A patent/JP2022526250A/en active Pending
- 2020-02-26 CN CN202080016649.6A patent/CN113574654A/en active Pending
- 2020-02-26 US US17/436,532 patent/US20220172983A1/en active Pending
- 2020-02-26 WO PCT/FR2020/050367 patent/WO2020188167A1/en active Application Filing
- 2020-02-26 SG SG11202109798U patent/SG11202109798UA/en unknown
Also Published As
| Publication number | Publication date |
|---|---|
| FR3093858A1 (en) | 2020-09-18 |
| US20220172983A1 (en) | 2022-06-02 |
| WO2020188167A1 (en) | 2020-09-24 |
| TW202036782A (en) | 2020-10-01 |
| KR20210138051A (en) | 2021-11-18 |
| CN113574654A (en) | 2021-10-29 |
| TWI811528B (en) | 2023-08-11 |
| EP3939076A1 (en) | 2022-01-19 |
| FR3093858B1 (en) | 2021-03-05 |
| JP2022526250A (en) | 2022-05-24 |
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