SG11202009447XA - Process for transferring a layer - Google Patents
Process for transferring a layerInfo
- Publication number
- SG11202009447XA SG11202009447XA SG11202009447XA SG11202009447XA SG11202009447XA SG 11202009447X A SG11202009447X A SG 11202009447XA SG 11202009447X A SG11202009447X A SG 11202009447XA SG 11202009447X A SG11202009447X A SG 11202009447XA SG 11202009447X A SG11202009447X A SG 11202009447XA
- Authority
- SG
- Singapore
- Prior art keywords
- transferring
- layer
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR1800257A FR3079660B1 (fr) | 2018-03-29 | 2018-03-29 | Procede de transfert d'une couche |
| PCT/IB2019/000206 WO2019186267A1 (fr) | 2018-03-29 | 2019-03-27 | Procede de transfert d'une couche |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| SG11202009447XA true SG11202009447XA (en) | 2020-10-29 |
Family
ID=63407246
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| SG11202009447XA SG11202009447XA (en) | 2018-03-29 | 2019-03-27 | Process for transferring a layer |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US11501997B2 (ja) |
| EP (1) | EP3776643A1 (ja) |
| JP (1) | JP7279284B2 (ja) |
| CN (1) | CN111902927A (ja) |
| FR (1) | FR3079660B1 (ja) |
| SG (1) | SG11202009447XA (ja) |
| WO (1) | WO2019186267A1 (ja) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR3108788A1 (fr) * | 2020-03-24 | 2021-10-01 | Soitec | Procédé de fabrication d’une structure piézoélectrique pour dispositif radiofréquence et pouvant servir pour le transfert d’une couche piézoélectrique, et procédé de transfert d’une telle couche piézoélectrique |
| FR3108789B1 (fr) * | 2020-03-24 | 2023-12-08 | Soitec Silicon On Insulator | Procédé de fabrication d’une structure piézoélectrique pour dispositif radiofréquence et pouvant servir pour le transfert d’une couche piézoélectrique, et procédé de transfert d’une telle couche piézoélectrique |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2816445B1 (fr) | 2000-11-06 | 2003-07-25 | Commissariat Energie Atomique | Procede de fabrication d'une structure empilee comprenant une couche mince adherant a un substrat cible |
| JP2006258958A (ja) | 2005-03-15 | 2006-09-28 | Shibaura Mechatronics Corp | 基板接着方法及び基板接着装置 |
| JP5137461B2 (ja) * | 2007-05-15 | 2013-02-06 | 株式会社半導体エネルギー研究所 | 半導体装置 |
| FR2926672B1 (fr) * | 2008-01-21 | 2010-03-26 | Soitec Silicon On Insulator | Procede de fabrication de couches de materiau epitaxie |
| FR2940852A1 (fr) * | 2009-04-22 | 2010-07-09 | Commissariat Energie Atomique | Procede de transfert d'une couche depuis un substrat de depart vers un substrat final, par double fragilisation |
| US9184228B2 (en) | 2011-03-07 | 2015-11-10 | Sumitomo Electric Industries, Ltd. | Composite base including sintered base and base surface flattening layer, and composite substrate including that composite base and semiconductor crystalline layer |
| JP2013080896A (ja) | 2011-09-22 | 2013-05-02 | Sumitomo Chemical Co Ltd | 複合基板の製造方法および複合基板 |
| US9257339B2 (en) * | 2012-05-04 | 2016-02-09 | Silicon Genesis Corporation | Techniques for forming optoelectronic devices |
| US10582618B2 (en) * | 2014-05-16 | 2020-03-03 | The Regents Of The University Of California | Fabrication of flexible electronic devices |
| JP6454606B2 (ja) | 2015-06-02 | 2019-01-16 | 信越化学工業株式会社 | 酸化物単結晶薄膜を備えた複合ウェーハの製造方法 |
| FR3037443B1 (fr) * | 2015-06-12 | 2018-07-13 | Soitec | Heterostructure et methode de fabrication |
| CN107750400A (zh) * | 2015-06-19 | 2018-03-02 | Qmat股份有限公司 | 接合和释放层转移工艺 |
| TW201806779A (zh) * | 2016-05-16 | 2018-03-01 | 道康寧公司 | 用於顯示裝置基板處理之包括矽倍半氧烷聚合物及矽烷中至少一者的黏合劑剝離層 |
| TWI729120B (zh) * | 2016-05-16 | 2021-06-01 | 美商道康寧公司 | 包括至少一氟矽化合物之離型層 |
-
2018
- 2018-03-29 FR FR1800257A patent/FR3079660B1/fr active Active
-
2019
- 2019-03-27 WO PCT/IB2019/000206 patent/WO2019186267A1/fr active Application Filing
- 2019-03-27 JP JP2020549781A patent/JP7279284B2/ja active Active
- 2019-03-27 US US17/042,019 patent/US11501997B2/en active Active
- 2019-03-27 SG SG11202009447XA patent/SG11202009447XA/en unknown
- 2019-03-27 EP EP19721379.6A patent/EP3776643A1/fr active Pending
- 2019-03-27 CN CN201980021411.XA patent/CN111902927A/zh active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| US11501997B2 (en) | 2022-11-15 |
| FR3079660B1 (fr) | 2020-04-17 |
| EP3776643A1 (fr) | 2021-02-17 |
| FR3079660A1 (fr) | 2019-10-04 |
| JP7279284B2 (ja) | 2023-05-23 |
| WO2019186267A1 (fr) | 2019-10-03 |
| JP2021518663A (ja) | 2021-08-02 |
| US20210166968A1 (en) | 2021-06-03 |
| KR20200138320A (ko) | 2020-12-09 |
| CN111902927A (zh) | 2020-11-06 |
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