SG11202005328WA - Method for preparing the remainder of a donor substrate, substrate produced by said method, and use of such a substrate - Google Patents

Method for preparing the remainder of a donor substrate, substrate produced by said method, and use of such a substrate

Info

Publication number
SG11202005328WA
SG11202005328WA SG11202005328WA SG11202005328WA SG11202005328WA SG 11202005328W A SG11202005328W A SG 11202005328WA SG 11202005328W A SG11202005328W A SG 11202005328WA SG 11202005328W A SG11202005328W A SG 11202005328WA SG 11202005328W A SG11202005328W A SG 11202005328WA
Authority
SG
Singapore
Prior art keywords
substrate
remainder
preparing
produced
donor
Prior art date
Application number
SG11202005328WA
Other languages
English (en)
Inventor
Charlotte Drazek
Djamel Belhachemi
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Publication of SG11202005328WA publication Critical patent/SG11202005328WA/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02032—Preparing bulk and homogeneous wafers by reclaiming or re-processing
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00349—Creating layers of material on a substrate
    • B81C1/00357—Creating layers of material on a substrate involving bonding one or several substrates on a non-temporary support, e.g. another substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02021—Edge treatment, chamfering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00—Manufacture or treatment of microstructural devices or systems
    • B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0174—Manufacture or treatment of microstructural devices or systems in or on a substrate for making multi-layered devices, film deposition or growing
    • B81C2201/0191—Transfer of a layer from a carrier wafer to a device wafer
    • B81C2201/0192—Transfer of a layer from a carrier wafer to a device wafer by cleaving the carrier wafer

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Organic Low-Molecular-Weight Compounds And Preparation Thereof (AREA)
SG11202005328WA 2017-12-05 2018-11-21 Method for preparing the remainder of a donor substrate, substrate produced by said method, and use of such a substrate SG11202005328WA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1761674A FR3074608B1 (fr) 2017-12-05 2017-12-05 Procede de preparation d'un residu de substrat donneur, substrat obtenu a l'issu de ce procede, et utilisation d'un tel susbtrat
PCT/FR2018/052938 WO2019110885A1 (fr) 2017-12-05 2018-11-21 Procédé de préparation d'un résidu de substrat donneur, substrat obtenu à l'issu de ce procédé, et utilisation d'un tel substrat

Publications (1)

Publication Number Publication Date
SG11202005328WA true SG11202005328WA (en) 2020-07-29

Family

ID=62017361

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11202005328WA SG11202005328WA (en) 2017-12-05 2018-11-21 Method for preparing the remainder of a donor substrate, substrate produced by said method, and use of such a substrate

Country Status (9)

Country Link
US (2) US11542155B2 (ja)
EP (1) EP3721467B1 (ja)
JP (1) JP7252231B2 (ja)
KR (1) KR102568640B1 (ja)
CN (1) CN111527584B (ja)
FR (1) FR3074608B1 (ja)
SG (1) SG11202005328WA (ja)
TW (1) TWI773852B (ja)
WO (1) WO2019110885A1 (ja)

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11204493A (ja) * 1998-01-09 1999-07-30 Komatsu Electron Metals Co Ltd 半導体ウェハの製造方法
JP3932369B2 (ja) * 1998-04-09 2007-06-20 信越半導体株式会社 剥離ウエーハを再利用する方法および再利用に供されるシリコンウエーハ
US6093623A (en) * 1998-08-04 2000-07-25 Micron Technology, Inc. Methods for making silicon-on-insulator structures
EP1039533A3 (en) * 1999-03-22 2001-04-04 Infineon Technologies North America Corp. High performance dram and method of manufacture
KR100414193B1 (ko) * 2001-05-08 2004-01-07 주식회사 실트론 에스오아이 웨이퍼 제조용 도너 웨이퍼 가공 방법
WO2004019403A2 (en) * 2002-08-26 2004-03-04 S.O.I.Tec Silicon On Insulator Technologies Mechanical recycling of a wafer comprising a buffer layer, after having taken a layer therefrom
CN100547760C (zh) * 2002-08-26 2009-10-07 S.O.I.Tec绝缘体上硅技术公司 在已经移去薄层之后对包括缓冲层的晶片的再循环方法
FR2858875B1 (fr) * 2003-08-12 2006-02-10 Soitec Silicon On Insulator Procede de realisation de couches minces de materiau semi-conducteur a partir d'une plaquette donneuse
US7402520B2 (en) * 2004-11-26 2008-07-22 Applied Materials, Inc. Edge removal of silicon-on-insulator transfer wafer
FR2889887B1 (fr) * 2005-08-16 2007-11-09 Commissariat Energie Atomique Procede de report d'une couche mince sur un support
US7781309B2 (en) * 2005-12-22 2010-08-24 Sumco Corporation Method for manufacturing direct bonded SOI wafer and direct bonded SOI wafer manufactured by the method
EP2015354A1 (en) * 2007-07-11 2009-01-14 S.O.I.Tec Silicon on Insulator Technologies Method for recycling a substrate, laminated wafer fabricating method and suitable recycled donor substrate
US20090278233A1 (en) * 2007-07-26 2009-11-12 Pinnington Thomas Henry Bonded intermediate substrate and method of making same
WO2009058245A2 (en) * 2007-10-31 2009-05-07 Corning Incorporated Improved substrate compositions and methods for forming semiconductor on insulator devices
EP2213415A1 (en) * 2009-01-29 2010-08-04 S.O.I. TEC Silicon Device for polishing the edge of a semiconductor substrate
EP2219208B1 (en) 2009-02-12 2012-08-29 Soitec Method for reclaiming a surface of a substrate
WO2011055769A1 (en) * 2009-11-06 2011-05-12 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor element and semiconductor device, and deposition apparatus
US8952496B2 (en) * 2009-12-24 2015-02-10 Sumco Corporation Semiconductor wafer and method of producing same
US8852391B2 (en) * 2010-06-21 2014-10-07 Brewer Science Inc. Method and apparatus for removing a reversibly mounted device wafer from a carrier substrate
US20120052623A1 (en) * 2010-08-31 2012-03-01 Twin Creeks Technologies, Inc. Method to adhere a lamina to a receiver element using glass frit paste
KR20130043063A (ko) * 2011-10-19 2013-04-29 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 반도체 장치의 제작 방법
US20140113452A1 (en) * 2012-10-18 2014-04-24 United Microelectronics Corp. Wafer edge trimming method
US9966248B2 (en) * 2015-01-05 2018-05-08 Toshiba Memory Corporation Semiconductor manufacturing apparatus and semiconductor manufacturing method
US9859458B2 (en) * 2015-06-19 2018-01-02 QMAT, Inc. Bond and release layer transfer process
US9773705B2 (en) * 2015-06-30 2017-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET channel on oxide structures and related methods
US10090210B2 (en) * 2015-10-01 2018-10-02 Sensor Electronic Technology, Inc. Material growth with temperature controlled layer
US10199216B2 (en) * 2015-12-24 2019-02-05 Infineon Technologies Austria Ag Semiconductor wafer and method
FR3051968B1 (fr) * 2016-05-25 2018-06-01 Soitec Procede de fabrication d'un substrat semi-conducteur a haute resistivite
US20180033609A1 (en) * 2016-07-28 2018-02-01 QMAT, Inc. Removal of non-cleaved/non-transferred material from donor substrate
US10818488B2 (en) * 2017-11-13 2020-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer structure and trimming method thereof

Also Published As

Publication number Publication date
EP3721467A1 (fr) 2020-10-14
EP3721467B1 (fr) 2021-12-29
KR20200090812A (ko) 2020-07-29
KR102568640B1 (ko) 2023-08-22
CN111527584B (zh) 2023-09-05
US20200385265A1 (en) 2020-12-10
US20230073003A1 (en) 2023-03-09
FR3074608A1 (fr) 2019-06-07
TW201926407A (zh) 2019-07-01
FR3074608B1 (fr) 2019-12-06
CN111527584A (zh) 2020-08-11
US11542155B2 (en) 2023-01-03
WO2019110885A1 (fr) 2019-06-13
JP7252231B2 (ja) 2023-04-04
TWI773852B (zh) 2022-08-11
JP2021506122A (ja) 2021-02-18

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