SG11201708367SA - Package assembly with gathered insulated wires - Google Patents

Package assembly with gathered insulated wires

Info

Publication number
SG11201708367SA
SG11201708367SA SG11201708367SA SG11201708367SA SG11201708367SA SG 11201708367S A SG11201708367S A SG 11201708367SA SG 11201708367S A SG11201708367S A SG 11201708367SA SG 11201708367S A SG11201708367S A SG 11201708367SA SG 11201708367S A SG11201708367S A SG 11201708367SA
Authority
SG
Singapore
Prior art keywords
gathered
package assembly
insulated wires
insulated
wires
Prior art date
Application number
SG11201708367SA
Other languages
English (en)
Inventor
Gong Ouyang
Beom-Taek Lee
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of SG11201708367SA publication Critical patent/SG11201708367SA/en

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    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
SG11201708367SA 2015-06-26 2015-06-26 Package assembly with gathered insulated wires SG11201708367SA (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2015/038109 WO2016209286A1 (en) 2015-06-26 2015-06-26 Package assembly with gathered insulated wires

Publications (1)

Publication Number Publication Date
SG11201708367SA true SG11201708367SA (en) 2018-01-30

Family

ID=57585304

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201708367SA SG11201708367SA (en) 2015-06-26 2015-06-26 Package assembly with gathered insulated wires

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Country Link
US (1) US9935036B2 (zh)
EP (1) EP3314651B1 (zh)
JP (1) JP2018518828A (zh)
KR (1) KR102422980B1 (zh)
CN (1) CN108064417B (zh)
SG (1) SG11201708367SA (zh)
TW (1) TWI741983B (zh)
WO (1) WO2016209286A1 (zh)

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Publication number Priority date Publication date Assignee Title
US10734321B2 (en) 2017-09-28 2020-08-04 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit and method of manufacturing same
WO2020004153A1 (ja) * 2018-06-27 2020-01-02 三菱電機株式会社 パワーモジュール及びその製造方法並びに電力変換装置
JP6971952B2 (ja) 2018-11-07 2021-11-24 三菱電機株式会社 半導体装置
TWI763110B (zh) * 2020-11-04 2022-05-01 瑞昱半導體股份有限公司 球柵陣列封裝及其封裝基板

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5818949A (ja) * 1981-07-28 1983-02-03 Nec Corp 半導体装置
JP2880734B2 (ja) * 1989-08-31 1999-04-12 株式会社東芝 集積回路及びその接続回路
JP3690342B2 (ja) * 2001-12-10 2005-08-31 凸版印刷株式会社 ボンディングワイヤ及びそれを用いた半導体装置
JP4271435B2 (ja) * 2002-12-09 2009-06-03 シャープ株式会社 半導体装置
US20040119172A1 (en) * 2002-12-18 2004-06-24 Downey Susan H. Packaged IC using insulated wire
US6812580B1 (en) * 2003-06-09 2004-11-02 Freescale Semiconductor, Inc. Semiconductor package having optimized wire bond positioning
US20060175712A1 (en) 2005-02-10 2006-08-10 Microbonds, Inc. High performance IC package and method
US7675168B2 (en) * 2005-02-25 2010-03-09 Agere Systems Inc. Integrated circuit with staggered differential wire bond pairs
US7626123B2 (en) * 2005-12-12 2009-12-01 Raytheon Sarcos, Llc Electrical microfilament to circuit interface
US7538413B2 (en) * 2006-12-28 2009-05-26 Micron Technology, Inc. Semiconductor components having through interconnects
US7825527B2 (en) * 2008-06-13 2010-11-02 Altera Corporation Return loss techniques in wirebond packages for high-speed data communications
US7718471B1 (en) * 2008-11-12 2010-05-18 White Electronic Designs Corporation Method and apparatus for stacked die package with insulated wire bonds
US9184151B2 (en) * 2011-03-11 2015-11-10 Cypress Semiconductor Corporation Mixed wire bonding profile and pad-layout configurations in IC packaging processes for high-speed electronic devices
US8723338B2 (en) * 2012-08-15 2014-05-13 Stats Chippac Ltd. Integrated circuit packaging system with array contacts and method of manufacture thereof
US9078352B2 (en) * 2012-10-29 2015-07-07 Avago Technologies General Ip (Singapore) Pte. Ltd. Low inductance flex bond with low thermal resistance
US9613877B2 (en) 2013-10-10 2017-04-04 UTAC Headquarters Pte. Ltd. Semiconductor packages and methods for forming semiconductor package

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Publication number Publication date
EP3314651A4 (en) 2018-12-12
CN108064417B (zh) 2022-01-18
KR102422980B1 (ko) 2022-07-19
EP3314651B1 (en) 2023-04-19
TW201711151A (zh) 2017-03-16
CN108064417A (zh) 2018-05-22
JP2018518828A (ja) 2018-07-12
KR20180021138A (ko) 2018-02-28
WO2016209286A1 (en) 2016-12-29
EP3314651A1 (en) 2018-05-02
US9935036B2 (en) 2018-04-03
TWI741983B (zh) 2021-10-11
US20170207146A1 (en) 2017-07-20

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