SG11201406661YA - Method for manufacturing bonded wafer - Google Patents

Method for manufacturing bonded wafer

Info

Publication number
SG11201406661YA
SG11201406661YA SG11201406661YA SG11201406661YA SG11201406661YA SG 11201406661Y A SG11201406661Y A SG 11201406661YA SG 11201406661Y A SG11201406661Y A SG 11201406661YA SG 11201406661Y A SG11201406661Y A SG 11201406661YA SG 11201406661Y A SG11201406661Y A SG 11201406661YA
Authority
SG
Singapore
Prior art keywords
bonded wafer
manufacturing bonded
manufacturing
wafer
bonded
Prior art date
Application number
SG11201406661YA
Other languages
English (en)
Inventor
Tohru Ishizuka
Original Assignee
Shinetsu Handotai Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinetsu Handotai Kk filed Critical Shinetsu Handotai Kk
Publication of SG11201406661YA publication Critical patent/SG11201406661YA/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32412—Plasma immersion ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H01L21/6875—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by a plurality of individual support members, e.g. support posts or protrusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H01L21/02052—Wet cleaning only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
SG11201406661YA 2012-04-26 2013-04-02 Method for manufacturing bonded wafer SG11201406661YA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2012101768A JP5664592B2 (ja) 2012-04-26 2012-04-26 貼り合わせウェーハの製造方法
PCT/JP2013/002278 WO2013161188A1 (ja) 2012-04-26 2013-04-02 貼り合わせウェーハの製造方法

Publications (1)

Publication Number Publication Date
SG11201406661YA true SG11201406661YA (en) 2014-11-27

Family

ID=49482543

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201406661YA SG11201406661YA (en) 2012-04-26 2013-04-02 Method for manufacturing bonded wafer

Country Status (7)

Country Link
US (1) US9142449B2 (ja)
EP (1) EP2843686B1 (ja)
JP (1) JP5664592B2 (ja)
KR (1) KR101855812B1 (ja)
CN (1) CN104246971B (ja)
SG (1) SG11201406661YA (ja)
WO (1) WO2013161188A1 (ja)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6213046B2 (ja) * 2013-08-21 2017-10-18 信越半導体株式会社 貼り合わせウェーハの製造方法
JP6638282B2 (ja) * 2015-09-25 2020-01-29 三菱マテリアル株式会社 冷却器付き発光モジュールおよび冷却器付き発光モジュールの製造方法
US10269756B2 (en) 2017-04-21 2019-04-23 Invensas Bonding Technologies, Inc. Die processing
JP6686962B2 (ja) * 2017-04-25 2020-04-22 信越半導体株式会社 貼り合わせウェーハの製造方法
CN107633997B (zh) * 2017-08-10 2019-01-29 长江存储科技有限责任公司 一种晶圆键合方法
US10727219B2 (en) 2018-02-15 2020-07-28 Invensas Bonding Technologies, Inc. Techniques for processing devices
CN109671664A (zh) * 2018-12-14 2019-04-23 北京半导体专用设备研究所（中国电子科技集团公司第四十五研究所） 晶圆载片台
US11742314B2 (en) 2020-03-31 2023-08-29 Adeia Semiconductor Bonding Technologies Inc. Reliable hybrid bonded apparatus

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56135934A (en) * 1980-03-27 1981-10-23 Chiyou Lsi Gijutsu Kenkyu Kumiai Dry etching device
JP3134391B2 (ja) * 1991-09-19 2001-02-13 株式会社デンソー シリコン基板の接合方法
US6534380B1 (en) * 1997-07-18 2003-03-18 Denso Corporation Semiconductor substrate and method of manufacturing the same
US6335535B1 (en) * 1998-06-26 2002-01-01 Nissin Electric Co., Ltd Method for implanting negative hydrogen ion and implanting apparatus
EP2259299A1 (en) * 1999-10-14 2010-12-08 Shin-Etsu Handotai Co., Ltd. Method for manufacturing SOI wafer, and SOI wafer
JP3626933B2 (ja) 2001-02-08 2005-03-09 東京エレクトロン株式会社 基板載置台の製造方法
US7176528B2 (en) * 2003-02-18 2007-02-13 Corning Incorporated Glass-based SOI structures
JP4509488B2 (ja) * 2003-04-02 2010-07-21 株式会社Ｓｕｍｃｏ 貼り合わせ基板の製造方法
JP2006339363A (ja) 2005-06-01 2006-12-14 Bondtech Inc 表面活性化方法および表面活性化装置
JP2007173354A (ja) 2005-12-20 2007-07-05 Shin Etsu Chem Co Ltd Ｓｏｉ基板およびｓｏｉ基板の製造方法
US7791708B2 (en) * 2006-12-27 2010-09-07 Asml Netherlands B.V. Lithographic apparatus, substrate table, and method for enhancing substrate release properties
JP5433927B2 (ja) * 2007-03-14 2014-03-05 株式会社Ｓｕｍｃｏ 貼り合わせウェーハの製造方法
JP5415676B2 (ja) * 2007-05-30 2014-02-12 信越化学工業株式会社 Ｓｏｉウェーハの製造方法
JP4577382B2 (ja) 2008-03-06 2010-11-10 信越半導体株式会社 貼り合わせウェーハの製造方法
EP2200077B1 (en) * 2008-12-22 2012-12-05 Soitec Method for bonding two substrates
US8557679B2 (en) * 2010-06-30 2013-10-15 Corning Incorporated Oxygen plasma conversion process for preparing a surface for bonding
JP2012038963A (ja) 2010-08-09 2012-02-23 Sumco Corp 貼り合わせウェーハの製造方法

Also Published As

Publication number Publication date
CN104246971B (zh) 2018-06-15
US9142449B2 (en) 2015-09-22
CN104246971A (zh) 2014-12-24
JP5664592B2 (ja) 2015-02-04
KR101855812B1 (ko) 2018-05-10
JP2013229516A (ja) 2013-11-07
WO2013161188A1 (ja) 2013-10-31
EP2843686A1 (en) 2015-03-04
EP2843686A4 (en) 2016-01-20
EP2843686B1 (en) 2019-03-27
KR20150003763A (ko) 2015-01-09
US20150118825A1 (en) 2015-04-30

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