SG10201913097SA - Structure for radiofrequency applications - Google Patents
Structure for radiofrequency applicationsInfo
- Publication number
- SG10201913097SA SG10201913097SA SG10201913097SA SG10201913097SA SG10201913097SA SG 10201913097S A SG10201913097S A SG 10201913097SA SG 10201913097S A SG10201913097S A SG 10201913097SA SG 10201913097S A SG10201913097S A SG 10201913097SA SG 10201913097S A SG10201913097S A SG 10201913097SA
- Authority
- SG
- Singapore
- Prior art keywords
- radiofrequency applications
- radiofrequency
- applications
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/01—Manufacture or treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6758—Thin-film transistors [TFT] characterised by the insulating substrates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/113—Isolations within a component, i.e. internal isolations
- H10D62/115—Dielectric isolations, e.g. air gaps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/411—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by materials, geometry or structure of the substrates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Micromachines (AREA)
- Element Separation (AREA)
- Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR1655266A FR3052592B1 (fr) | 2016-06-08 | 2016-06-08 | Structure pour applications radiofrequences |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| SG10201913097SA true SG10201913097SA (en) | 2020-02-27 |
Family
ID=56511794
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| SG10201913097SA SG10201913097SA (en) | 2016-06-08 | 2017-06-06 | Structure for radiofrequency applications |
| SG11201810415PA SG11201810415PA (en) | 2016-06-08 | 2017-06-06 | Structure for radiofrequency applications |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| SG11201810415PA SG11201810415PA (en) | 2016-06-08 | 2017-06-06 | Structure for radiofrequency applications |
Country Status (8)
| Country | Link |
|---|---|
| US (3) | US10943815B2 (enExample) |
| EP (1) | EP3469627B1 (enExample) |
| JP (1) | JP7053502B2 (enExample) |
| KR (1) | KR102369549B1 (enExample) |
| FR (1) | FR3052592B1 (enExample) |
| SG (2) | SG10201913097SA (enExample) |
| TW (1) | TWI733831B (enExample) |
| WO (1) | WO2017212160A1 (enExample) |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR3052592B1 (fr) * | 2016-06-08 | 2018-05-18 | Soitec | Structure pour applications radiofrequences |
| FR3062517B1 (fr) * | 2017-02-02 | 2019-03-15 | Soitec | Structure pour application radiofrequence |
| CN110828962B (zh) | 2018-08-09 | 2021-08-03 | 财团法人工业技术研究院 | 天线阵列模块及其制造方法 |
| US10658474B2 (en) * | 2018-08-14 | 2020-05-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming thin semiconductor-on-insulator (SOI) substrates |
| FR3086096B1 (fr) * | 2018-09-14 | 2021-08-27 | Soitec Silicon On Insulator | Procede de realisation d'un substrat avance pour une integration hybride |
| US11661337B2 (en) * | 2020-10-19 | 2023-05-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Comb electrode release process for MEMS structure |
| US11658206B2 (en) * | 2020-11-13 | 2023-05-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Deep trench structure for a capacitive device |
| US20220406649A1 (en) * | 2021-06-22 | 2022-12-22 | Texas Instruments Incorporated | Passive component q factor enhancement with elevated resistance region of substrate |
| FR3126541B1 (fr) | 2021-09-02 | 2025-01-10 | Commissariat Energie Atomique | Procédé de fabrication d’une structure multicouche |
| FR3134478B1 (fr) * | 2022-04-06 | 2025-07-25 | Commissariat Energie Atomique | Substrat comprenant des vias et procédés de fabrication associés |
| FR3142289A1 (fr) * | 2022-11-23 | 2024-05-24 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Procédé de fabrication d’un empilement comprenant une couche isolante |
| CN116902904A (zh) * | 2023-07-14 | 2023-10-20 | 绍兴中芯集成电路制造股份有限公司 | 一种mems器件、mems器件的制备方法和电子装置 |
Family Cites Families (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3582890B2 (ja) * | 1995-05-23 | 2004-10-27 | 株式会社日立製作所 | 半導体装置 |
| US6312568B2 (en) * | 1999-12-07 | 2001-11-06 | Applied Materials, Inc. | Two-step AIN-PVD for improved film properties |
| KR100388011B1 (ko) * | 2000-01-17 | 2003-06-18 | 삼성전기주식회사 | GaN박막 SAW필터 및 이를 제조하는 방법 |
| US6391792B1 (en) * | 2000-05-18 | 2002-05-21 | Taiwan Semiconductor Manufacturing Co., Ltd | Multi-step chemical mechanical polish (CMP) planarizing method for forming patterned planarized aperture fill layer |
| US20090179027A1 (en) * | 2007-12-29 | 2009-07-16 | Saint-Gobain Ceramics & Plastics, Inc. | Coaxial ceramic igniter and methods of fabrication |
| US8232920B2 (en) * | 2008-08-07 | 2012-07-31 | International Business Machines Corporation | Integrated millimeter wave antenna and transceiver on a substrate |
| US8492868B2 (en) * | 2010-08-02 | 2013-07-23 | International Business Machines Corporation | Method, apparatus, and design structure for silicon-on-insulator high-bandwidth circuitry with reduced charge layer |
| CN102169552A (zh) | 2011-01-28 | 2011-08-31 | 上海集成电路研发中心有限公司 | 射频识别标签及其制造方法 |
| US9070585B2 (en) * | 2012-02-24 | 2015-06-30 | Semiconductor Components Industries, Llc | Electronic device including a trench and a conductive structure therein and a process of forming the same |
| CN103022054B (zh) * | 2012-12-21 | 2016-12-28 | 上海华虹宏力半导体制造有限公司 | 绝缘体上硅射频器件及绝缘体上硅衬底 |
| CN103077949B (zh) * | 2013-01-28 | 2016-09-14 | 上海华虹宏力半导体制造有限公司 | 绝缘体上硅射频器件及其制作方法 |
| US9373613B2 (en) * | 2013-12-31 | 2016-06-21 | Skyworks Solutions, Inc. | Amplifier voltage limiting using punch-through effect |
| EP3024020A1 (en) * | 2014-11-19 | 2016-05-25 | Nxp B.V. | Semiconductor device and method |
| WO2016209263A1 (en) * | 2015-06-26 | 2016-12-29 | Intel Corporation | GALLIUM NITRIDE (GaN) TRANSISTOR STRUCTURES ON A SUBSTRATE |
| DE112015007201T5 (de) * | 2015-12-21 | 2018-09-06 | Intel Corporation | Integrierte hf-frontend-strukturen |
| FR3052592B1 (fr) * | 2016-06-08 | 2018-05-18 | Soitec | Structure pour applications radiofrequences |
-
2016
- 2016-06-08 FR FR1655266A patent/FR3052592B1/fr active Active
-
2017
- 2017-06-06 WO PCT/FR2017/051418 patent/WO2017212160A1/fr not_active Ceased
- 2017-06-06 JP JP2018564318A patent/JP7053502B2/ja active Active
- 2017-06-06 SG SG10201913097SA patent/SG10201913097SA/en unknown
- 2017-06-06 SG SG11201810415PA patent/SG11201810415PA/en unknown
- 2017-06-06 EP EP17742463.7A patent/EP3469627B1/fr active Active
- 2017-06-06 KR KR1020187034754A patent/KR102369549B1/ko active Active
- 2017-06-06 US US16/308,602 patent/US10943815B2/en active Active
- 2017-06-07 TW TW106118833A patent/TWI733831B/zh active
-
2020
- 2020-12-02 US US17/109,978 patent/US11367650B2/en active Active
-
2022
- 2022-05-18 US US17/663,898 patent/US11923239B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| US11923239B2 (en) | 2024-03-05 |
| SG11201810415PA (en) | 2018-12-28 |
| JP7053502B2 (ja) | 2022-04-12 |
| TWI733831B (zh) | 2021-07-21 |
| EP3469627A1 (fr) | 2019-04-17 |
| US20190157137A1 (en) | 2019-05-23 |
| JP2019527925A (ja) | 2019-10-03 |
| US20210143053A1 (en) | 2021-05-13 |
| TW201806175A (zh) | 2018-02-16 |
| WO2017212160A1 (fr) | 2017-12-14 |
| EP3469627B1 (fr) | 2020-07-29 |
| FR3052592B1 (fr) | 2018-05-18 |
| US10943815B2 (en) | 2021-03-09 |
| US11367650B2 (en) | 2022-06-21 |
| KR20190017762A (ko) | 2019-02-20 |
| FR3052592A1 (fr) | 2017-12-15 |
| KR102369549B1 (ko) | 2022-03-04 |
| US20220277988A1 (en) | 2022-09-01 |
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