KR102369549B1 - 무선 주파수 애플리케이션들을 위한 구조 - Google Patents

무선 주파수 애플리케이션들을 위한 구조 Download PDF

Info

Publication number
KR102369549B1
KR102369549B1 KR1020187034754A KR20187034754A KR102369549B1 KR 102369549 B1 KR102369549 B1 KR 102369549B1 KR 1020187034754 A KR1020187034754 A KR 1020187034754A KR 20187034754 A KR20187034754 A KR 20187034754A KR 102369549 B1 KR102369549 B1 KR 102369549B1
Authority
KR
South Korea
Prior art keywords
substrate
radio frequency
frequency devices
trenches
microelectronic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
KR1020187034754A
Other languages
English (en)
Korean (ko)
Other versions
KR20190017762A (ko
Inventor
에릭 데보네
이오누트 라두
올레그 코논추크
장-피에르 라스킨
Original Assignee
소이텍
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 소이텍 filed Critical 소이텍
Publication of KR20190017762A publication Critical patent/KR20190017762A/ko
Application granted granted Critical
Publication of KR102369549B1 publication Critical patent/KR102369549B1/ko
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283Lateral isolation by refilling of trenches with dielectric material
    • H01L21/84
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01Manufacture or treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002Preparing wafers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H01L27/1203
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/6758Thin-film transistors [TFT] characterised by the insulating substrates
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113Isolations within a component, i.e. internal isolations
    • H10D62/115Dielectric isolations, e.g. air gaps
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/411Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by materials, geometry or structure of the substrates
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Micromachines (AREA)
  • Element Separation (AREA)
  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
KR1020187034754A 2016-06-08 2017-06-06 무선 주파수 애플리케이션들을 위한 구조 Active KR102369549B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR1655266 2016-06-08
FR1655266A FR3052592B1 (fr) 2016-06-08 2016-06-08 Structure pour applications radiofrequences
PCT/FR2017/051418 WO2017212160A1 (fr) 2016-06-08 2017-06-06 Structure pour applications radiofrequences

Publications (2)

Publication Number Publication Date
KR20190017762A KR20190017762A (ko) 2019-02-20
KR102369549B1 true KR102369549B1 (ko) 2022-03-04

Family

ID=56511794

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020187034754A Active KR102369549B1 (ko) 2016-06-08 2017-06-06 무선 주파수 애플리케이션들을 위한 구조

Country Status (8)

Country Link
US (3) US10943815B2 (enExample)
EP (1) EP3469627B1 (enExample)
JP (1) JP7053502B2 (enExample)
KR (1) KR102369549B1 (enExample)
FR (1) FR3052592B1 (enExample)
SG (2) SG10201913097SA (enExample)
TW (1) TWI733831B (enExample)
WO (1) WO2017212160A1 (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3052592B1 (fr) * 2016-06-08 2018-05-18 Soitec Structure pour applications radiofrequences
FR3062517B1 (fr) 2017-02-02 2019-03-15 Soitec Structure pour application radiofrequence
CN110828962B (zh) 2018-08-09 2021-08-03 财团法人工业技术研究院 天线阵列模块及其制造方法
US10658474B2 (en) * 2018-08-14 2020-05-19 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming thin semiconductor-on-insulator (SOI) substrates
FR3086096B1 (fr) * 2018-09-14 2021-08-27 Soitec Silicon On Insulator Procede de realisation d'un substrat avance pour une integration hybride
US11661337B2 (en) * 2020-10-19 2023-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Comb electrode release process for MEMS structure
US11658206B2 (en) * 2020-11-13 2023-05-23 Taiwan Semiconductor Manufacturing Company, Ltd. Deep trench structure for a capacitive device
US20220406649A1 (en) * 2021-06-22 2022-12-22 Texas Instruments Incorporated Passive component q factor enhancement with elevated resistance region of substrate
FR3126541B1 (fr) 2021-09-02 2025-01-10 Commissariat Energie Atomique Procédé de fabrication d’une structure multicouche
FR3134478B1 (fr) * 2022-04-06 2025-07-25 Commissariat Energie Atomique Substrat comprenant des vias et procédés de fabrication associés
FR3142289A1 (fr) * 2022-11-23 2024-05-24 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procédé de fabrication d’un empilement comprenant une couche isolante
CN116902904A (zh) * 2023-07-14 2023-10-20 绍兴中芯集成电路制造股份有限公司 一种mems器件、mems器件的制备方法和电子装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120266116A1 (en) 2008-08-07 2012-10-18 International Business Machines Corporation Integrated millimeter wave antenna and transceiver on a substrate
JP2013537715A (ja) 2010-08-02 2013-10-03 インターナショナル・ビジネス・マシーンズ・コーポレーション 電荷層を軽減した集積回路構造およびこれを形成する方法
US20140175598A1 (en) * 2012-12-21 2014-06-26 Shanghai Huahong Grace Semiconductor Manufacturing Corporation Silicon-on-insulator radio frequency device and silicon-on-insulator substrate

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3582890B2 (ja) * 1995-05-23 2004-10-27 株式会社日立製作所 半導体装置
US6312568B2 (en) * 1999-12-07 2001-11-06 Applied Materials, Inc. Two-step AIN-PVD for improved film properties
KR100388011B1 (ko) * 2000-01-17 2003-06-18 삼성전기주식회사 GaN박막 SAW필터 및 이를 제조하는 방법
US6391792B1 (en) * 2000-05-18 2002-05-21 Taiwan Semiconductor Manufacturing Co., Ltd Multi-step chemical mechanical polish (CMP) planarizing method for forming patterned planarized aperture fill layer
US20090179027A1 (en) * 2007-12-29 2009-07-16 Saint-Gobain Ceramics & Plastics, Inc. Coaxial ceramic igniter and methods of fabrication
CN102169552A (zh) 2011-01-28 2011-08-31 上海集成电路研发中心有限公司 射频识别标签及其制造方法
US9070585B2 (en) * 2012-02-24 2015-06-30 Semiconductor Components Industries, Llc Electronic device including a trench and a conductive structure therein and a process of forming the same
CN103077949B (zh) * 2013-01-28 2016-09-14 上海华虹宏力半导体制造有限公司 绝缘体上硅射频器件及其制作方法
US9373613B2 (en) * 2013-12-31 2016-06-21 Skyworks Solutions, Inc. Amplifier voltage limiting using punch-through effect
EP3024020A1 (en) * 2014-11-19 2016-05-25 Nxp B.V. Semiconductor device and method
CN107660313B (zh) * 2015-06-26 2022-09-13 英特尔公司 在衬底上的氮化镓(GaN)晶体管结构
US10411067B2 (en) * 2015-12-21 2019-09-10 Intel Corporation Integrated RF frontend structures
FR3052592B1 (fr) * 2016-06-08 2018-05-18 Soitec Structure pour applications radiofrequences

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120266116A1 (en) 2008-08-07 2012-10-18 International Business Machines Corporation Integrated millimeter wave antenna and transceiver on a substrate
JP2013537715A (ja) 2010-08-02 2013-10-03 インターナショナル・ビジネス・マシーンズ・コーポレーション 電荷層を軽減した集積回路構造およびこれを形成する方法
US20140175598A1 (en) * 2012-12-21 2014-06-26 Shanghai Huahong Grace Semiconductor Manufacturing Corporation Silicon-on-insulator radio frequency device and silicon-on-insulator substrate

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
2005IEEE*
비특허문헌 1, 9TH IEEE WORKSHOP ON SIGNAL PROPAGATION ON INTERCONNECTS, 2005., 2005.08.29*
비특허문헌 2, 2013 IEEE BIPOLAR/BICMOS CIRCUITS AND TECHNOLOGY MEETING (BCTM), 2014.04.17

Also Published As

Publication number Publication date
US10943815B2 (en) 2021-03-09
JP7053502B2 (ja) 2022-04-12
JP2019527925A (ja) 2019-10-03
US11367650B2 (en) 2022-06-21
US20190157137A1 (en) 2019-05-23
TW201806175A (zh) 2018-02-16
SG11201810415PA (en) 2018-12-28
US11923239B2 (en) 2024-03-05
FR3052592B1 (fr) 2018-05-18
TWI733831B (zh) 2021-07-21
WO2017212160A1 (fr) 2017-12-14
US20220277988A1 (en) 2022-09-01
EP3469627A1 (fr) 2019-04-17
US20210143053A1 (en) 2021-05-13
FR3052592A1 (fr) 2017-12-15
KR20190017762A (ko) 2019-02-20
EP3469627B1 (fr) 2020-07-29
SG10201913097SA (en) 2020-02-27

Similar Documents

Publication Publication Date Title
KR102369549B1 (ko) 무선 주파수 애플리케이션들을 위한 구조
JP6643316B2 (ja) 無線周波アプリケーションの構造
US10250282B2 (en) Structure for radiofrequency applications
US12418120B2 (en) Structure for radio frequency applications
US11164945B2 (en) SOI substrate, semiconductor device and method for manufacturing the same
JP2018501651A5 (enExample)
TWI741217B (zh) 複合半導體基底、半導體裝置及其製造方法
JP7293537B2 (ja) 高周波用途のための基板及び関連付けられた製造方法

Legal Events

Date Code Title Description
PA0105 International application

Patent event date: 20181129

Patent event code: PA01051R01D

Comment text: International Patent Application

PG1501 Laying open of application
A201 Request for examination
PA0201 Request for examination

Patent event code: PA02012R01D

Patent event date: 20200420

Comment text: Request for Examination of Application

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

Comment text: Notification of reason for refusal

Patent event date: 20210420

Patent event code: PE09021S01D

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

Comment text: Notification of reason for refusal

Patent event date: 20211026

Patent event code: PE09021S01D

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

Patent event code: PE07011S01D

Comment text: Decision to Grant Registration

Patent event date: 20220101

PR0701 Registration of establishment

Comment text: Registration of Establishment

Patent event date: 20220225

Patent event code: PR07011E01D

PR1002 Payment of registration fee

Payment date: 20220228

End annual number: 3

Start annual number: 1

PG1601 Publication of registration
PR1001 Payment of annual fee

Payment date: 20250124

Start annual number: 4

End annual number: 4