SG10201807751QA - Wafer processing method - Google Patents

Wafer processing method

Info

Publication number
SG10201807751QA
SG10201807751QA SG10201807751QA SG10201807751QA SG10201807751QA SG 10201807751Q A SG10201807751Q A SG 10201807751QA SG 10201807751Q A SG10201807751Q A SG 10201807751QA SG 10201807751Q A SG10201807751Q A SG 10201807751QA SG 10201807751Q A SG10201807751Q A SG 10201807751QA
Authority
SG
Singapore
Prior art keywords
wafer
sealing material
front surface
surface side
processing method
Prior art date
Application number
SG10201807751QA
Inventor
Suzuki Katsuhiko
Ban Yuri
Original Assignee
Disco Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Disco Corp filed Critical Disco Corp
Publication of SG10201807751QA publication Critical patent/SG10201807751QA/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67092—Apparatus for mechanical treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H01L21/681—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment using optical controlling means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Dicing (AREA)
  • Laser Beam Processing (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Constituent Portions Of Griding Lathes, Driving, Sensing And Control (AREA)
  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)

Abstract

WAFER PROCESSING METHOD A wafer processing method includes: an alignment step of capturing the front surface side of the wafer through a sealing material by an infrared imaging unit from the front surface side of the wafer, detecting an alignment mark, and detecting a division line to be laser processed based on the alignment mark; a laser processed groove forming step of emitting a laser beam of such a wavelength as to be absorbed in the sealing material along the division lines from the front surface side of the wafer, and forming, by ablation processing, laser processed grooves having a depth corresponding to the finished thickness of each of the device chips in the sealing material in the cut grooves; and a dividing step of grinding the wafer from a back surface side of the wafer to the finished thickness of each of the device chips to expose the laser processed grooves, and dividing the wafer into individual device chips each of which has its front surface and four side surfaces surrounded by the sealing material. (Figure 4)
SG10201807751QA 2017-09-08 2018-09-07 Wafer processing method SG10201807751QA (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2017173188A JP7098221B2 (en) 2017-09-08 2017-09-08 Wafer processing method

Publications (1)

Publication Number Publication Date
SG10201807751QA true SG10201807751QA (en) 2019-04-29

Family

ID=65441509

Family Applications (1)

Application Number Title Priority Date Filing Date
SG10201807751QA SG10201807751QA (en) 2017-09-08 2018-09-07 Wafer processing method

Country Status (6)

Country Link
JP (1) JP7098221B2 (en)
KR (1) KR102631710B1 (en)
CN (1) CN109473396B (en)
DE (1) DE102018215249A1 (en)
SG (1) SG10201807751QA (en)
TW (1) TW201913784A (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020181876A (en) * 2019-04-24 2020-11-05 株式会社ディスコ Method for manufacturing device package
WO2021132679A1 (en) * 2019-12-27 2021-07-01 リンテック株式会社 Curable resin film, composite sheet, and method for manufacturing semiconductor chip
KR20220122641A (en) * 2019-12-27 2022-09-02 린텍 가부시키가이샤 Semiconductor chip manufacturing method
TW202136448A (en) * 2020-02-27 2021-10-01 日商琳得科股份有限公司 Protective coating formation sheet, method for producing chip equipped with protective coating, and layered product

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3595232B2 (en) * 1999-03-11 2004-12-02 沖電気工業株式会社 Method for manufacturing semiconductor device
JP3415069B2 (en) * 1999-05-14 2003-06-09 株式会社東京精密 Dicing equipment
JP2003327666A (en) * 2002-05-16 2003-11-19 Kyocera Chemical Corp Epoxy resin composition and semiconductor sealed device
JP4471632B2 (en) * 2003-11-18 2010-06-02 株式会社ディスコ Wafer processing method
JP2006052279A (en) * 2004-08-11 2006-02-23 Tokai Carbon Co Ltd Carbon black colorant for semiconductor sealing material and method for producing the same
US7494900B2 (en) * 2006-05-25 2009-02-24 Electro Scientific Industries, Inc. Back side wafer dicing
JP5948034B2 (en) 2011-09-27 2016-07-06 株式会社ディスコ Alignment method
JP2015023078A (en) * 2013-07-17 2015-02-02 株式会社ディスコ Method of processing wafer
JP2016015438A (en) 2014-07-03 2016-01-28 株式会社ディスコ Alignment method
JP2017005056A (en) * 2015-06-08 2017-01-05 株式会社ディスコ Wafer processing method
JP2017108089A (en) * 2015-12-04 2017-06-15 株式会社東京精密 Laser processing apparatus and laser processing method
JP6608694B2 (en) * 2015-12-25 2019-11-20 株式会社ディスコ Wafer processing method

Also Published As

Publication number Publication date
KR20190028322A (en) 2019-03-18
CN109473396B (en) 2023-06-23
JP7098221B2 (en) 2022-07-11
CN109473396A (en) 2019-03-15
DE102018215249A1 (en) 2019-03-14
KR102631710B1 (en) 2024-01-30
TW201913784A (en) 2019-04-01
JP2019050261A (en) 2019-03-28

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