SE9601685D0 - Arrangement and method relating to instruction processing - Google Patents

Arrangement and method relating to instruction processing

Info

Publication number
SE9601685D0
SE9601685D0 SE9601685A SE9601685A SE9601685D0 SE 9601685 D0 SE9601685 D0 SE 9601685D0 SE 9601685 A SE9601685 A SE 9601685A SE 9601685 A SE9601685 A SE 9601685A SE 9601685 D0 SE9601685 D0 SE 9601685D0
Authority
SE
Sweden
Prior art keywords
arrangement
jump
instructions
fifo
register
Prior art date
Application number
SE9601685A
Other languages
English (en)
Other versions
SE509499C2 (sv
SE9601685L (sv
Inventor
Dan Halvarsson
Original Assignee
Ericsson Telefon Ab L M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Telefon Ab L M filed Critical Ericsson Telefon Ab L M
Priority to SE9601685A priority Critical patent/SE509499C2/sv
Publication of SE9601685D0 publication Critical patent/SE9601685D0/sv
Priority to JP09539844A priority patent/JP2000510623A/ja
Priority to PCT/SE1997/000744 priority patent/WO1997042567A1/en
Priority to CA002253560A priority patent/CA2253560C/en
Priority to EP97922267A priority patent/EP1029268B1/en
Priority to AU27983/97A priority patent/AU2798397A/en
Priority to DE69734403T priority patent/DE69734403T2/de
Priority to CN97195758.4A priority patent/CN1103960C/zh
Publication of SE9601685L publication Critical patent/SE9601685L/sv
Priority to US09/185,194 priority patent/US6330664B1/en
Publication of SE509499C2 publication Critical patent/SE509499C2/sv

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G06F9/3806—Instruction prefetching for branches, e.g. hedging, branch folding using address prediction, e.g. return stack, branch history buffer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30058—Conditional branch instructions

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
SE9601685A 1996-05-03 1996-05-03 Metod och anordning för hantering av villkorliga hopp vid instruktionsbehandling i en pipeline-arkitektur SE509499C2 (sv)

Priority Applications (9)

Application Number Priority Date Filing Date Title
SE9601685A SE509499C2 (sv) 1996-05-03 1996-05-03 Metod och anordning för hantering av villkorliga hopp vid instruktionsbehandling i en pipeline-arkitektur
CN97195758.4A CN1103960C (zh) 1996-05-03 1997-05-02 在多级流水线结构中处理条件跳转的结构和方法
EP97922267A EP1029268B1 (en) 1996-05-03 1997-05-02 Method relating to handling of conditional jumps in a multi-stage pipeline arrangement
PCT/SE1997/000744 WO1997042567A1 (en) 1996-05-03 1997-05-02 Method relating to handling of conditional jumps in a multi-stage pipeline arrangement
CA002253560A CA2253560C (en) 1996-05-03 1997-05-02 Method relating to handling of conditional jumps in a multi-stage pipeline arrangement
JP09539844A JP2000510623A (ja) 1996-05-03 1997-05-02 多重ステージパイプライン装置における条件付き飛越しの取扱いに関する方法
AU27983/97A AU2798397A (en) 1996-05-03 1997-05-02 Method relating to handling of conditional jumps in a multi-stage pipeline arrangement
DE69734403T DE69734403T2 (de) 1996-05-03 1997-05-02 Verfahren im bezug auf die behandlung von konditionellen sprüngen in einer multietagen-pipeline-struktur
US09/185,194 US6330664B1 (en) 1996-05-03 1998-11-03 Method relating to handling of conditional jumps in a multi-stage pipeline arrangement

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE9601685A SE509499C2 (sv) 1996-05-03 1996-05-03 Metod och anordning för hantering av villkorliga hopp vid instruktionsbehandling i en pipeline-arkitektur

Publications (3)

Publication Number Publication Date
SE9601685D0 true SE9601685D0 (sv) 1996-05-03
SE9601685L SE9601685L (sv) 1997-11-04
SE509499C2 SE509499C2 (sv) 1999-02-01

Family

ID=20402437

Family Applications (1)

Application Number Title Priority Date Filing Date
SE9601685A SE509499C2 (sv) 1996-05-03 1996-05-03 Metod och anordning för hantering av villkorliga hopp vid instruktionsbehandling i en pipeline-arkitektur

Country Status (9)

Country Link
US (1) US6330664B1 (sv)
EP (1) EP1029268B1 (sv)
JP (1) JP2000510623A (sv)
CN (1) CN1103960C (sv)
AU (1) AU2798397A (sv)
CA (1) CA2253560C (sv)
DE (1) DE69734403T2 (sv)
SE (1) SE509499C2 (sv)
WO (1) WO1997042567A1 (sv)

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SE509499C2 (sv) * 1996-05-03 1999-02-01 Ericsson Telefon Ab L M Metod och anordning för hantering av villkorliga hopp vid instruktionsbehandling i en pipeline-arkitektur
SE510295C2 (sv) * 1997-07-21 1999-05-10 Ericsson Telefon Ab L M Metod vid processor för att hantera villkorade hoppinstruktioner samt processor anpassad att verka enligt den angivna metoden
US6948054B2 (en) * 2000-11-29 2005-09-20 Lsi Logic Corporation Simple branch prediction and misprediction recovery method
US6691306B1 (en) * 2000-12-22 2004-02-10 Lsi Logic Corporation Use of limited program space of general purpose processor for unlimited sequence of translated instructions
US7281120B2 (en) * 2004-03-26 2007-10-09 International Business Machines Corporation Apparatus and method for decreasing the latency between an instruction cache and a pipeline processor
EP1810128B1 (en) * 2004-08-30 2009-11-11 Texas Instruments Incorporated Methods and apparatus for branch prediction and processing of microprocessor instructions and the like
US7603544B2 (en) * 2004-12-23 2009-10-13 Intel Corporation Dynamic allocation of a buffer across multiple clients in multi-threaded processor without performing a complete flush of data associated with allocation
US20060179277A1 (en) * 2005-02-04 2006-08-10 Flachs Brian K System and method for instruction line buffer holding a branch target buffer
US20080222392A1 (en) * 2007-03-09 2008-09-11 On Demand Microelectronics Method and arrangements for pipeline processing of instructions
US20080222393A1 (en) * 2007-03-09 2008-09-11 On Demand Microelectronics Method and arrangements for pipeline processing of instructions
US7941653B2 (en) * 2008-12-04 2011-05-10 Analog Devices, Inc. Jump instruction having a reference to a pointer for accessing a branch address table
CN102117198B (zh) * 2009-12-31 2015-07-15 上海芯豪微电子有限公司 一种分支处理方法
CN106990942A (zh) * 2011-06-29 2017-07-28 上海芯豪微电子有限公司 分支处理方法与系统
CN102508641A (zh) * 2011-11-04 2012-06-20 杭州中天微系统有限公司 低成本的程序计数器数据传输装置
US9134377B2 (en) * 2013-03-14 2015-09-15 Teradyne, Inc. Method and apparatus for device testing using multiple processing paths
US9513924B2 (en) * 2013-06-28 2016-12-06 Globalfoundries Inc. Predictor data structure for use in pipelined processing
CN103744642B (zh) * 2013-12-31 2017-01-18 天津国芯科技有限公司 用于改进处理器中直接跳转的方法及系统
CN104331268B (zh) * 2014-10-27 2017-05-03 杭州中天微系统有限公司 一种用于低功耗处理器的加快条件跳转执行的装置
US10139449B2 (en) 2016-01-26 2018-11-27 Teradyne, Inc. Automatic test system with focused test hardware
CN109324838B (zh) * 2018-08-31 2022-05-10 深圳市元征科技股份有限公司 单片机程序的执行方法、执行装置及终端
CN110704108B (zh) * 2019-08-30 2020-08-14 阿里巴巴集团控股有限公司 解释执行字节码指令流的方法及装置
US10802854B2 (en) 2019-08-30 2020-10-13 Alibaba Group Holding Limited Method and apparatus for interpreting bytecode instruction stream
CN111026442B (zh) * 2019-12-17 2022-08-02 天津国芯科技有限公司 一种cpu中用于消除程序无条件跳转开销的方法及装置
CN113220347B (zh) * 2021-03-30 2024-03-22 深圳市创成微电子有限公司 基于多级流水线的指令处理方法、浮点型dsp以及音频设备
CN113760366B (zh) * 2021-07-30 2024-02-09 浪潮电子信息产业股份有限公司 一种条件跳转指令的处理方法、系统及相关装置
CN113946539B (zh) * 2021-10-09 2024-02-13 深圳市创成微电子有限公司 一种dsp处理器及其循环跳转指令的处理方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3751503T2 (de) * 1986-03-26 1996-05-09 Hitachi Ltd Datenprozessor in Pipelinestruktur mit der Fähigkeit mehrere Befehle parallel zu dekodieren und auszuführen.
US4974155A (en) 1988-08-15 1990-11-27 Evans & Sutherland Computer Corp. Variable delay branch system
US5131086A (en) * 1988-08-25 1992-07-14 Edgcore Technology, Inc. Method and system for executing pipelined three operand construct
US5101341A (en) * 1988-08-25 1992-03-31 Edgcore Technology, Inc. Pipelined system for reducing instruction access time by accumulating predecoded instruction bits a FIFO
JP2710994B2 (ja) * 1989-08-29 1998-02-10 三菱電機株式会社 データ処理装置
JP2560889B2 (ja) * 1990-05-22 1996-12-04 日本電気株式会社 マイクロプロセッサ
US5287467A (en) * 1991-04-18 1994-02-15 International Business Machines Corporation Pipeline for removing and concurrently executing two or more branch instructions in synchronization with other instructions executing in the execution unit
US5317700A (en) * 1992-05-01 1994-05-31 Unisys Corporation Program history for pipelined processor including temporary storage queues for storing branch addresses
US5442756A (en) * 1992-07-31 1995-08-15 Intel Corporation Branch prediction and resolution apparatus for a superscalar computer processor
DE69429061T2 (de) * 1993-10-29 2002-07-18 Advanced Micro Devices Inc Superskalarmikroprozessoren
US5758142A (en) * 1994-05-31 1998-05-26 Digital Equipment Corporation Trainable apparatus for predicting instruction outcomes in pipelined processors
US5598546A (en) * 1994-08-31 1997-01-28 Exponential Technology, Inc. Dual-architecture super-scalar pipeline
US5692170A (en) * 1995-04-28 1997-11-25 Metaflow Technologies, Inc. Apparatus for detecting and executing traps in a superscalar processor
SE509499C2 (sv) * 1996-05-03 1999-02-01 Ericsson Telefon Ab L M Metod och anordning för hantering av villkorliga hopp vid instruktionsbehandling i en pipeline-arkitektur
JP3745039B2 (ja) * 1996-08-01 2006-02-15 株式会社ルネサステクノロジ 遅延命令を有するマイクロプロセッサ
US5949995A (en) * 1996-08-02 1999-09-07 Freeman; Jackie Andrew Programmable branch prediction system and method for inserting prediction operation which is independent of execution of program code
US6055630A (en) * 1998-04-20 2000-04-25 Intel Corporation System and method for processing a plurality of branch instructions by a plurality of storage devices and pipeline units

Also Published As

Publication number Publication date
JP2000510623A (ja) 2000-08-15
DE69734403D1 (de) 2005-11-24
EP1029268A1 (en) 2000-08-23
CA2253560C (en) 2003-07-22
SE509499C2 (sv) 1999-02-01
US6330664B1 (en) 2001-12-11
EP1029268B1 (en) 2005-10-19
SE9601685L (sv) 1997-11-04
CA2253560A1 (en) 1997-11-13
CN1222985A (zh) 1999-07-14
DE69734403T2 (de) 2006-07-06
AU2798397A (en) 1997-11-26
CN1103960C (zh) 2003-03-26
WO1997042567A1 (en) 1997-11-13

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