DE69628480D1 - Ausnahmebehandlung in einem Datenprozessor - Google Patents

Ausnahmebehandlung in einem Datenprozessor

Info

Publication number
DE69628480D1
DE69628480D1 DE69628480T DE69628480T DE69628480D1 DE 69628480 D1 DE69628480 D1 DE 69628480D1 DE 69628480 T DE69628480 T DE 69628480T DE 69628480 T DE69628480 T DE 69628480T DE 69628480 D1 DE69628480 D1 DE 69628480D1
Authority
DE
Germany
Prior art keywords
instruction
register
physical
logical
registers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69628480T
Other languages
English (en)
Other versions
DE69628480T2 (de
Inventor
Michael C Shebanow
Gene W Shen
Ravi Swami
Niteen A Patkar
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE69628480D1 publication Critical patent/DE69628480D1/de
Publication of DE69628480T2 publication Critical patent/DE69628480T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384—Register renaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3856—Reordering of instructions, e.g. using queues or age tags
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G06F9/3863—Recovery, e.g. branch miss-prediction, exception handling using multiple copies of the architectural state, e.g. shadow registers

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Retry When Errors Occur (AREA)
  • Exchange Systems With Centralized Control (AREA)
DE69628480T 1995-03-03 1996-03-01 Ausnahmebehandlung in einem Datenprozessor Expired - Lifetime DE69628480T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US39789395A 1995-03-03 1995-03-03
US397893 1995-03-03

Publications (2)

Publication Number Publication Date
DE69628480D1 true DE69628480D1 (de) 2003-07-10
DE69628480T2 DE69628480T2 (de) 2004-05-06

Family

ID=23573099

Family Applications (2)

Application Number Title Priority Date Filing Date
DE69628480T Expired - Lifetime DE69628480T2 (de) 1995-03-03 1996-03-01 Ausnahmebehandlung in einem Datenprozessor
DE69638299T Expired - Lifetime DE69638299D1 (de) 1995-03-03 1996-03-01 Verfahren und Vorrichtung zur Änderung der Namen von Registern

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE69638299T Expired - Lifetime DE69638299D1 (de) 1995-03-03 1996-03-01 Verfahren und Vorrichtung zur Änderung der Namen von Registern

Country Status (4)

Country Link
US (1) US5675759A (de)
EP (2) EP1308837B1 (de)
AT (1) ATE242508T1 (de)
DE (2) DE69628480T2 (de)

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US6314511B2 (en) * 1997-04-03 2001-11-06 University Of Washington Mechanism for freeing registers on processors that perform dynamic out-of-order execution of instructions using renaming registers
US6003126A (en) * 1997-07-01 1999-12-14 International Business Machines Special instruction register including allocation field utilized for temporary designation of physical registers as general registers
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US6009509A (en) * 1997-10-08 1999-12-28 International Business Machines Corporation Method and system for the temporary designation and utilization of a plurality of physical registers as a stack
US5974525A (en) * 1997-12-05 1999-10-26 Intel Corporation System for allowing multiple instructions to use the same logical registers by remapping them to separate physical segment registers when the first is being utilized
US6108771A (en) * 1997-12-19 2000-08-22 International Business Machines Corporation Register renaming with a pool of physical registers
US6212619B1 (en) * 1998-05-11 2001-04-03 International Business Machines Corporation System and method for high-speed register renaming by counting
US6230262B1 (en) 1998-07-31 2001-05-08 Advanced Micro Devices, Inc. Processor configured to selectively free physical registers upon retirement of instructions
US6122656A (en) 1998-07-31 2000-09-19 Advanced Micro Devices, Inc. Processor configured to map logical register numbers to physical register numbers using virtual register numbers
US6119223A (en) * 1998-07-31 2000-09-12 Advanced Micro Devices, Inc. Map unit having rapid misprediction recovery
US6633563B1 (en) * 1999-03-02 2003-10-14 Nortel Networks Limited Assigning cell data to one of several processors provided in a data switch
US6553483B1 (en) * 1999-11-29 2003-04-22 Intel Corporation Enhanced virtual renaming scheme and deadlock prevention therefor
US6633970B1 (en) * 1999-12-28 2003-10-14 Intel Corporation Processor with registers storing committed/speculative data and a RAT state history recovery mechanism with retire pointer
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US20040064657A1 (en) * 2002-09-27 2004-04-01 Muraleedhara Navada Memory structure including information storage elements and associated validity storage elements
US7117297B2 (en) * 2003-05-23 2006-10-03 Hewlett-Packard Development Company, L.P. Method and apparatus for storing multiple entry types and ordering information using a single addressable storage array
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US7216219B2 (en) * 2004-05-03 2007-05-08 Sun Microsystems Inc. Method and apparatus for avoiding write-after-read hazards in an execute-ahead processor
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US20080016326A1 (en) 2006-07-14 2008-01-17 Mips Technologies, Inc. Latest producer tracking in an out-of-order processor, and applications thereof
US7370178B1 (en) * 2006-07-14 2008-05-06 Mips Technologies, Inc. Method for latest producer tracking in an out-of-order processor, and applications thereof
EP2527972A3 (de) 2006-11-14 2014-08-06 Soft Machines, Inc. Vorrichtung und Verfahren zum Verarbeiten von komplexen Anweisungsformaten in einer Multi-Thread-Architektur, die verschiedene Kontextschaltungsmodi und Visualisierungsschemen unterstützt
JP5595633B2 (ja) * 2007-02-26 2014-09-24 スパンション エルエルシー シミュレーション方法及びシミュレーション装置
TWI389026B (zh) * 2009-06-08 2013-03-11 Rdc Semiconductor Co Ltd 暫存器更名表的回復方法與回復系統
WO2012037491A2 (en) 2010-09-17 2012-03-22 Soft Machines, Inc. Single cycle multi-branch prediction including shadow cache for early far branch prediction
CN108376097B (zh) 2011-03-25 2022-04-15 英特尔公司 用于通过使用由可分割引擎实例化的虚拟核来支持代码块执行的寄存器文件段
EP2689326B1 (de) 2011-03-25 2022-11-16 Intel Corporation Speicherfragmente zur unterstützung einer codeblockausführung mittels durch partitionierbare engines realisierter virtueller kerne
TWI533129B (zh) 2011-03-25 2016-05-11 軟體機器公司 使用可分割引擎實體化的虛擬核心執行指令序列程式碼區塊
US9170818B2 (en) * 2011-04-26 2015-10-27 Freescale Semiconductor, Inc. Register renaming scheme with checkpoint repair in a processing device
EP2710480B1 (de) 2011-05-20 2018-06-20 Intel Corporation Verbindungsstruktur zur unterstützung der ausführung von instruktionssequenzen durch mehrere maschinen
TWI666551B (zh) 2011-05-20 2019-07-21 美商英特爾股份有限公司 以複數個引擎作資源與互連結構的分散式分配以支援指令序列的執行
IN2014CN03678A (de) 2011-11-22 2015-09-25 Soft Machines Inc
CN104040491B (zh) 2011-11-22 2018-06-12 英特尔公司 微处理器加速的代码优化器
US20140075140A1 (en) * 2011-12-30 2014-03-13 Ingo Schmiegel Selective control for commit lines for shadowing data in storage elements
US9569216B2 (en) 2013-03-15 2017-02-14 Soft Machines, Inc. Method for populating a source view data structure by using register template snapshots
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US9904625B2 (en) 2013-03-15 2018-02-27 Intel Corporation Methods, systems and apparatus for predicting the way of a set associative cache
US9891924B2 (en) 2013-03-15 2018-02-13 Intel Corporation Method for implementing a reduced size register view data structure in a microprocessor
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US9811342B2 (en) 2013-03-15 2017-11-07 Intel Corporation Method for performing dual dispatch of blocks and half blocks
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US9886279B2 (en) * 2013-03-15 2018-02-06 Intel Corporation Method for populating and instruction view data structure by using register template snapshots
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US10275255B2 (en) 2013-03-15 2019-04-30 Intel Corporation Method for dependency broadcasting through a source organized source view data structure
JP6307975B2 (ja) * 2014-03-28 2018-04-11 富士通株式会社 演算処理装置及び演算処理装置の制御方法
US20180203703A1 (en) * 2017-01-13 2018-07-19 Optimum Semiconductor Technologies, Inc. Implementation of register renaming, call-return prediction and prefetch
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Also Published As

Publication number Publication date
US5675759A (en) 1997-10-07
DE69628480T2 (de) 2004-05-06
EP1308837B1 (de) 2010-12-01
EP1308837A2 (de) 2003-05-07
EP0730225A2 (de) 1996-09-04
EP1308837A3 (de) 2007-02-28
EP0730225B1 (de) 2003-06-04
DE69638299D1 (de) 2011-01-13
EP0730225A3 (de) 1999-12-08
ATE242508T1 (de) 2003-06-15

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