JPS573142A - Instruction prefetching system - Google Patents

Instruction prefetching system

Info

Publication number
JPS573142A
JPS573142A JP7592480A JP7592480A JPS573142A JP S573142 A JPS573142 A JP S573142A JP 7592480 A JP7592480 A JP 7592480A JP 7592480 A JP7592480 A JP 7592480A JP S573142 A JPS573142 A JP S573142A
Authority
JP
Japan
Prior art keywords
instruction
address
branch
absolute
buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7592480A
Other languages
Japanese (ja)
Inventor
Etsuo Kusumoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP7592480A priority Critical patent/JPS573142A/en
Publication of JPS573142A publication Critical patent/JPS573142A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)

Abstract

PURPOSE:To enhance the processing speed, by prefetching the instruction of a branch destination in respect to a branch instruction designating an absolute or relative address. CONSTITUTION:A bit, which indicates whether a prefetched instruction held in a buffer 1 is the branch instruction of the absolute or relative address designation system or not, and a bit, which indicates information required for calculation of the address of the branch destination, out of bits constituting this prefetched instruction are inputted from the buffer 1 to an instruction prefetching address generating circuit 3 through a signal line D4. This instruction prefetching address generating circuit 3 generates the address of the branch destination if the branch instruction of the absolute or relative address designation system is held in the buffer 1, but otherwise, contents of a register 4 are increased by 1 simply. When the address of the branch destination is generated, this generation is reported to a register group 2 through a signal line C.
JP7592480A 1980-06-04 1980-06-04 Instruction prefetching system Pending JPS573142A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7592480A JPS573142A (en) 1980-06-04 1980-06-04 Instruction prefetching system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7592480A JPS573142A (en) 1980-06-04 1980-06-04 Instruction prefetching system

Publications (1)

Publication Number Publication Date
JPS573142A true JPS573142A (en) 1982-01-08

Family

ID=13590326

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7592480A Pending JPS573142A (en) 1980-06-04 1980-06-04 Instruction prefetching system

Country Status (1)

Country Link
JP (1) JPS573142A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6395539A (en) * 1986-10-09 1988-04-26 Nec Corp Pipeline processing system
EP0324952A2 (en) * 1988-01-18 1989-07-26 Kabushiki Kaisha Toshiba Branching circuit for a pipelined processor
EP0394711A2 (en) * 1989-04-28 1990-10-31 Kabushiki Kaisha Toshiba Branch instruction control unit based on a pipeline method
EP0402524A2 (en) * 1988-11-25 1990-12-19 Nec Corporation Microcomputer capable of quickly processing a branch instruction code
US5729727A (en) * 1994-12-06 1998-03-17 Matsushita Electric Industrial Co., Ltd. Pipelined processor which reduces branch instruction interlocks by compensating for misaligned branch instructions

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5039437A (en) * 1973-08-10 1975-04-11

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5039437A (en) * 1973-08-10 1975-04-11

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6395539A (en) * 1986-10-09 1988-04-26 Nec Corp Pipeline processing system
EP0324952A2 (en) * 1988-01-18 1989-07-26 Kabushiki Kaisha Toshiba Branching circuit for a pipelined processor
US5237664A (en) * 1988-01-18 1993-08-17 Kabushiki Kaisha Toshiba Pipeline circuit
EP0402524A2 (en) * 1988-11-25 1990-12-19 Nec Corporation Microcomputer capable of quickly processing a branch instruction code
EP0394711A2 (en) * 1989-04-28 1990-10-31 Kabushiki Kaisha Toshiba Branch instruction control unit based on a pipeline method
US5729727A (en) * 1994-12-06 1998-03-17 Matsushita Electric Industrial Co., Ltd. Pipelined processor which reduces branch instruction interlocks by compensating for misaligned branch instructions
EP0716376A3 (en) * 1994-12-06 1998-04-01 Matsushita Electric Industrial Co., Ltd. A pipeline processor with reduced interlocks caused by branch instructions

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