SE9503951L - Spekulativ historikmekanism i en grenmålsbuffert - Google Patents

Spekulativ historikmekanism i en grenmålsbuffert

Info

Publication number
SE9503951L
SE9503951L SE9503951A SE9503951A SE9503951L SE 9503951 L SE9503951 L SE 9503951L SE 9503951 A SE9503951 A SE 9503951A SE 9503951 A SE9503951 A SE 9503951A SE 9503951 L SE9503951 L SE 9503951L
Authority
SE
Sweden
Prior art keywords
branch
history
speculative
bit
target buffer
Prior art date
Application number
SE9503951A
Other languages
Unknown language ( )
English (en)
Other versions
SE515698C2 (sv
SE9503951D0 (sv
Inventor
Bradley D Hoyt
Glenn J Hinton
Andrew F Glew
Subramanian Natarajan
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from PCT/US1994/003897 external-priority patent/WO1994027210A1/en
Application filed by Intel Corp filed Critical Intel Corp
Publication of SE9503951D0 publication Critical patent/SE9503951D0/sv
Publication of SE9503951L publication Critical patent/SE9503951L/sv
Publication of SE515698C2 publication Critical patent/SE515698C2/sv

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G06F9/3806—Instruction prefetching for branches, e.g. hedging, branch folding using address prediction, e.g. return stack, branch history buffer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G06F9/3844—Speculative instruction execution using dynamic branch prediction, e.g. using branch history tables

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
SE9503951A 1993-05-14 1995-11-08 Spekulativ historikmekanism i en grenmålsbuffert SE515698C2 (sv)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US6201293A 1993-05-14 1993-05-14
PCT/US1994/003897 WO1994027210A1 (en) 1993-05-14 1994-04-08 Speculative history mechanism in a branch target buffer

Publications (3)

Publication Number Publication Date
SE9503951D0 SE9503951D0 (sv) 1995-11-08
SE9503951L true SE9503951L (sv) 1995-12-29
SE515698C2 SE515698C2 (sv) 2001-09-24

Family

ID=22039646

Family Applications (1)

Application Number Title Priority Date Filing Date
SE9503951A SE515698C2 (sv) 1993-05-14 1995-11-08 Spekulativ historikmekanism i en grenmålsbuffert

Country Status (4)

Country Link
US (1) US5584001A (sv)
JP (1) JPH09500989A (sv)
KR (1) KR100310581B1 (sv)
SE (1) SE515698C2 (sv)

Families Citing this family (55)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5493687A (en) 1991-07-08 1996-02-20 Seiko Epson Corporation RISC microprocessor architecture implementing multiple typed register sets
US5539911A (en) 1991-07-08 1996-07-23 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
EP0636256B1 (en) 1992-03-31 1997-06-04 Seiko Epson Corporation Superscalar risc processor instruction scheduling
EP0638183B1 (en) 1992-05-01 1997-03-05 Seiko Epson Corporation A system and method for retiring instructions in a superscalar microprocessor
DE69330889T2 (de) 1992-12-31 2002-03-28 Seiko Epson Corp., Tokio/Tokyo System und Verfahren zur Änderung der Namen von Registern
US5628021A (en) * 1992-12-31 1997-05-06 Seiko Epson Corporation System and method for assigning tags to control instruction processing in a superscalar processor
US5454117A (en) 1993-08-25 1995-09-26 Nexgen, Inc. Configurable branch prediction for a processor performing speculative execution
US5918046A (en) * 1994-01-03 1999-06-29 Intel Corporation Method and apparatus for a branch instruction pointer table
US5574871A (en) * 1994-01-04 1996-11-12 Intel Corporation Method and apparatus for implementing a set-associative branch target buffer
JP3494484B2 (ja) * 1994-10-12 2004-02-09 株式会社ルネサステクノロジ 命令処理装置
JP3569014B2 (ja) * 1994-11-25 2004-09-22 富士通株式会社 マルチコンテキストをサポートするプロセッサおよび処理方法
US5799179A (en) * 1995-01-24 1998-08-25 International Business Machines Corporation Handling of exceptions in speculative instructions
US5968169A (en) * 1995-06-07 1999-10-19 Advanced Micro Devices, Inc. Superscalar microprocessor stack structure for judging validity of predicted subroutine return addresses
US5881278A (en) * 1995-10-30 1999-03-09 Advanced Micro Devices, Inc. Return address prediction system which adjusts the contents of return stack storage to enable continued prediction after a mispredicted branch
US5740417A (en) * 1995-12-05 1998-04-14 Motorola, Inc. Pipelined processor operating in different power mode based on branch prediction state of branch history bit encoded as taken weakly not taken and strongly not taken states
US5864707A (en) 1995-12-11 1999-01-26 Advanced Micro Devices, Inc. Superscalar microprocessor configured to predict return addresses from a return stack storage
US5909573A (en) * 1996-03-28 1999-06-01 Intel Corporation Method of branch prediction using loop counters
US5752014A (en) * 1996-04-29 1998-05-12 International Business Machines Corporation Automatic selection of branch prediction methodology for subsequent branch instruction based on outcome of previous branch prediction
US5901307A (en) * 1996-07-22 1999-05-04 International Business Machines Corporation Processor having a selectively configurable branch prediction unit that can access a branch prediction utilizing bits derived from a plurality of sources
US5949995A (en) * 1996-08-02 1999-09-07 Freeman; Jackie Andrew Programmable branch prediction system and method for inserting prediction operation which is independent of execution of program code
JPH1091441A (ja) * 1996-09-13 1998-04-10 Sanyo Electric Co Ltd プログラム実行方法およびその方法を利用した装置
US6088793A (en) * 1996-12-30 2000-07-11 Intel Corporation Method and apparatus for branch execution on a multiple-instruction-set-architecture microprocessor
US5941985A (en) * 1997-06-24 1999-08-24 Sun Microsystems, Inc. Branch instruction prediction method
US5857098A (en) * 1997-06-24 1999-01-05 Samsung Electronics Co., Ltd. Branch instruction prediction apparatus
US5987595A (en) * 1997-11-25 1999-11-16 Intel Corporation Method and apparatus for predicting when load instructions can be executed out-of order
US6151671A (en) * 1998-02-20 2000-11-21 Intel Corporation System and method of maintaining and utilizing multiple return stack buffers
US6055630A (en) * 1998-04-20 2000-04-25 Intel Corporation System and method for processing a plurality of branch instructions by a plurality of storage devices and pipeline units
US6493821B1 (en) 1998-06-09 2002-12-10 Intel Corporation Recovery from writeback stage event signal or micro-branch misprediction using instruction sequence number indexed state information table
US6233678B1 (en) * 1998-11-05 2001-05-15 Hewlett-Packard Company Method and apparatus for profiling of non-instrumented programs and dynamic processing of profile data
US6189091B1 (en) * 1998-12-02 2001-02-13 Ip First, L.L.C. Apparatus and method for speculatively updating global history and restoring same on branch misprediction detection
JP3513038B2 (ja) * 1998-12-10 2004-03-31 富士通株式会社 命令フェッチ制御装置
US6601161B2 (en) 1998-12-30 2003-07-29 Intel Corporation Method and system for branch target prediction using path information
US6499101B1 (en) 1999-03-18 2002-12-24 I.P. First L.L.C. Static branch prediction mechanism for conditional branch instructions
US6484256B1 (en) * 1999-08-09 2002-11-19 International Business Machines Corporation Apparatus and method of branch prediction utilizing a comparison of a branch history table to an aliasing table
US6647490B2 (en) * 1999-10-14 2003-11-11 Advanced Micro Devices, Inc. Training line predictor for branch targets
US6546478B1 (en) 1999-10-14 2003-04-08 Advanced Micro Devices, Inc. Line predictor entry with location pointers and control information for corresponding instructions in a cache line
US6636959B1 (en) 1999-10-14 2003-10-21 Advanced Micro Devices, Inc. Predictor miss decoder updating line predictor storing instruction fetch address and alignment information upon instruction decode termination condition
US6546481B1 (en) 1999-11-05 2003-04-08 Ip - First Llc Split history tables for branch prediction
DE60141807D1 (de) * 2000-02-28 2010-05-27 Nxp Bv Datenprozessor mit meherern befehlen umfassende befehlswörtern
US7107437B1 (en) * 2000-06-30 2006-09-12 Intel Corporation Branch target buffer (BTB) including a speculative BTB (SBTB) and an architectural BTB (ABTB)
US6857060B2 (en) 2001-03-30 2005-02-15 Intel Corporation System, apparatus and method for prioritizing instructions and eliminating useless instructions
US6954849B2 (en) * 2002-02-21 2005-10-11 Intel Corporation Method and system to use and maintain a return buffer
US6950925B1 (en) * 2002-08-28 2005-09-27 Advanced Micro Devices, Inc. Scheduler for use in a microprocessor that supports data-speculative execution
US7337271B2 (en) * 2003-12-01 2008-02-26 International Business Machines Corporation Context look ahead storage structures
US7426631B2 (en) * 2005-02-02 2008-09-16 International Business Machines Corporation Methods and systems for storing branch information in an address table of a processor
US7827392B2 (en) * 2006-06-05 2010-11-02 Qualcomm Incorporated Sliding-window, block-based branch target address cache
US8612731B2 (en) 2009-11-06 2013-12-17 International Business Machines Corporation Branch target buffer for emulation environments
US8533422B2 (en) 2010-09-30 2013-09-10 Intel Corporation Instruction prefetching using cache line history
US9122486B2 (en) 2010-11-08 2015-09-01 Qualcomm Incorporated Bimodal branch predictor encoded in a branch instruction
EP2662767A1 (en) * 2011-01-07 2013-11-13 Fujitsu Limited Computation processing device and branch prediction method
US20130283023A1 (en) * 2012-04-18 2013-10-24 Qualcomm Incorporated Bimodal Compare Predictor Encoded In Each Compare Instruction
JP6523274B2 (ja) * 2013-10-25 2019-05-29 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッドＡｄｖａｎｃｅｄ Ｍｉｃｒｏ Ｄｅｖｉｃｅｓ Ｉｎｃｏｒｐｏｒａｔｅｄ 分岐予測ユニット及びレベル１命令キャッシュにおける帯域幅の増加
US10754781B2 (en) 2017-02-27 2020-08-25 International Business Machines Corporation Heuristic method to control fetching of metadata from a cache hierarchy
US10613867B1 (en) * 2017-07-19 2020-04-07 Apple Inc. Suppressing pipeline redirection indications
US11698789B2 (en) * 2020-10-12 2023-07-11 Microsoft Technology Licensing, Llc Restoring speculative history used for making speculative predictions for instructions processed in a processor employing control independence techniques

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4477872A (en) * 1982-01-15 1984-10-16 International Business Machines Corporation Decode history table for conditional branch instructions
US4679141A (en) * 1985-04-29 1987-07-07 International Business Machines Corporation Pageable branch history table
US4991080A (en) * 1986-03-13 1991-02-05 International Business Machines Corporation Pipeline processing apparatus for executing instructions in three streams, including branch stream pre-execution processor for pre-executing conditional branch instructions
JP2722523B2 (ja) * 1988-09-21 1998-03-04 日本電気株式会社 命令先取り装置
US5142634A (en) * 1989-02-03 1992-08-25 Digital Equipment Corporation Branch prediction
JPH0650465B2 (ja) * 1989-10-16 1994-06-29 株式会社東芝 分岐制御回路
US5210831A (en) * 1989-10-30 1993-05-11 International Business Machines Corporation Methods and apparatus for insulating a branch prediction mechanism from data dependent branch table updates that result from variable test operand locations
US5226130A (en) * 1990-02-26 1993-07-06 Nexgen Microsystems Method and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency
EP0463965B1 (en) * 1990-06-29 1998-09-09 Digital Equipment Corporation Branch prediction unit for high-performance processor
US5265213A (en) * 1990-12-10 1993-11-23 Intel Corporation Pipeline system for executing predicted branch target instruction in a cycle concurrently with the execution of branch instruction
US5442756A (en) * 1992-07-31 1995-08-15 Intel Corporation Branch prediction and resolution apparatus for a superscalar computer processor

Also Published As

Publication number Publication date
SE515698C2 (sv) 2001-09-24
KR100310581B1 (ko) 2001-12-17
JPH09500989A (ja) 1997-01-28
US5584001A (en) 1996-12-10
SE9503951D0 (sv) 1995-11-08

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