SE8405090L - Vlsi-krets som er uppdelad i isokrona regioner, sett for maskinell konstruktion av en sadan krets och sett for maskinell testning av en sadan krets - Google Patents

Vlsi-krets som er uppdelad i isokrona regioner, sett for maskinell konstruktion av en sadan krets och sett for maskinell testning av en sadan krets

Info

Publication number
SE8405090L
SE8405090L SE8405090A SE8405090A SE8405090L SE 8405090 L SE8405090 L SE 8405090L SE 8405090 A SE8405090 A SE 8405090A SE 8405090 A SE8405090 A SE 8405090A SE 8405090 L SE8405090 L SE 8405090L
Authority
SE
Sweden
Prior art keywords
circuit
function block
machine
pair
isokrona
Prior art date
Application number
SE8405090A
Other languages
Unknown language ( )
English (en)
Other versions
SE8405090D0 (sv
Inventor
L Spaanenburg
P B Duin
R Woudsma
Der Poel A A Van
Original Assignee
Philips Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Nv filed Critical Philips Nv
Publication of SE8405090D0 publication Critical patent/SE8405090D0/sv
Publication of SE8405090L publication Critical patent/SE8405090L/sv

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7828—Architectures of general purpose stored program computers comprising a single central processing unit without memory
    • G06F15/7832—Architectures of general purpose stored program computers comprising a single central processing unit without memory on one IC chip (single chip microprocessors)
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Microcomputers (AREA)
SE8405090A 1983-10-14 1984-10-11 Vlsi-krets som er uppdelad i isokrona regioner, sett for maskinell konstruktion av en sadan krets och sett for maskinell testning av en sadan krets SE8405090L (sv)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL8303536A NL8303536A (nl) 1983-10-14 1983-10-14 Geintegreerde schakeling op grote schaal welke verdeeld is in isochrone gebieden, werkwijze voor het machinaal ontwerpen van zo een geintegreerde schakeling, en werkwijze voor het machinaal testen van zo een geintegreerde schakeling.

Publications (2)

Publication Number Publication Date
SE8405090D0 SE8405090D0 (sv) 1984-10-11
SE8405090L true SE8405090L (sv) 1985-04-15

Family

ID=19842560

Family Applications (1)

Application Number Title Priority Date Filing Date
SE8405090A SE8405090L (sv) 1983-10-14 1984-10-11 Vlsi-krets som er uppdelad i isokrona regioner, sett for maskinell konstruktion av en sadan krets och sett for maskinell testning av en sadan krets

Country Status (9)

Country Link
US (1) US4656592A (sv)
JP (1) JPH07107916B2 (sv)
CA (1) CA1224271A (sv)
DE (1) DE3437511A1 (sv)
FR (1) FR2557322B1 (sv)
GB (1) GB2148029B (sv)
IT (1) IT1209591B (sv)
NL (1) NL8303536A (sv)
SE (1) SE8405090L (sv)

Families Citing this family (83)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5230079A (en) * 1986-09-18 1993-07-20 Digital Equipment Corporation Massively parallel array processing system with processors selectively accessing memory module locations using address in microword or in address register
US5146606A (en) * 1986-09-18 1992-09-08 Digital Equipment Corporation Systems for interconnecting and configuring plurality of memory elements by control of mode signals
JP2695160B2 (ja) * 1987-04-30 1997-12-24 株式会社日立製作所 任意形状抵抗体の端子間抵抗計算方法
US4815003A (en) * 1987-06-19 1989-03-21 General Electric Company Structured design method for high density standard cell and macrocell layout of VLSI chips
US4862399A (en) * 1987-08-31 1989-08-29 General Electric Company Method for generating efficient testsets for a class of digital circuits
US5056053A (en) * 1988-02-11 1991-10-08 The Mitre Corporation Algebraic transform machine
US5097468A (en) * 1988-05-03 1992-03-17 Digital Equipment Corporation Testing asynchronous processes
US5003487A (en) * 1988-06-28 1991-03-26 International Business Machines Corporation Method and apparatus for performing timing correction transformations on a technology-independent logic model during logic synthesis
US5452231A (en) * 1988-10-05 1995-09-19 Quickturn Design Systems, Inc. Hierarchically connected reconfigurable logic assembly
US5239465A (en) * 1988-10-11 1993-08-24 Hitachi, Ltd. Method and system for layout design of integrated circuits with a data transferring flow
US5329470A (en) * 1988-12-02 1994-07-12 Quickturn Systems, Inc. Reconfigurable hardware emulation system
US5109353A (en) 1988-12-02 1992-04-28 Quickturn Systems, Incorporated Apparatus for emulation of electronic hardware system
US5276893A (en) * 1989-02-08 1994-01-04 Yvon Savaria Parallel microprocessor architecture
US5353243A (en) * 1989-05-31 1994-10-04 Synopsys Inc. Hardware modeling system and method of use
US5369593A (en) * 1989-05-31 1994-11-29 Synopsys Inc. System for and method of connecting a hardware modeling element to a hardware modeling system
US5210700A (en) * 1990-02-20 1993-05-11 International Business Machines Corporation Automatic delay adjustment for static timing analysis
US5459673A (en) * 1990-10-29 1995-10-17 Ross Technology, Inc. Method and apparatus for optimizing electronic circuits
US5574655A (en) * 1991-10-30 1996-11-12 Xilinx, Inc. Method of allocating logic using general function components
CZ383292A3 (en) * 1992-02-18 1994-03-16 Koninkl Philips Electronics Nv Method of testing electronic circuits and an integrated circuit tested in such a manner
USRE39395E1 (en) 1992-11-02 2006-11-14 Negotiated Data Solutions Llc Data communication network with transfer port, cascade port and/or frame synchronizing signal
USRE39116E1 (en) 1992-11-02 2006-06-06 Negotiated Data Solutions Llc Network link detection and generation
EP0596648A1 (en) 1992-11-02 1994-05-11 National Semiconductor Corporation Network link endpoint capability detection
EP0596651A1 (en) 1992-11-02 1994-05-11 National Semiconductor Corporation Network for data communication with isochronous capability
US5799161A (en) * 1993-06-25 1998-08-25 Intel Corporation Method and apparatus for concurrent data routing
US5422891A (en) * 1993-07-23 1995-06-06 Rutgers University Robust delay fault built-in self-testing method and apparatus
US5680583A (en) * 1994-02-16 1997-10-21 Arkos Design, Inc. Method and apparatus for a trace buffer in an emulation system
JPH0877002A (ja) * 1994-08-31 1996-03-22 Sony Corp 並列プロセッサ装置
US5533018A (en) 1994-12-21 1996-07-02 National Semiconductor Corporation Multi-protocol packet framing over an isochronous network
US5841967A (en) * 1996-10-17 1998-11-24 Quickturn Design Systems, Inc. Method and apparatus for design verification using emulation and simulation
AU5153198A (en) * 1996-10-23 1998-05-15 Rutgers University Method and system for identifying tested path-delay faults
US6134516A (en) * 1997-05-02 2000-10-17 Axis Systems, Inc. Simulation server system and method
US6009256A (en) * 1997-05-02 1999-12-28 Axis Systems, Inc. Simulation/emulation system and method
US6389379B1 (en) 1997-05-02 2002-05-14 Axis Systems, Inc. Converification system and method
US6026230A (en) * 1997-05-02 2000-02-15 Axis Systems, Inc. Memory simulation system and method
US6421251B1 (en) 1997-05-02 2002-07-16 Axis Systems Inc Array board interconnect system and method
US6321366B1 (en) 1997-05-02 2001-11-20 Axis Systems, Inc. Timing-insensitive glitch-free logic system and method
US6099577A (en) * 1997-05-13 2000-08-08 Kabushiki Kaisha Toshiba Logic circuit conversion method and logic circuit design support device
US5960191A (en) * 1997-05-30 1999-09-28 Quickturn Design Systems, Inc. Emulation system with time-multiplexed interconnect
US5970240A (en) * 1997-06-25 1999-10-19 Quickturn Design Systems, Inc. Method and apparatus for configurable memory emulation
JP3777768B2 (ja) * 1997-12-26 2006-05-24 株式会社日立製作所 半導体集積回路装置およびセルライブラリを記憶した記憶媒体および半導体集積回路の設計方法
JP3461443B2 (ja) * 1998-04-07 2003-10-27 松下電器産業株式会社 半導体装置、半導体装置の設計方法、記録媒体および半導体装置の設計支援装置
JP3157775B2 (ja) * 1998-04-14 2001-04-16 日本電気アイシーマイコンシステム株式会社 半導体集積回路装置及びその回路設計方法
US6154137A (en) 1998-06-08 2000-11-28 3M Innovative Properties Company Identification tag with enhanced security
BR9912929A (pt) * 1998-08-14 2001-05-08 3M Innovative Properties Co Sistema de antena, combinação, e, processo para interrogar determinados artigos
JP2002522849A (ja) 1998-08-14 2002-07-23 スリーエム イノベイティブ プロパティズ カンパニー 無線周波数識別システムのアプリケーション
US6424262B2 (en) 1998-08-14 2002-07-23 3M Innovative Properties Company Applications for radio frequency identification systems
US6232870B1 (en) 1998-08-14 2001-05-15 3M Innovative Properties Company Applications for radio frequency identification systems
US6577992B1 (en) 1999-05-07 2003-06-10 Nassda Corporation Transistor level circuit simulator using hierarchical data
US20040069851A1 (en) * 2001-03-13 2004-04-15 Grunes Mitchell B. Radio frequency identification reader with removable media
US20050032151A1 (en) * 2001-06-05 2005-02-10 Eisenberg Peter M. Methods of managing the transfer and use of data
US7588185B2 (en) * 2001-06-07 2009-09-15 3M Innovative Properties Company RFID data collection and use
US6668357B2 (en) * 2001-06-29 2003-12-23 Fujitsu Limited Cold clock power reduction
US6751783B1 (en) * 2001-10-30 2004-06-15 Lsi Logic Corporation System and method for optimizing an integrated circuit design
US6792584B1 (en) 2001-10-30 2004-09-14 Lsi Logic Corporation System and method for designing an integrated circuit
US6654946B1 (en) * 2001-10-30 2003-11-25 Lsi Logic Corporation Interscalable interconnect
US6889366B2 (en) 2001-12-27 2005-05-03 Lsi Logic Corporation System and method for coevolutionary circuit design
US7114133B2 (en) * 2002-01-10 2006-09-26 Lsi Logic Corporation Broken symmetry for optimization of resource fabric in a sea-of-platform architecture
US20040025133A1 (en) * 2002-07-31 2004-02-05 Koford James S. System and method for integrated circuit design
US6857108B2 (en) * 2002-07-31 2005-02-15 Lsi Logic Corporation Interactive representation of structural dependencies in semiconductor design flows
US7299427B2 (en) * 2002-08-30 2007-11-20 Lsi Corporation Radio prototyping system
US7212961B2 (en) * 2002-08-30 2007-05-01 Lsi Logic Corporation Interface for rapid prototyping system
US7043703B2 (en) * 2002-09-11 2006-05-09 Lsi Logic Corporation Architecture and/or method for using input/output affinity region for flexible use of hard macro I/O buffers
US6966044B2 (en) * 2002-12-09 2005-11-15 Lsi Logic Corporation Method for composing memory on programmable platform devices to meet varied memory requirements with a fixed set of resources
US7401057B2 (en) 2002-12-10 2008-07-15 Asset Trust, Inc. Entity centric computer system
US7069523B2 (en) * 2002-12-13 2006-06-27 Lsi Logic Corporation Automated selection and placement of memory during design of an integrated circuit
US7831653B2 (en) * 2002-12-13 2010-11-09 Lsi Corporation Flexible template having embedded gate array and composable memory for integrated circuits
US7055113B2 (en) * 2002-12-31 2006-05-30 Lsi Logic Corporation Simplified process to design integrated circuits
US6823502B2 (en) * 2002-12-31 2004-11-23 Lsi Logic Corporation Placement of configurable input/output buffer structures during design of integrated circuits
US20040153301A1 (en) * 2003-02-03 2004-08-05 Daniel Isaacs Integrated circuit development methodology
US6973630B1 (en) 2003-04-07 2005-12-06 Lsi Logic Corporation System and method for reference-modeling a processor
US6959428B2 (en) * 2003-06-19 2005-10-25 Lsi Logic Corporation Designing and testing the interconnection of addressable devices of integrated circuits
US7305593B2 (en) * 2003-08-26 2007-12-04 Lsi Corporation Memory mapping for parallel turbo decoding
US7111275B2 (en) * 2003-08-28 2006-09-19 International Business Machines Corporation Electronic circuit design analysis system
JP2005083895A (ja) 2003-09-09 2005-03-31 Matsushita Electric Ind Co Ltd 半導体装置のテスト方法
US20050114818A1 (en) * 2003-11-21 2005-05-26 Lsi Logic Corporation Chip design command processor
US8713025B2 (en) 2005-03-31 2014-04-29 Square Halt Solutions, Limited Liability Company Complete context search system
US20120106539A1 (en) * 2010-10-27 2012-05-03 International Business Machines Corporation Coordinating Communications Interface Activities in Data Communicating Devices Using Redundant Lines
US8681839B2 (en) 2010-10-27 2014-03-25 International Business Machines Corporation Calibration of multiple parallel data communications lines for high skew conditions
US8767531B2 (en) 2010-10-27 2014-07-01 International Business Machines Corporation Dynamic fault detection and repair in a data communications mechanism
US8898504B2 (en) 2011-12-14 2014-11-25 International Business Machines Corporation Parallel data communications mechanism having reduced power continuously calibrated lines
US9411750B2 (en) 2012-07-30 2016-08-09 International Business Machines Corporation Efficient calibration of a low power parallel data communications channel
US9292372B2 (en) * 2014-05-18 2016-03-22 Freescale Semiconductor, Inc. Error pad for safety device
US9474034B1 (en) 2015-11-30 2016-10-18 International Business Machines Corporation Power reduction in a parallel data communications interface using clock resynchronization

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3896418A (en) * 1971-08-31 1975-07-22 Texas Instruments Inc Synchronous multi-processor system utilizing a single external memory unit
US3919695A (en) * 1973-12-26 1975-11-11 Ibm Asynchronous clocking apparatus
US4130865A (en) * 1974-06-05 1978-12-19 Bolt Beranek And Newman Inc. Multiprocessor computer apparatus employing distributed communications paths and a passive task register
JPS51137340A (en) * 1975-05-23 1976-11-27 Yokogawa Hokushin Electric Corp Data processing unit
US4065809A (en) * 1976-05-27 1977-12-27 Tokyo Shibaura Electric Co., Ltd. Multi-processing system for controlling microcomputers and memories
US4174514A (en) * 1976-11-15 1979-11-13 Environmental Research Institute Of Michigan Parallel partitioned serial neighborhood processors
US4191996A (en) * 1977-07-22 1980-03-04 Chesley Gilman D Self-configurable computer and memory system
IT1111606B (it) * 1978-03-03 1986-01-13 Cselt Centro Studi Lab Telecom Sistema elaborativo modulare multiconfigurabile integrato con un sistema di preelaborazione
US4286173A (en) * 1978-03-27 1981-08-25 Hitachi, Ltd. Logical circuit having bypass circuit
US4270169A (en) * 1978-05-03 1981-05-26 International Computers Limited Array processor
US4270170A (en) * 1978-05-03 1981-05-26 International Computers Limited Array processor
US4251861A (en) * 1978-10-27 1981-02-17 Mago Gyula A Cellular network of processors
JPS5591853A (en) * 1978-12-29 1980-07-11 Fujitsu Ltd Semiconductor device
NL7901156A (nl) * 1979-02-14 1980-08-18 Philips Nv Systeem voor het asynchroon transporteren van gegevens tussen aktieve deelinrichtingen.
FR2469751A1 (fr) * 1979-11-07 1981-05-22 Philips Data Syst Processeur d'intercommunication du systeme utilise dans un systeme de traitement de donnees reparti
NL7909178A (nl) * 1979-12-20 1981-07-16 Philips Nv Rekenmachine met verspreide redundantie welke is verdeeld over verschillende isolatiegebieden voor fouten.
GB2082354B (en) * 1980-08-21 1984-04-11 Burroughs Corp Improvements in or relating to wafer-scale integrated circuits
GB2083929B (en) * 1980-08-21 1984-03-07 Burroughs Corp Branched labyrinth wafer scale integrated circuit
US4445171A (en) * 1981-04-01 1984-04-24 Teradata Corporation Data processing systems and methods
US4468727A (en) * 1981-05-14 1984-08-28 Honeywell Inc. Integrated cellular array parallel processor
US4484292A (en) * 1981-06-12 1984-11-20 International Business Machines Corporation High speed machine for the physical design of very large scale integrated circuits
US4397021A (en) * 1981-06-15 1983-08-02 Westinghouse Electric Corp. Multi-processor automatic test system
JPS57207347A (en) * 1981-06-16 1982-12-20 Mitsubishi Electric Corp Semiconductor device
EP0081309B1 (en) * 1981-12-08 1989-01-04 Unisys Corporation Constant-distance structure polycellular very large scale integrated circuit

Also Published As

Publication number Publication date
US4656592A (en) 1987-04-07
JPS60108937A (ja) 1985-06-14
SE8405090D0 (sv) 1984-10-11
IT1209591B (it) 1989-08-30
NL8303536A (nl) 1985-05-01
JPH07107916B2 (ja) 1995-11-15
FR2557322A1 (fr) 1985-06-28
GB8425824D0 (en) 1984-11-21
IT8423095A0 (it) 1984-10-11
GB2148029A (en) 1985-05-22
DE3437511A1 (de) 1985-04-25
GB2148029B (en) 1987-04-15
CA1224271A (en) 1987-07-14
FR2557322B1 (fr) 1991-03-15

Similar Documents

Publication Publication Date Title
SE8405090L (sv) Vlsi-krets som er uppdelad i isokrona regioner, sett for maskinell konstruktion av en sadan krets och sett for maskinell testning av en sadan krets
US5486783A (en) Method and apparatus for providing clock de-skewing on an integrated circuit board
DE3851001D1 (de) Taktgeberschema für ein VLSI-System.
NO803650L (no) R koplingsstykke med null innfoeringskraft for lsi-kretspakke
FR2203231B1 (sv)
SE8603749L (sv) Forfarande for testning av berare forsedda med ett flertal digitala integrerade kretsar, berare forsedd med sadana kretsar, integrerad krets lempad for montering pa en sadan berare och testanordning for testning av sada
KR920007138A (ko) 프로세스 모니터 회로 및 그 방법
TW428129B (en) Data path clock skew management in a dynamic power management environment
SE8604262L (sv) Databehandlingsanordning bestaende av ett flertal parallellarbetande databehandlingsmoduler, multipel redundant klockanordning med ett antal inbordes sjelvsynkroniserande klockkretsar avsedd att anvendas i en sadan data
KR900014970A (ko) 동기 회로
MX164336B (es) Aparato y metodo para sincronizar los bordes de entrada de un par de seeales digitales
DE3365089D1 (en) Testing method for high speed logic designs using low speed tester
DE69531597D1 (de) Testmethode und flipflop mit mutter- und tochtereinheit umfassender elektronischer schaltkreis
ES451922A1 (es) Un metodo de supervision de senales de un reloj en un siste-ma de datos digitales.
SE7701959L (sv) In- och utmatningsanordning for en dator
JP2515704B2 (ja) 半導体集積回路装置
JPS55138128A (en) Memory circuit
Svensson Signal resynchronization in VLSI systems
JPS57199040A (en) Synchronizing device for data transfer
IT1238149B (it) Sistema logico per la trasmissione di dati tra periferiche con generatori di sincronizzazione della emissione e di coincidenza per la rilevazione dei dati
DE3472593D1 (en) Device for testing and sorting of electronic components, especially of integrated circuits
JPS52144253A (en) Flip-flop circuit
JPS5785124A (en) Clock distributing system
JPS5566131A (en) Integrated circuit
JPS5667451A (en) Operation inspecting system

Legal Events

Date Code Title Description
NAV Patent application has lapsed

Ref document number: 8405090-5

Effective date: 19900501