SE7910530L - SET TO MANUFACTURE INTEGRATED CIRCUITS - Google Patents
SET TO MANUFACTURE INTEGRATED CIRCUITSInfo
- Publication number
- SE7910530L SE7910530L SE7910530A SE7910530A SE7910530L SE 7910530 L SE7910530 L SE 7910530L SE 7910530 A SE7910530 A SE 7910530A SE 7910530 A SE7910530 A SE 7910530A SE 7910530 L SE7910530 L SE 7910530L
- Authority
- SE
- Sweden
- Prior art keywords
- substrate
- conductivity
- epitaxial layer
- stages
- zones
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title abstract 2
- 239000000758 substrate Substances 0.000 abstract 5
- 238000009792 diffusion process Methods 0.000 abstract 1
- 239000002019 doping agent Substances 0.000 abstract 1
- 238000009413 insulation Methods 0.000 abstract 1
- 230000000873 masking effect Effects 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/761—PN junctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0821—Collector regions of bipolar transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Bipolar Transistors (AREA)
- Bipolar Integrated Circuits (AREA)
- Element Separation (AREA)
Abstract
In a method for producing a plurality of integrated semiconductor devices e.g. vertical, planar transistors on a monocrystalline substrate (1) zones (3) strongly doped with a second type of conductivity which is opposite to that of the substrate are formed by diffusion and then there is grown uniformly over the face (2) of the substrate (1) an epitaxial layer (4,5) into which various doping agents are successively diffused with selective masking to form insulation columns (6), a base zone (7) and an emitter zone (8). This epitaxial growth is divided into two stages, the first of which is to form a first uniformly distributed layer (4) of the same type of conductivity as the substrate (1) and having a thickness which is limited such that in the finished structure the diffused zones (3) are not covered by this first epitaxial layer (4). The second of the stages is to form a second uniformly distributed epitaxial layer (5) of opposite conductivity to that of the substrate (1). <IMAGE>
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IT31304/78A IT1101096B (en) | 1978-12-22 | 1978-12-22 | IMPROVEMENT OF THE PROCEDURE TO PRODUCE INTEGRATED SEMICONDUCTOR DEVICES AND RESULTING PRODUCT |
Publications (1)
Publication Number | Publication Date |
---|---|
SE7910530L true SE7910530L (en) | 1980-06-23 |
Family
ID=11233426
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SE7910530A SE7910530L (en) | 1978-12-22 | 1979-12-20 | SET TO MANUFACTURE INTEGRATED CIRCUITS |
Country Status (6)
Country | Link |
---|---|
JP (1) | JPS55108762A (en) |
DE (1) | DE2951821A1 (en) |
FR (1) | FR2445022A1 (en) |
GB (1) | GB2039415A (en) |
IT (1) | IT1101096B (en) |
SE (1) | SE7910530L (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3276888D1 (en) * | 1981-01-29 | 1987-09-03 | Toshiba Kk | Semiconductor device |
US4902633A (en) * | 1988-05-09 | 1990-02-20 | Motorola, Inc. | Process for making a bipolar integrated circuit |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS51123577A (en) * | 1975-04-22 | 1976-10-28 | Toshiba Corp | Semiconductor integrating circuit including epitaxial base typ vertica l directional transistor |
-
1978
- 1978-12-22 IT IT31304/78A patent/IT1101096B/en active
-
1979
- 1979-12-05 FR FR7929840A patent/FR2445022A1/en not_active Withdrawn
- 1979-12-20 SE SE7910530A patent/SE7910530L/en not_active Application Discontinuation
- 1979-12-21 JP JP16577079A patent/JPS55108762A/en active Pending
- 1979-12-21 DE DE19792951821 patent/DE2951821A1/en not_active Withdrawn
- 1979-12-24 GB GB7944398A patent/GB2039415A/en not_active Withdrawn
Also Published As
Publication number | Publication date |
---|---|
IT7831304A0 (en) | 1978-12-22 |
GB2039415A (en) | 1980-08-06 |
JPS55108762A (en) | 1980-08-21 |
IT1101096B (en) | 1985-09-28 |
DE2951821A1 (en) | 1980-07-03 |
FR2445022A1 (en) | 1980-07-18 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
NAV | Patent application has lapsed |
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