GB2039415A - A method for producing integrated semiconductor devices, and the resultant product - Google Patents
A method for producing integrated semiconductor devices, and the resultant product Download PDFInfo
- Publication number
- GB2039415A GB2039415A GB7944398A GB7944398A GB2039415A GB 2039415 A GB2039415 A GB 2039415A GB 7944398 A GB7944398 A GB 7944398A GB 7944398 A GB7944398 A GB 7944398A GB 2039415 A GB2039415 A GB 2039415A
- Authority
- GB
- United Kingdom
- Prior art keywords
- type
- conductivity
- substrate
- layer
- epitaxial
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 7
- 239000004065 semiconductor Substances 0.000 title claims abstract description 5
- 238000009792 diffusion process Methods 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 238000009413 insulation Methods 0.000 claims abstract description 16
- 239000002019 doping agent Substances 0.000 claims abstract description 6
- 230000000873 masking effect Effects 0.000 claims abstract description 3
- 238000000034 method Methods 0.000 claims description 5
- 238000004904 shortening Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 238000013517 stratification Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/761—PN junctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0821—Collector regions of bipolar transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Bipolar Transistors (AREA)
- Bipolar Integrated Circuits (AREA)
- Element Separation (AREA)
Abstract
In a method for producing a plurality of integrated semiconductor devices e.g. vertical, planar transistors on a monocrystalline substrate (1) zones (3) strongly doped with a second type of conductivity which is opposite to that of the substrate are formed by diffusion and then there is grown uniformly over the face (2) of the substrate (1) an epitaxial layer (4,5) into which various doping agents are successively diffused with selective masking to form insulation columns (6), a base zone (7) and an emitter zone (8). This epitaxial growth is divided into two stages, the first of which is to form a first uniformly distributed layer (4) of the same type of conductivity as the substrate (1) and having a thickness which is limited such that in the finished structure the diffused zones (3) are not covered by this first epitaxial layer (4). The second of the stages is to form a second uniformly distributed epitaxial layer (5) of opposite conductivity to that of the substrate (1). <IMAGE>
Description
SPECIFICATION
A method for producing integrated semiconductor devices, and the resultant product
This invention relates to a method for producing integrated devices containing bipolar transistors of epitaxial planar type, and in particular vertical transistors provided with a buried layer.
In these types of transistors, the buried layer zone is strongly doped, and both the epitaxial growth stages and the stages of prolonged time diffusion at high temperature contribute to increasing the out-diffusion of the buried layer.
The out-diffusion of the buried layer can be defined as the expansion of the buried layer volume into the epitaxial layer which lies above it, this latter layer being functionally active as the collector zone. It follows that if the thickness of the epitaxial layer and the depth of the diffused base zone are kept constant, then the collector zone is reduced in thickness, with consequent reduction in the V(BR)CBO if the out-diffusion of the buried layer increases.
An object of the present invention is to reduce the actual value of the thickness loss by out-diffusion by reducing the diffusion time for the insulation columns.
According to this invention there is provided a method for producing a plurality of integrated semi-conductor devices of the epitaxial planar type on a monocrystalline substrate of a first type of conductivity and in the form of a slice comprising diffusing, on a first face of the substrate, in positions corresponding with the active zones for transistors of vertical structure, zones of limited area strongly doped with a second type of conductivity which is opposite to the first type, and growing uniformly over this entire first face an epitaxial layer into which various doping agents are successively diffused with selective masking to form insulation columns, a base zone, and an emitter zone, which are differently doped, the uniform epitaxial growth on the first face is divided into two stages, the first of which being to form a first uniformly distributed layer of the same type of conductivity as the substrate and having a thickness which is limited such that at the end of all the necessary operations for completing the device, said diffused zones of limited area strongly doped with the second type of conductivity opposite to the first type are not covered by the first epitaxial layer, and the second of said stages being to form a second uniformly distributed epitaxial layer, which is of opposite conductivity to that of the substrate, which forms a junction with the diffused zones and with the first layer, and is of adequate thickness for the necessary rupture voltage V(BR)CBO of the vertical transistors; the insulation diffusion proceeding until the diffused insulation columns have a depth equal to that of the epitaxial layer produced in the second stage.
The diffusion time for the insulation columns produced by the method according to the invention is reduced by shortening the length of these columns, as is explained hereinafter. A further advantage of considerable importance from the cost aspect is the reduction in the total area occupied by the device on the slice. In this respect, shortening the insulation columns also leads to a reduction in the area occupied by them on the slice, as the diffusion by which they are crested proceeds both in a vertical direction (depth) and in a lateral direction. Thus, by keeping the minimum distance between the base-collector junction and the adjacent insulation column constant, it is possible according to the invention to shorten the distance between the centres of the insulation column and the base-collector junction.As a result, the total area of the device is approximately 25-30% less than that of the conventional structure.
The thickness of the second layer is substantially less than that which would have to be grown with equal polarity to obtain the same V(BR)cBo by means of the known art.
Taking account of the fact that the out-diffusion of the buried layer at the end of the diffusion operations according to the known art is about one third (from experimental knowledge using the normal concentrations of doping agent) of the total thickness of the epitaxial layer superposed on the substrate, it is easily apparent that by dividing this total thickness into two thicknesses, the second of which is at least two thirds of the total, and possesses the characteristic of being the only one which requires insulation columns for forming independent devices within the same integrated circuit, the insulation diffusion time is also reduced to an equal extent.
A method and a device according to this invention will now be described, with reference to the accompanying drawings which are not to scale and in which:
Figure 1 conains the notation used for comparing a vertical planar transistor obtainable in an integrated circuit according to the known art with one according to the invention; and
Figure 2 shows the structure of a device according to the invention.
Figure 1:
This Figure serves to clarify the effect of the stratification of the epitaxial growth into two distinct stages according to the invention, in comparison with the known art. As a first approximation, the common assumptions are that the diffusion speed of the doping agents is constant, that the thickness of out-diffusion the theburied layer is directly proportional to the thickness of the epitaxial layer containing the insulation, and that the extent of the out-diffusion of the buried layer at the end of all of the operations is equivalent to one third of this layer.
The meaning of the notation is as follows: Si is the epitaxial thickness to be insulated according to the known art.
S2 is the epitaxial thickness to be insulated according to the invention.
D1 is the thickness of the out-diffusion of the buried layer towards the base according to the known art.
K1, K2 is the sum of the depth of diffusion of the base and the useful collector zone in the absence of polarisation between the base and collector.
In the particular case of comparison between the known art and the improved method according to the invention:1) K1=K2 2) S1 = D1 + K1 3) D1 = S,/3 4) S2 = K2 = K1 5) Sa~S2 52= D1 + K1 - K1 = Sa/3 The empirical relationship 5) shows the advantage according to the invention, by which for equal values of V#a##ceo, the epitaxial thickness to be insulated is less than the epitaxial thickness necessary with the known art by one third.
Figure 2:
This Figure, which is not to scale, shows an integrated device containing by way of example a vertical planar NPN transistor constructed by the improved method of the invention.
A N+ doped layer of limited area 3 is formed on the P- doped substrate 1 by predoping and preliminary diffusion. The layer 3, the initial thickness of which is contained within the substrate 1 at the level of the face 2 by predisposing the N+ doping agent, is initially prepared according to the known art for obtaining the buried layer. After this preparation, the first stage of the epitaxial deposition according to the invention is carried out. Consequently, the layer 4, which is P- doped as the substrate, is grown on the plane 2, such that at the end of all the operations its thickness is slightly less than that of the buried layer which expands during these operations. In the Figure, the complete buried layer 3 is shown with substantial penetration into the second epitaxial layer for greater clarity. The second epitaxial layer 5 sther grown on the layer 4 and the buried layer 3, and is N- doped. The P+ doped insulation columns 6 have a sleight limited to the thickness of the layer 5 in which are located the active zones of the transistor, namely the collector 9, base 7 and emitter 8.
Ohmic contacts 10, 11 and 12 are finally fitted to said zones for the electrical connections to the device.
Claims (3)
1. A method for producing a plurality of integrated ser dconductor devices of the epitaxial planar type on a monocrystalline substrate of a first type of conductivity and in the form of a slice comprising diffusing, on a first face of the substrate, in positions corresponding with the active zones for transistors of vertical structure, zones of limited area strongly doped with a second type of conductivity which is opposite to the first type, and growing uniformly over this entire first face an epitaxial layer into which various doping agents are successively diffused with selective masking to form insulation columns, a base zone, and an emitter zone, which are differently doped, the uniform epitaxial growth on the first face is divided into two stages, the first of which being to form a first uniformly distributed layer of the same type of conductivity as the substrate and having a thickness which is limited such that at the end of all the necessary operations for completing the device, said diffused zones of limited area strongly doped with the second type of conductivity opposite to the first type are not covered by the first epitaxial layer, and the second of said stages being to form a second uniformly distributed epitaxial layer, which is of opposite conductivity to that of the substrate, which forms a junction with the diffused zones and with the first layer, and is of adequate thickness for the necessary rupture voltage V(BR)cBo of the vertical transistors; the insulation diffusion proceeding until the diffused insulation columns have a depth equal to that of the epitaxial layer produced in the second stage.
2. A method for producing a plurality of integrated semiconductor devices of the epitaxial planar type on a monocrystalline substrate of a first type of conductivity and in the form of a slice substantially as hereinbefore described with reference to the accompanying drawings.
3. An integrated device containing at least one bipolar transistor produced by a method as claimed in claim 1 or claim 2.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| IT31304/78A IT1101096B (en) | 1978-12-22 | 1978-12-22 | IMPROVEMENT OF THE PROCEDURE TO PRODUCE INTEGRATED SEMICONDUCTOR DEVICES AND RESULTING PRODUCT |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB2039415A true GB2039415A (en) | 1980-08-06 |
Family
ID=11233426
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB7944398A Withdrawn GB2039415A (en) | 1978-12-22 | 1979-12-24 | A method for producing integrated semiconductor devices, and the resultant product |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JPS55108762A (en) |
| DE (1) | DE2951821A1 (en) |
| FR (1) | FR2445022A1 (en) |
| GB (1) | GB2039415A (en) |
| IT (1) | IT1101096B (en) |
| SE (1) | SE7910530L (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0057549B1 (en) * | 1981-01-29 | 1987-07-29 | Kabushiki Kaisha Toshiba | Semiconductor device |
| US4902633A (en) * | 1988-05-09 | 1990-02-20 | Motorola, Inc. | Process for making a bipolar integrated circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51123577A (en) * | 1975-04-22 | 1976-10-28 | Toshiba Corp | Semiconductor integrating circuit including epitaxial base typ vertica l directional transistor |
-
1978
- 1978-12-22 IT IT31304/78A patent/IT1101096B/en active
-
1979
- 1979-12-05 FR FR7929840A patent/FR2445022A1/en not_active Withdrawn
- 1979-12-20 SE SE7910530A patent/SE7910530L/en not_active Application Discontinuation
- 1979-12-21 JP JP16577079A patent/JPS55108762A/en active Pending
- 1979-12-21 DE DE19792951821 patent/DE2951821A1/en not_active Withdrawn
- 1979-12-24 GB GB7944398A patent/GB2039415A/en not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| DE2951821A1 (en) | 1980-07-03 |
| IT1101096B (en) | 1985-09-28 |
| JPS55108762A (en) | 1980-08-21 |
| FR2445022A1 (en) | 1980-07-18 |
| IT7831304A0 (en) | 1978-12-22 |
| SE7910530L (en) | 1980-06-23 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |