SE7909953L - SET FOR MANUFACTURING AN INTEGRATED SEMICONDUCTOR DEVICE - Google Patents

SET FOR MANUFACTURING AN INTEGRATED SEMICONDUCTOR DEVICE

Info

Publication number
SE7909953L
SE7909953L SE7909953A SE7909953A SE7909953L SE 7909953 L SE7909953 L SE 7909953L SE 7909953 A SE7909953 A SE 7909953A SE 7909953 A SE7909953 A SE 7909953A SE 7909953 L SE7909953 L SE 7909953L
Authority
SE
Sweden
Prior art keywords
angstrom
grown
layer
zones
minute
Prior art date
Application number
SE7909953A
Other languages
Unknown language ( )
Swedish (sv)
Other versions
SE454631B (en
Inventor
A Casadei
M Camagni
F Bertotti
P Carmina
A Cuccia
V Prestileo
B Sanasi
Original Assignee
Ates Componenti Elettron
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ates Componenti Elettron filed Critical Ates Componenti Elettron
Publication of SE7909953L publication Critical patent/SE7909953L/en
Publication of SE454631B publication Critical patent/SE454631B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/763—Polycrystalline semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H01L21/02576—N-type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743—Making of internal connections, substrate contacts

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Bipolar Transistors (AREA)

Abstract

In a method for producing an integrated semiconductor device which contains a vertical epitaxial planar NPN bipolar transistor and isolation columns on an epitaxially grown P-type substrate 1 of (100) orientation, a layer is provided which comprises semiconducting regions of polycrystalline silicon for isolation zones 7 and collector connector zones 8, and monocrystalline type silicon for the remaining parts. The polycrystalline and epitaxial layers are grown in three separate stages using chemical vapour deposition. In the first stage, collector connector zones 8 and isolation zones 7 are grown to a thickness of about 6000 ANGSTROM -8000 ANGSTROM , Fig. 5, at a growth rate of about 1 000 ANGSTROM /minute. The second layer extends beyond the areas already grown in the first stage to the remaining areas of the substrate, Fig. 6, to produce a layer 10 of about 30,000 ANGSTROM , thickness, at a growth rate of 2000 to 3000 ANGSTROM /minute. In the third growth stage, Fig. 7, a layer 12 is grown at a rate of 10,000 to 15,000 ANGSTROM /minute. <IMAGE>
SE7909953A 1978-12-04 1979-12-03 SET FOR MANUFACTURING AN INTEGRATED SEMICONDUCTOR DEVICE WITH EPITAXIAL GROWTH DIVIDED IN THREE SEPARATE STEPS STABILIZED AT THREE DIFFERENT TEMPERATURES SE454631B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT30507/78A IT1101183B (en) 1978-12-04 1978-12-04 IMPROVEMENT IN THE PRODUCTION PROCESS FOR BIPOLAR TRANSISTORS INTAGRATED WITH HIGH BREAKDOWN VOLTAGE COLLECTOR-EMITTER AND RESULTING PRODUCT

Publications (2)

Publication Number Publication Date
SE7909953L true SE7909953L (en) 1980-06-05
SE454631B SE454631B (en) 1988-05-16

Family

ID=11229874

Family Applications (1)

Application Number Title Priority Date Filing Date
SE7909953A SE454631B (en) 1978-12-04 1979-12-03 SET FOR MANUFACTURING AN INTEGRATED SEMICONDUCTOR DEVICE WITH EPITAXIAL GROWTH DIVIDED IN THREE SEPARATE STEPS STABILIZED AT THREE DIFFERENT TEMPERATURES

Country Status (5)

Country Link
DE (1) DE2948800A1 (en)
FR (1) FR2443742A1 (en)
GB (1) GB2037487A (en)
IT (1) IT1101183B (en)
SE (1) SE454631B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT201600130185A1 (en) * 2016-12-22 2018-06-22 St Microelectronics Srl PROCESS OF MANUFACTURING A SEMICONDUCTOR DEVICE INTEGRATING A VERTICAL CONDUCTIVE TRANSISTOR, AND SEMICONDUCTOR DEVICE

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1300768A (en) * 1969-07-29 1972-12-20 Fairchild Camera Instr Co Improvements in or relating to semiconductor structures

Also Published As

Publication number Publication date
IT1101183B (en) 1985-09-28
FR2443742A1 (en) 1980-07-04
IT7830507A0 (en) 1978-12-04
GB2037487A (en) 1980-07-09
DE2948800A1 (en) 1980-06-19
FR2443742B1 (en) 1985-03-08
SE454631B (en) 1988-05-16

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