JPH01101648A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To increase the density of an element by sequentially stacking an insulating film, an impurity doped polycrystalline film, and an insulating film on the silicon substrate, exposing the surface of the semiconductor substrate after forming a groove, and selectively growing a single crystal in the groove using a single crystal substrate as a seed. CONSTITUTION:An SiO2 film 2, a polycrystalline silicon film 3, and an SiO2 film 4 are formed sequentially on a P-type silicon substrate 1, and then a groove 5 is formed by partially removing by reactive ion etching the SiO2 film 4, the polycrystalline silicon film 3, the SiO2 film 2 in this order to expose the surface of the silicon substrate 1. Then by having the silicon epitaxially grown selectively using dichlorosilane and hydrogen chloride, the groove 5 is buried with a single-crystal silicon 6. According to the constitution, it is allowed to obtain a device structure whose parasitic capacitance for source and drain regions is extremely small with high density.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device (MOS (
Metal-Oxide-3emiconductor
) type element or lvl I 3 ()letal-I
The present invention relates to a method of manufacturing an nsulator-3 semiconductor device.

[Prior Art] The present invention is effective for a general MIS type device manufacturing method, but it is also effective for silicon MO3 which has extremely high versatility as a device.
This will be explained using a type element as an example.

Conventionally, a silicon MO8 type element has been formed as shown in FIG. 2. That is, an element isolation region 12 and a silicon region 13 are formed on a silicon substrate 11 as shown in FIG. 2(a).・Such a structure can be formed by (1) using selective oxidation of the silicon substrate, (2) forming a groove in the silicon substrate and filling it with an insulator, or (3) using an insulating film formed on the silicon substrate. A method used is to form a groove to expose a portion of the silicon substrate surface, and then fill the groove with a silicon single crystal film.

Thereafter, the silicon surface is oxidized to form a thin oxide film 14, polycrystalline silicon 15 is roughly deposited, polycrystalline silicon 15 is patterned, and source regions 16 are formed by ion implantation.
By forming the drain region 17 as shown in FIG.
The basic structure of the MO3 type element shown in FIG.

[Problems to be Solved by the Invention] Increasing the density of elements and reducing stray capacitance are important for increasing the speed of devices, but from this perspective, the above-mentioned conventional method for manufacturing MO3 type elements has several have shortcomings. That is, in the method of FIG. 2, polycrystalline silicon 1
Although the step of patterning 5 is included, considering the alignment margin etc., this is one of the factors that prevents higher density of elements, so it is preferable that this step can be performed by a self-alignment line.

Further, the lower structure of the source region 16 and the drain region 17 is not necessary for the device structure, and serves only as a parasitic capacitance, which is undesirable because it rather impedes the speeding up of the device.

The present invention has been made in order to eliminate the conventional drawbacks as described above, and is capable of manufacturing a semiconductor device that can increase the density of elements and reduce the parasitic capacitance of the source and drain regions. The purpose is to provide a method.

[Means for Solving the Problems] The present invention includes a step of sequentially laminating an insulating film, a polycrystalline film, and an insulating film on a semiconductor substrate, and forming grooves at predetermined locations on the laminated surface to form a single layer on the substrate. a step of exposing the crystal surface;
The method includes a step of selectively growing a single crystal in the trench using the exposed single crystal as a seed, and also growing a crystal from the polycrystalline film exposed on the side wall of the trench, and a step of forming an insulating film on the surface of the grown film. A method of manufacturing a semiconductor device is characterized in that:

[Operation] An insulating film, an impurity-doped polycrystalline film, and an insulating film are sequentially laminated on a silicon substrate, grooves are processed to expose the semiconductor surface of the substrate, and the single crystal substrate is used as a seed to selectively fill the grooves. to grow a single crystal. During selective growth, the polycrystalline silicon exposed on the sidewalls also grows, although at a slower rate than single crystal silicon. This grown polycrystalline silicon region is used as a source and a drain. Because the growth rate of polycrystalline silicon is much slower than single crystal, the area of polycrystalline silicon that reaches the growth surface is very small, so the source and train regions do not extend much laterally from the sidewalls and do not extend into isolation regions. Since there is a thick silicon dioxide film under the buried polycrystalline silicon film, there is almost no parasitic capacitance.

Furthermore, the alignment margin due to patterning of the polycrystalline silicon 15, which the conventional method had, is eliminated, and the device can be made more dense.

[Example] Next, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a schematic cross-sectional view showing the steps of an embodiment of the present invention.

FIG. 1(a) shows a silicon dioxide film 2, a polycrystalline silicon film 3, and a silicon dioxide film 4 formed in this order on a P-type silicon substrate 1. The silicon dioxide film 4 and polycrystalline silicon film 3 are etched by reactive ion etching. , silicon dioxide film 2
are sequentially partially removed to form grooves 5, and the silicon substrate 1 is
The surface is exposed. Since the polycrystalline silicon film 3 will eventually become part of the source and drain wiring, it is doped with arsenic, which is an N-type impurity, and is patterned in accordance with the device.

Figure 1(b) shows dichlorosilane (Sit-hcffi2).
) and hydrogen chloride (HC) to perform selective epitaxial growth of silicon, and fill the trench 5 with single crystal silicon 6. Since the polycrystalline silicon film 3 is exposed on the side wall, During growth, polycrystalline silicon 7 also grows from the sidewalls using polycrystalline silicon as seeds.Since the growth rate of polycrystalline silicon is much slower than that of single crystal silicon, the area of polycrystalline silicon that reaches the growth surface is very small. Since polycrystalline silicon is doped with arsenic, the grown polycrystalline silicon 7 is also doped with arsenic at a high temperature.A thin gate oxide film is necessarily formed on the surface by thermal oxidation, and then The basic structure of the MO3 type device can be made by depositing polycrystalline silicon. Although polycrystalline silicon needs to be patterned, the conventional patterning of polycrystalline silicon does not require any precision.

As is clear from the structure of FIG. 1(b), the source and drain regions hardly spread laterally from the sidewalls, and there are Since the thick silicon dioxide film 2 is covered, the structure has almost no parasitic capacitance.

The above embodiment shows an N-type MOS transistor, but if the N-type and P-type regions are exchanged cr, it becomes a P-type MOS transistor as it is.
An S transistor can be formed.

[Effect of the invention] As described above, according to the present invention, MOS or MI
Compared to the conventional method, it is possible to fabricate an S-type device with higher density and extremely small parasitic capacitance in the source and drain regions, that is, a device structure that is effective for increasing speed.

[Brief explanation of the drawing]

FIG. 1 is a schematic cross-sectional view showing the steps of an embodiment of the present invention;
FIG. 2 is a schematic cross-sectional view showing a conventional process. 1.11... Silicon substrate 2.4... Silicon dioxide film 3... Polycrystalline silicon film 5... Groove 6... Single crystal silicon

Claims (1)

[Claims] (1) A process of sequentially laminating an insulating film, a polycrystalline film, and an insulating film on a semiconductor substrate, a process of forming grooves at predetermined locations on the laminated surface to expose the single crystal surface of the substrate, and a process of exposing the single crystal surface of the substrate; A method comprising the steps of selectively growing a single crystal in a groove using a crystal as a seed, and also growing a crystal from a polycrystalline film exposed on the side wall of the trench, and forming an insulating film on the surface of the grown film. A method for manufacturing a semiconductor device, characterized by: