SE7903354L - BINER MULTIPLICATOR CIRCUIT - Google Patents
BINER MULTIPLICATOR CIRCUITInfo
- Publication number
- SE7903354L SE7903354L SE7903354A SE7903354A SE7903354L SE 7903354 L SE7903354 L SE 7903354L SE 7903354 A SE7903354 A SE 7903354A SE 7903354 A SE7903354 A SE 7903354A SE 7903354 L SE7903354 L SE 7903354L
- Authority
- SE
- Sweden
- Prior art keywords
- product
- coded
- register
- bit
- accumulator register
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/49—Computations with a radix, other than binary, 8, 16 or decimal, e.g. ternary, negative or imaginary radices, mixed radix non-linear PCM
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
- H03M7/50—Conversion to or from non-linear codes, e.g. companding
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Optimization (AREA)
- Computing Systems (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Nonlinear Science (AREA)
- Pure & Applied Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
- Image Processing (AREA)
- Complex Calculations (AREA)
- Error Detection And Correction (AREA)
- Facsimile Image Signal Circuits (AREA)
Abstract
A binary multiplier circuit wherein the product is expressed in coded form as soon as the linear (or non-coded) product is produced. When a twelve-bit binary number in a register 10 is multiplied by another twelve-bit binary number in a register 12 a twenty-four bit binary number is produced in an accumulator register 15. The twenty-four bit product can be coded into an unsigned seven-bit binary number ( mu -255 code) as follows. The number 33 x 2<11> in binary form is preset in accumulator register 15 which at the end of the multiplication contains an augmented product. The number of leading zeroes in the augmented product is counted by a counter 23 which counts clock pulses and is reset by each 1 fed to accumulator register 15, and the base-minus-one complement of the count is formed by inverters 32, 33, 34 and used as the three most significant bits of the coded product. The four next most significant bits of the augmented product, after the most significant logic 1, are, at the end of the multiplication, stored in a latch 26, which is loaded by each 1 fed to accumulator register 15, and four least significant bits of the coded product. A sign bit for the coded product may be supplied at 37. <IMAGE>
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA301,370A CA1089569A (en) | 1978-04-18 | 1978-04-18 | Binary multiplier circuit including coding circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| SE7903354L true SE7903354L (en) | 1979-10-19 |
| SE440562B SE440562B (en) | 1985-08-05 |
Family
ID=4111272
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| SE7903354A SE440562B (en) | 1978-04-18 | 1979-04-17 | MULTIPLICATOR CIRCUIT FOR MULTIPLICATING A FIRST BINER NUMBER WITHOUT SIGN WITH ANOTHER BINERIC NUMBER WITHOUT SIGN AND CREATING A CODED BINER PRODUCT WITHOUT SIGN |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JPS583252B2 (en) |
| CA (1) | CA1089569A (en) |
| FR (1) | FR2423821A1 (en) |
| GB (1) | GB2020068B (en) |
| SE (1) | SE440562B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0452064U (en) * | 1990-09-10 | 1992-05-01 |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR1086043A (en) * | 1953-07-02 | 1955-02-09 | Electronique & Automatisme Sa | Improvements to multipliers for digital electric calculators |
| FR2276635A1 (en) * | 1974-06-28 | 1976-01-23 | Jeumont Schneider | FAST DIGITAL MULTIPLIER AND ITS APPLICATIONS |
| GB1597468A (en) * | 1977-06-02 | 1981-09-09 | Post Office | Conversion between linear pcm representation and compressed pcm |
-
1978
- 1978-04-18 CA CA301,370A patent/CA1089569A/en not_active Expired
-
1979
- 1979-04-05 GB GB7911981A patent/GB2020068B/en not_active Expired
- 1979-04-16 JP JP54045522A patent/JPS583252B2/en not_active Expired
- 1979-04-17 FR FR7909666A patent/FR2423821A1/en active Granted
- 1979-04-17 SE SE7903354A patent/SE440562B/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| SE440562B (en) | 1985-08-05 |
| JPS583252B2 (en) | 1983-01-20 |
| GB2020068A (en) | 1979-11-07 |
| JPS54140434A (en) | 1979-10-31 |
| FR2423821B1 (en) | 1984-11-02 |
| GB2020068B (en) | 1982-09-02 |
| FR2423821A1 (en) | 1979-11-16 |
| CA1089569A (en) | 1980-11-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0398568A3 (en) | Multiplier circuit | |
| JPS55153052A (en) | Digital multiplier | |
| SE7903354L (en) | BINER MULTIPLICATOR CIRCUIT | |
| US3373269A (en) | Binary to decimal conversion method and apparatus | |
| GB977430A (en) | Apparatus to generate an electrical binary representation of a number from a succession of electrical binary representations of decimal digits of the number | |
| GB1274155A (en) | Electronic system for use in calculators | |
| GB1042786A (en) | Improvements in or relating to calculating machines | |
| JPS5652438A (en) | Decoding circuit | |
| GB1138559A (en) | Binary-decimal converters | |
| SU1291973A1 (en) | Dividing device | |
| JPS5676844A (en) | Divider circuit | |
| JPS55164942A (en) | Division circuit | |
| JPS5759227A (en) | Input equipment | |
| FR2445982A1 (en) | Format changing circuit for pure binary number - has data input register for highest character and intermediate register for remaining characters | |
| JPS5550777A (en) | Information compression device | |
| GB1306256A (en) | ||
| JPS564839A (en) | Operating method for software | |
| JPS57113154A (en) | Generator for test data | |
| JPS55150042A (en) | Code converter | |
| GB1172844A (en) | Improvements in or relating to Calculating Machines | |
| JPS5779573A (en) | Small-sized electronic information equipment | |
| ES361727A1 (en) | A programmed apparatus for the serial handling of numerical information | |
| Potton et al. | Binary Arithmetic Operations | |
| GB1428211A (en) | Numerical data input apparatus | |
| JPS56114043A (en) | Code converting circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| NUG | Patent has lapsed |
Ref document number: 7903354-4 Effective date: 19911108 Format of ref document f/p: F |