FR2423821A1 - BINARY MULTIPLIER CIRCUIT INCLUDING A CODING CIRCUIT - Google Patents

BINARY MULTIPLIER CIRCUIT INCLUDING A CODING CIRCUIT

Info

Publication number
FR2423821A1
FR2423821A1 FR7909666A FR7909666A FR2423821A1 FR 2423821 A1 FR2423821 A1 FR 2423821A1 FR 7909666 A FR7909666 A FR 7909666A FR 7909666 A FR7909666 A FR 7909666A FR 2423821 A1 FR2423821 A1 FR 2423821A1
Authority
FR
France
Prior art keywords
product
bit
encoded
circuit
linear
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7909666A
Other languages
French (fr)
Other versions
FR2423821B1 (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nortel Networks Ltd
Original Assignee
Northern Telecom Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Northern Telecom Ltd filed Critical Northern Telecom Ltd
Publication of FR2423821A1 publication Critical patent/FR2423821A1/en
Application granted granted Critical
Publication of FR2423821B1 publication Critical patent/FR2423821B1/fr
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/49—Computations with a radix, other than binary, 8, 16 or decimal, e.g. ternary, negative or imaginary radices, mixed radix non-linear PCM
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
    • H03M7/50—Conversion to or from non-linear codes, e.g. companding

Abstract

La présente invention prévoit un circuit multiplicateur binaire où le produit est exprimé sous forme codée dès obtention du traduit linéaire (ou non codé). Lorsqu'un nombre binaire à 12 bits est multiplié par un autre nombre binaire à 12 bits, un nombre binaire à 24 bits est obtenu. Le produit à 24 bits peut être codé sous forme d'un nombre binaire à 7 bits sans signe (code mu 255) de la façon suivante. Le nombre 33 x 2**11 en binaire est ajouté au produit linéaire de façon à former un produit augmenté. Le nombre de premiers zeros dans le produit augmenté est compté et le complément base-moins-un du comptage est utilisé pour les trois positions de bits les plus significatives du produit codé. Les quatre bits les plus significatifs suivants du produit augmenté, après le niveau logique 1 le plus significatif, sont utilisés pour les quatre positions de bits les moins significatives du produit codé. Un circuit est décrit qui permet ce processus de codage, alors que le produit linéaire est en cours de formation, et donne le résultat codé lorsque le produit linéaire final est terminé. Application aux circuits multiplicateurs.The present invention provides a binary multiplier circuit where the product is expressed in coded form as soon as the linear translation (or not coded) is obtained. When a 12-bit binary number is multiplied by another 12-bit binary number, a 24-bit binary number is obtained. The 24-bit product can be encoded as an unsigned 7-bit binary number (mu code 255) as follows. The number 33 x 2 ** 11 in binary is added to the linear product so as to form an augmented product. The number of first zeros in the augmented product is counted and the base-minus-one complement of the count is used for the three most significant bit positions of the encoded product. The next four most significant bits of the augmented product, after the most significant logic level 1, are used for the four least significant bit positions of the encoded product. A circuit is described which enables this encoding process while the linear product is being formed, and gives the encoded result when the final linear product is completed. Application to multiplier circuits.

FR7909666A 1978-04-18 1979-04-17 BINARY MULTIPLIER CIRCUIT INCLUDING A CODING CIRCUIT Granted FR2423821A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CA301,370A CA1089569A (en) 1978-04-18 1978-04-18 Binary multiplier circuit including coding circuit

Publications (2)

Publication Number Publication Date
FR2423821A1 true FR2423821A1 (en) 1979-11-16
FR2423821B1 FR2423821B1 (en) 1984-11-02

Family

ID=4111272

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7909666A Granted FR2423821A1 (en) 1978-04-18 1979-04-17 BINARY MULTIPLIER CIRCUIT INCLUDING A CODING CIRCUIT

Country Status (5)

Country Link
JP (1) JPS583252B2 (en)
CA (1) CA1089569A (en)
FR (1) FR2423821A1 (en)
GB (1) GB2020068B (en)
SE (1) SE440562B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0452064U (en) * 1990-09-10 1992-05-01

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1086043A (en) * 1953-07-02 1955-02-09 Electronique & Automatisme Sa Improvements to multipliers for digital electric calculators
US4031378A (en) * 1974-06-28 1977-06-21 Jeumont-Schneider Method and apparatus for fast multiplication including conversion of operand format
FR2393479A1 (en) * 1977-06-02 1978-12-29 Post Office CODE CONVERTER FOR MIC SIGNALS

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1086043A (en) * 1953-07-02 1955-02-09 Electronique & Automatisme Sa Improvements to multipliers for digital electric calculators
US4031378A (en) * 1974-06-28 1977-06-21 Jeumont-Schneider Method and apparatus for fast multiplication including conversion of operand format
FR2393479A1 (en) * 1977-06-02 1978-12-29 Post Office CODE CONVERTER FOR MIC SIGNALS

Also Published As

Publication number Publication date
FR2423821B1 (en) 1984-11-02
JPS583252B2 (en) 1983-01-20
CA1089569A (en) 1980-11-11
JPS54140434A (en) 1979-10-31
GB2020068A (en) 1979-11-07
SE7903354L (en) 1979-10-19
SE440562B (en) 1985-08-05
GB2020068B (en) 1982-09-02

Similar Documents

Publication Publication Date Title
JPS57195308A (en) Block coding method
EP0177950A3 (en) A digital information signal encoding method
JPS57164662A (en) Compression system for multilevel signal
EP0725486A3 (en) Transmission code having local parity
EP0128457A3 (en) Coding method for an electronic key
ATE11620T1 (en) METHOD FOR PARALLEL SERIES IMPLEMENTATION OF A DIGITAL PARALLEL SEQUENCE.
FR2423821A1 (en) BINARY MULTIPLIER CIRCUIT INCLUDING A CODING CIRCUIT
KR0148151B1 (en) Variable length coding method and apparatus of differential motion vector value using improvement differential motion coding table
JPS59183542A (en) Adaptive type vector quantization device
JPS5216997A (en) Processing method of multi-superconductor
DE19518204A1 (en) Multilevel trellis coding system using binary convolutional code
JPS6471228A (en) Method of improving resolution of digital signal
JPS5580939A (en) Digital signal transmission method
WO1995027284A1 (en) Method of converting a sequence of m-bit information words to a modulated signal, method of producing a record carrier, coding device, decoding device, recording device, reading device, signal, as well as a record carrier
JPS6049328B2 (en) Decimal quadruple generation circuit
ATE125404T1 (en) METHOD FOR TREATING PARITY MONITORABLE BINARY CODE WORDS WHICH EXPERIENCE DIGITAL ATTENUATION AND/OR CODE CONVERSION DURING THEIR TRANSMISSION.
JPS5483411A (en) Binary data coding system
JPS57168539A (en) Coding system
Owen Admiralty Practice in the 19th Century-A Little Family Party-An Historical Footnote to Professor Tetley's Article
EP0106644A3 (en) Improvements in or relating to data processing
JPS54120515A (en) Coding system
JPH0191587A (en) Prediction code vector quantizing system
JPS524505A (en) Lubricating oil composition
JPS57174983A (en) Picture synthesizer
JPS5550777A (en) Information compression device

Legal Events

Date Code Title Description
ST Notification of lapse