SE440562B - MULTIPLICATOR CIRCUIT FOR MULTIPLICATING A FIRST BINER NUMBER WITHOUT SIGN WITH ANOTHER BINERIC NUMBER WITHOUT SIGN AND CREATING A CODED BINER PRODUCT WITHOUT SIGN - Google Patents

Description

79033544; the resulting linear product to include 24 binary bits. This 24-bit linear product must then be transformed to the seven-bit encoded PCH format.

According to known technology, circuits are used that multiply two linear digital words and generate a linear digital product. U.S. Patent 4,027,147 discloses an example of such a circuit. The prior art also includes circuits that expand or compress or otherwise modify a digital word. U.S. Patent 3,594,560 discloses such a circuit for expanding a digital word. U.S. Patent 4,071,774 discloses a scale conversion circuit for a digital word. U.S. Patent 4,069,478 relates to a binary / binary coded decimal converter.

A problem with such devices when used in tandem, i.e. a multiplier circuit followed by a coding circuit, is that precious time is lost in performing the two calculations consecutively, first the multiplication is performed and then when the multiplication is completed the digital number is coded. To save time when performing the calculations, it is desirable to perform the multiplication and coding simultaneously.

According to the present invention there is provided a multiplier / coding circuit in which the coded binary product is available at the output immediately after the multiplication has been performed.

In more detail, the present invention includes a 25 bit shift register for storing a first 12 bit binary number (without sign) and a 12 bit shift register for storing a second 12 bit binary number (without sign). The output of each shift register is applied to an input of an AND gate with two inputs, which performs the actual multiplication. A first clock controls the shift in the first shift register. The first shift register has its output fed back to its input, so that after 25 pulses from the first clock, the first register is again in its initial position. The second shift register v9o3ss4Fa ret is controlled by a second clock, which has a pulse rate corresponding to l / 24 of the pulse rate of the first clock.

The output signal from the AND gate is applied to an accumulator, which comprises a 24-bit shift register. The accumulator sums the sub-products from the multiplication process (obtained from the AND gate) and stores the resulting sum in its 24-bit shift register. At the start of the process, the 24-bit shift register is initially set to 33-211 in, for example, O00000Ol0000lO000000O000. A three-bit binary counter counts the number of logic zeros input to the when form, the 24-bit shift register, whereby the counter is reset to 0 at the occurrence of each logic 1 input to the shift register. When the most significant logic 1 in the final linear binary product is at the input of the 24-bit shift register, the counter is reset to 0 for the last time. Consequently, the final value in the counter corresponds to the number of leading zeros in the linear product without signs. The binary value is then inverted (bit by bit) and the result is the three most significant bits in the coded product (without sign).

In addition, a four-bit temporary memory is connected to the four most significant bit positions in the 24-bit register. When each logic 1 occurs at the input to the shift register, the contents of the four most significant bit positions in the shift register are loaded into the four-bit temporary memory. When the most significant logic 1 in the final linear binary product is located at the input of the 24-bit shift register, the four-bit temporary memory is loaded for the last time. The four logical bits stored in the temporary memory become the four least significant bits in the encoded product.

The coded product is now in parallel form and a character bit (obtained in a manner known per se) can be inserted before the least significant bit in the coded product.

In other words, the present invention relates to a circuit for transforming an n + m bit binary without a sign into a 7-bit binary number 7903354-læ I without a sign, wherein n, m and q are positive integers with n + m 2213 and q ¿_n + m, which circuit comprises: means for adding a constant number in binary form to said number with n + n1 bits thereby generating an amplified binary number, means for counting the number of conductive zeros in the amplified binary number and for forming the radix-minus-one-complement of the count value, which complement forms the qp most significant bits of the q-bit coded binary number, where p is a positive integer and so chosen that 04.p <¿q and means for extracting the p least significant logical bits immediately adjacent to the most significant logical 1 from the amplified number and utilizing these as the least significant bits in the encoded product. In one embodiment, n + m = 24, q = 7, p = 4 and the constant number is:. (q "p) (zxzpJrnxzßn fl n) (2 + p_ + 1 fl Expressed in yet another manner, the present invention relates to a multiplier circuit for multiplying a first binary number without a sign by a maximum of n b. Other bits with a second binary number without signs with maximum m binary bits and generating an encoded binary product without signs with maximum q binary bits, n, m and q all being positive integers with n + m> _q, which multicilator circuit comprises: an accumulator means comprising a shift register with n + m bit positions for storing both the sub-products and the final uncoded product of the first and second binary numbers, which register is preset to an initial binary Cage, a qp bit binary counter connected to increase its count value by one for each logic 0 input to the register, which counter is reset to 0 at the occurrence of each logic l at the input to the register, where p is a positive integer and so selected that 0 <.p¿_q, and a temporary memory circuit connected to receive the bits stored in the p most significant bit positions in the register, which temporary memory is receptive for the input signal to the register to charge the bits from the register in the memory circuit at each occurrence vsoázšl-4 of a logic l at the input to the register, the most significant bits of the coded product being the radix-minus-one complement to the final count value stored in the counter and the least significant bits of the coded product being the final binary number stored in the temporary memory. an embodiment is n = l2, m = l2, q = 7 and p = 4 and said initial binary value is 0000000l000Ol0OOO0000000.

A preferred embodiment of the invention will now be described in more detail with reference to the accompanying drawings.

Fig. 1 is a simplified block diagram of a multiplier and coding circuit according to the invention.

Pig. 2 is a graphical representation of the manipulations performed on the uncoded product to obtain the coded product.

The interconnection of the various components is shown in Figure 1, to which reference is now made. The shift register 10 contains 25 bit positions and will consequently be referred to as a 25-bit shift register. In the embodiment shown in Figure 1, the binary number J to be stored in the shift register 10 contains a maximum of 12 bits and when the shift register is initialized, these 12 bits are located on the right side of the register 10, i.e. in its 12 least significant bit positions. The remaining bit positions, i.e. the l3 most significant positions, are all 0.

Since the output (at the right or least significant bit position) of register 10 is fed back to the input (at the left or most significant bit position) of register 10, at each clock pulse it changes from clock A (clock frequency 2.56 MHz) the most significant bit of the information in register 10 to the most significant bit position and all other bits are shifted one bit position to the right (ie each bit is shifted to a bit position which is one bit less significant than its previous position). this procedure is repeated at each pulse from 79033544 * clock A, whereby consequently after 25 clock pulses the register 10 is again in its initial position. In addition to being fed back to the input of register 10, its output is also connected to an input of an AND gate 11.

A shift register l2 consists of a 12-bit binary shift register and contains a binary number K with a maximum of l2 bits. The output of register 12 is connected to an input of AND gate 11 as shown. A clock B provides a clock pulse to the register 12 at a rate of one pulse for each 24 pulses from the clock A. Each time the clock B emits a pulse, the bits in register 12 are shifted to a bit position which is a bit less significant than their previous position, i.e. a bit position to the right.

It should be noted that the numbers J and K are without signs, the sign for multiplication being determined by conventional methods and consequently will not be described here.

AND gate ll acts as a multiplier in the circuit shown. If both inputs to the AND gate l1 receive logic l, the output signal from the AND gate ll is a logic l. For all other input states, the output signal is a logic O. This effect is well known.

Since the clock A pulsates at a speed which is 24 times faster than that of the clock B, the least significant bit in the number K Y stored in register l2) is successively multiplied by the bits stored in the least significant bit position in register 10, which are of course the successive the logical bits that make up the number 5 starting with the least significant and running toward the most significant bit and then followed by 12 logical zeros. When the clock A generates its 24th pulse, the clock B produces its first pulse, ie the clock B actually counts the pulses generated by the clock A and when the counter reaches 24 it outputs a logic 1 and resets to 0 to start counting again. The pulse from the clock B causes each bit stored in the register 12 to shift one position to the right, ie to a bit less significant bit position. veeassß-4 The purpose of this is to cause the next least significant bit in the number K (which is now stored in the right bit position in register 12) to be successively multiplied (via AND gate ll) by a logic 0, then by the bits in the number J starting with the least significant bit and running towards the most significant bit and followed by a series of logical zeros. It should be noted that after 25 pulses from clock A, register 10 has completed a complete cycle and is back in its initial position, but after only 24 pulses from clock A, register 10 has not fully completed a complete cycle and the effect is that all bits in the register l0 is a bit position to the left of their original starting position, i.e. a significant bit higher. It will thus be appreciated that the purpose of introducing the 13 extra logical 0-bits (in addition to the 12 bits required for the number J) is to effect this shift regarding bit position in the number J. The theory behind this shift is the basis of the theory of multiplication and will not be described in more detail.

As stated earlier, the output of the AND gate 11 is the product of the logic bits at its input. Consequently, the output of AND gate ll consists of a sequence of binary digits. The output signal from the AND gate is applied to an input 16 of a one-bit adder 13. The sum output 14 of the adder 13 is connected to an input 17 (most significant bit) of a 24-bit shift register 15. The output 22 from the shift register 15 is connected to another input. 18 of the adder 13. The transfer output 19 of the adder 13 is connected to a transfer input 20 of the adder 13 via a flip-flop 21. The clock A is switched on to control the function of the shift register 15. At each clock pulse from the clock A, the register 15 adds a sub-product to its contents received from the one-bit adder 13. At the end of 288 clock pulses from the clock A, the register 15 contains the 24-bit product of the binary number J without a sign multiplied by the binary number K without a sign, 790335441. the most significant bit being located to the left in register 15 and the least significant bit to the right of register 15. It should be noted that when register 15 is initialized to begin its part of the product formation of two numbers, it is not set to 0 but instead the register 15 starts at the value 33-211 stored in binary form, ie 0000000l0000100000O0000O. The significance of this will be described later. It should also be noted that the adder 13, the flip-flop 21 and the register 15 together form an accumulator 38.

A three-bit binary counter 23 has its reset input 24 connected to the output 14 of the adder 13.

The counter 23 operates to count the clock pulses applied to its clock input 25 from the clock A. Each time a logic 1 pulse is received at a reset input 24, the counter 23 is reset to 0 and begins counting again.

The end result of this is that after 288 pulses from the clock A, the linear product of J and K is stored in the register 15 and the three-bit binary counter 23 contains a value corresponding to the number of zeros to the left of the most significant logic 1 stored in the register 15. ie the leading zeros in the product. The charging input 28 of a four-bit temporary memory 26 is also connected to the output 14 of the adder 13.

The memory 26 has its four inputs 27a, 27b, 27c and 27d connected to the four most significant bit positions in the register 15, as shown in Figure 1. When a logic 1 appears at the sum output 14 of the adder 13 and consequently at the charge input 28 of the memory 26, the information in the four most significant bit positions in the register 15 is loaded in the memory 26. This charging (and the following discharges) can take place many times during the multiplication process until the last logic 1 to be shifted to the register 15 appears at the sum output 14 of the adder. 13 and memory 26 are loaded for the last time. This last logic 1 will be the most significant logic 1 in the final result stored in register 15. At this time, the memory 26 contains the four bits immediately to the right of the most significant logic in the final, non-coded product stored in register 15, i.e. the four least significant logical bits immediately adjacent to the most significant logical one in the final, non-coded product.

To sum up so far, the leading zeros in the final non-coded product (ie the number of consecutive zeros in the most significant bit positions in register 15) have been counted and the resulting value stored in the three bit counter 23. The most significant logical The final uncoded product is used both to reset the counter 23 to 0 for the last time and to load the memory 26 for the last time.

The four least significant logical bits immediately adjacent to the most significant logical 1 are stored in memory 26.

Outputs 29, 30, 31 from the counter 23 are connected to inputs of the inverters 32, 33 and 34, respectively. It should be noted that the use of the counter 23 and the inverters 32, 33 and 34 is equivalent to the use of a counter, which is well known in the art. It should also be noted that the inverters 32, 33 and 34 provide the radix-minus-one complement of the value stored in the counter 23. The outputs of the inverters 32, 33 and 34 are connected to an 8-bit parallel-series shift register 35. Outputs 36a, 36b, 36c and 36d from the memory 26 are also connected to the shift register 35.

A character bit 37 is applied to the shift register 35 to the left of the bit from the inverter 32. The format of the resulting compressed (according to / 4255 PCM) PCM signal is as follows (starting with the most significant bit and running towards the least significant bit) : character bit, bit from inverter 32, bit from inverter 33, bit from inverter 34, bit from output 36a, bit from output 36b, bit from output 36c, and bit from output 36d.

The foregoing description has referred to a preferred embodiment of the invention for a particular application. Below now follows a brief description of the theory 790335114! 10 which forms the basis for the operation of the circuit according to Figure 1.

Beginning with a 24-bit linear (ie, non-coded) binary number Z without being converted, it will be converted to a 7-bit PCM code without a sign, the binary number Z can be described as: where; Y = a 24-bit binary number without a sign; Y1 = the 13 most significant bits of the number Y (integer, range from 0 to 8158); and YF = the ll least significant bits of the number Y (fraction, range from 0 to g§1_) 2048 In short, with the division of Z by the factor 211 (ie 2048) a binary point has been introduced to the right of the l3th most significant bit in the number Z.

C is now assumed to denote the corresponding PCM codeword without a sign so that: c = 16 L + v = 24. L + v, _ where L is the three-bit segment value and V is the four-bit step value.

The next step is to compare the number Y with all possible threshold values X, where X is defined as follows: x = zL (2v + 32) - 33 So that xnéy <Xn + l This is achieved according to the following procedure: Both the number Y and the threshold values X are amplified by 33 Y '= Y + 33 YF As above, Y = Yl +' YF 2048., Y '= Yl + 33 + 2048 X' = X + 33 790335h ~ 4 ll L (zv + 32) -33 L As above, X = 2 .Z x '= 2L (2v + 32) - 33 + 33 = 2 The modified number (ie Y') is then expressed as- (2V + 32) as a floating point number, (note that Y Y 'is within the range from 33 to 81l + 2047) 2048 Y' = 2L + Y "(expressed as a floating point number with Y" in the range 33 to 63 + 218-1 zla and L in the range 0-7.

This is equivalent to shifting the number stored in register 15 to the left, with 7-L positions, to eliminate the leading zeros and place the imaginary binary comma after what is now the sixth bit. This gives the segment bits L. then divide both Y 'the x' by 2L to obtain: Y 'L Y "- = 2 x 2L 2L 0.0 Y" = å; 2L I Let X "= 'Xi-T- 2 L Consequently §l ~ = 3-133-i-33) = x" LL 2 2, C x "= zv + 32 By doing Y" = X "we can obtain the step bits V: Y "= V + 32 + X" 2V = Y "-32 v = (Y" - 32) 2 Subtracting 32 from Y "has the effect of eliminating the most significant bit and division by 2 has effect of shifting the imaginary binary comma a position to the left. If the number V is abbreviated (ie, eliminate the bits to the right of the imaginary binary comma), the remaining four bits constitute the step bits V in the PCM code.

Figure 2 is a graphical representation of the theoretical manipulations performed regarding the final uncoded product stored in register 15. It should be noted that these manipulations do not occur in an actual case but are only shown here to facilitate understanding of the theory. behind the various steps previously described in connection with Figure 1, which appear in practice.

Figure 2A shows a representation of the register l5 after multiplication as an example has been carried out.

Figure 2B shows the insertion of an imaginary binary comma after the thirteen most significant bits. The parts YI and ¥ F of the number Y are shown, whereby YI consists of the 13 most significant bits and YF consists of the ll least significant bits.

Figure 2C is a representation of the number 33 (in binary form) and shows how this is added (in a suitable position) to the number Y in Figure 2B.

Figure 2D is the result of the addition of the two binary numbers Y and 33 given in Figures 2B and 2C, respectively.

Figure 2E is a representation of the contents of the counter 23, see Figure 1, after the complete multiplication.

The counter 23 contains the value of the number of leading zeros in the linear product (four in this example).

Figure 2F is a representation of the inversion of each bit from the counter 23 performed by the inverters 32, 33 and 34 of Figure 1.

Figure 2G indicates the binary number (from Figure 2D) shifted far enough to the left so that there are no longer any leading zeros (the leading zeros have been shifted to the least significant bit positions).

Figure 2G shows how the most significant logic 1 is rejected and how the next four bits become the four bit step value V and how the remaining bits are rejected. '79 Û335lv fi 13 Figure 2H shows how the segment value L, the step value V and the character bit are combined to form the coded product C with characters.

If one considers in more general terms an encoded binary number, encoded according to a / 4 ~ law code, consisting of a total of q bits (excluding the character bit), this encoded number of q bits can be stated to have q - p segment bits (L) and p step bits (V).

For the characterless / U255 code previously discussed, q = 7, p = 4 and q - p = 3 are noted. The decision levels X lower for the / H code (or fl-law) are defined as follows: x lower = 2 (2L (v + 29) - 29) -l = 2L (zv + 2x2p> -2x2P-1 where Xnedre is the lower limit of the level in question; p is the number of step bits in the coded binary number; L is the integer (value) expressed by the qp -segment- bits in the code; and V is the integer (ie the value) expressed by the p step bits in the code; and q is the total number of bits in the encoded number without a sign.

The offset for such an encoded binary number is thus 2x2p + 1, which is 33 for a normal (7-bit ßÅ255 PCM number (with p = 4) .This is the number added to the shift register l5 (Figure 1) in the appropriate position before the multiplication, (see also Figure 2C).

The linearized code for this general PCM / J koa contains p + z (q "p) + 1 bits, which becomes 13 (ie 4 + 23 + 1) for the normal seven-bit, M255 PCM number. (in determining the appropriate position for the displacement) must be entered in the final linear product according to the number of bits (calculated from the most significant bit, see Figure 2B) Consequently, the number that must be added to the linear product (stored in register l5, figure l) to code this: 7903354-4 14 (zxzP + l) xzf (n + m) "(2 (q_p) + P + 1Ü In the general case, in binary multiplication (ie JJXKK) the binary number JJ without sign p + 2 (q_p) + l bits (ie 4 + 23 + l = 13 bits for / 4255 code) The binary number KK without sign can also have the same number of bits as the number JJ. Depending on the application, the number of bits in the numbers JJ and KK vary and the number of bits in JJ need not be the same as the number of bits in the number KK.

Figures 1 and 2 show a circuit for use with a digital tone generator. In this context, 12 bits were used for each number J and K (Figure 1), since these numbers were not originally obtained from PCM and 12 bits were more suitable for the hardware then available.

Another coding law that is sometimes used is the A-law.

In contrast to the I / O law, the A law is not a regular code. The first segment in the A-law (closest to 0) is described by a different equation than the other segments. Consequently, there is no shift in connection with A-law, so that the final linear product is amplified by the value 0. This means that there is a possibility that the capacity of the three-bit counter used in Figure 1 is exceeded. The 0-segment in the A-code also requires a special output (namely the 8th to 11th most significant bits of the linear product). If the exceedance of the three-bit counter is neglected and if the zero segment in the A-law is neglected, the circuit according to Figure 1 will be applicable to the A-law. Minor modifications (not specified herein) may be made in the circuit of Figure 1 to account for exceeding the capacity of the counter and the 0-segment of the A-code.

Claims (8)

Claim 7903354144 1. l. Multiplier circuit for multiplying a first binary number (J) outside characters with a maximum of n bi- near bits with a second binary number (K) without signs with a maximum of m binary bits and generating an encoded binary product without signs with maximum q binary bits, wherein n, m and q are all positive integers, wherein n + nx 7 q, characterized in that it comprises accumulator means (38) comprising a shift register (15) with n + m bit positions for storing both the partial products and the final, non-coded product of said first (J) and second (K) binary numbers, which register (15) is preset to an initial binary value, a qp bit binary counter (23) connected to increase its count value by 1 for each logic 0 input to said register (15), which counter (23) is reset to 0 at the occurrence of each logic 1 at the input (17) of said register (15), p is a positive integer and so chosen that 0 <, p 4 q, and a tempo memory circuit (26) is connected to receive the bits stored in the p most significant bit positions in said register (15), which memory circuit (26) is receptive to the input signal to said register (15) for storing the bits from said register (15) in said memory circuit (26) at each occurrence of a logic l at the input (17) of said register (l5), the most significant bits in said coded product constituting the radix-minus-one complement of the final value stored in said counter (23) and the least significant bits in said coded product constitute the final binary number stored in said memory circuit (26). Circuit according to claim 1, characterized in that said initial binary value to which said register (15) is preset is: (2x2P + 1) x2 [(11 + m) - URI-p) + P + 117 79033544 ! 16 Circuit according to Claim 1 or 2, characterized by avaü n = lL m = lL q = 7od1p = 4. Circuit according to Claim 1 or 2, characterized by avattn = l3, m = l3, q = 7 and p = 4. A circuit according to claim 1, characterized in that said initial binary value of said register (15) is 000O000l0000l000O0000O00 in notation with base two, where n = 12, nx = 12, q = 7 and p = 4. A circuit according to claim 1 for multiplying a first binary number (J) by n bits without a sign by a second binary number (K) by m bits without a sign and storing both the intermediate and final results in an accumulator means (38). comprising a shift register (15) with n + m bit positions and a coding circuit for transforming the final linear product into a coded product with q bits without signs, wherein n, m and q are all positive integers with n + m> characterized in that it comprises means for adding a constant binary value to the contents of said shift register (15), a qp bit binary counter (23) for counting the number of conductive zeros in said final linear product. , where p is a positive integer and so selected that p <: q, inverter means (32, 33, 34) for inverting the count value stored in said counter (27) on a bit-by-bit basis to thereby produce radhc-minus -a complement to the count value, as well as a p bits s temporary memory circuit (26) for receiving the p least significant bits in said final linear product immediately adjacent to the most significant logic 1, the most significant bits in said coded product constituting the output of said inverter means (32, 33, 34) and the least significant bits in said coded product constitute the output signal (36a, 36b, 36c, 36d) from said p bit temporary memory circuit (26). Circuit according to Claim 6, characterized in that the constant binary value is: (q_p) (zxzP + 1) x2f - (“+ m) '(2 * P + IÜ': fun 790335ls ~ 4 17 Circuit according to Claim 6 or 7, characterized in that n = 13, m = 13, q = 7 and p = 4.