SE506636C2 - Receiver for use with multicarrier transmission system using orthogonal carriers - Google Patents

Abstract

The receiver includes a first feedback loop for aligning the receiver's frame timing by using a frame timing deviation signal to control an oscillator producing the receiver sampling clock. A second feedback loop compensates for channel effects by using a signal. This signal is representative of an argument estimate of the pilot carrier to control the oscillator which is VCXO. The transmission system is a DMT based VDSL system. The receiver includes a correlator connected to a peak position estimator to produce the frame timing deviation signal.

Description

506 636 the use of asymmetric solutions in which high data rates are transmitted only in one direction. Such solutions meet many of the requirements of high bandwidth services, such as video-on-demand, but in the long run symmetrical duplex systems will be required.

VDSL technology is very similar to ADSL, although ADSL has to provide much greater dynamic ranges and as a result is much more complex. VDSL is lower in cost and lower in energy (lower in power), and VDSL units in real estate (premises) need to implement an access control for media in the physical layer for multiplexing upstream data.

U Four line codes have been proposed for VDSL: CAP; "Carrierless" AM / PM, a version of QAM with suppressed carrier, for passive NT configurations, CAP would use QPSK upstream and a type of TDMA for multiplexing (although CAP does not exclude a solution with FDM for upstream multiplexing ); DMT; Discrete Multi-Tone, a multi-carrier system that uses Discrete Fourier Transforms to create and demodulate individual carriers, for passive NT configurations; DMT would use FDM for upstream multiplexing (although DMT does not rule out a TDMA multiplexing strategy); DWMT; Discrete Wavelet Multi-Tone, a multi-carrier system that uses "Wawelet transforms" to create and demodulate individual carriers; 10 25 30 35 506 636 DWMT also uses FDM for upstream multiplexing, but also allows TDMA ; and - SLC; Simple Line Code, a four-level baseband signaling that filters the baseband and resets it at the receiver, for passive NT configurations; it is most likely that SLC will use TDMA for upstream multiplexing, though FDM is possible.

Early versions of VDSL will use frequency division multiplexing to separate downstream from upstream channels, and both of these from POTS and ISDN. Echo quenching may be required for later generations of systems with symmetric data rates. A fairly large distance, in frequency, will be maintained between the lowest data channel and POTS to enable very simple and cost-effective POTS line splitters. Normal use would place the downstream duct above the upstream duct. However, the DAVIC specification reverses this scheme to enable the distribution of VDSL signals over coaxial cable systems in buildings.

In a multi-carrier transmission system, such as a DMT system, a receiver must be able to recover a sampling clock that is very precisely synchronized to a transmitter sampling clock. One known method of achieving synchronization uses a reserved carrier, which is transmitted with a fixed phase. (phase-locked) to the pilot carrier, The receiver sampling clock is then locked in the phase pilot carrier. Frame synchronization must also be restored.

This can be achieved using a correlation technique. An object of the present invention is to provide in a multi-carrier transmission system an improved method of retrieving a sampling clock and phase-locking the sampling clock to a pilot carrier, thereby synchronizing a receiver sampling clock with a transmitter sampling clock.

Another object of the present invention is to provide a multi-carrier transmission system in which a pilot carrier is transmitted, incorporating an improved technique for phase locking a sampling clock, in a receiver, to said pilot carrier, thereby synchronizing said receiver sampling clock with a transmitter sampling clock.

A further object of the present invention is to provide a receiver which may form part of a transceiver, for use in a multicarrier transmission system, wherein said receiver and / or transceiver uses an improved technique for phase locking a sampling clock, in said receiver, to a pilot carrier, thereby synchronizing said receiver sampling clock with a transmitter sampling clock.

According to a first aspect of the present invention, there is provided a receiver for use in a multi-carrier transmission system using orthogonal carriers, in which a receiver sampling clock is synchronized with a transmitter sampling clock by phasing said receiver sampling clock to a pilot carrier. aligning the frame synchronization of said receiver by using a frame synchronization deviation signal to control an oscillator device adapted to produce said receiver sampling clock; and - a second feedback loop arranged to compensate for channel effects by using a signal representing an argument value calculation of said pilot carrier to control said oscillator device.

Said oscillator device may be a VCXO.

Said multi-carrier transmission system may be a DMT transmission system.

Said multi-carrier transmission system may be a DMT-based VDSL system.

Said receiver may include a correlation device connected to a peak position estimator means arranged to produce said frame synchronization deviation signal.

Said receiver may include means for pilot means for producing said signal representing said argument value calculation (argument estimation) pilot argument value calculation.

Said top position value calculation device and said pilot argument value calculation device can each be connected to a feedback control device which can be connected, via a D / A, to said oscillator device.

Said field switch control device may comprise two feedback control devices whose output data is added to produce a control signal for said oscillator device. 506 636 Said signal representing said pilot argument value calculation can act as a smoothing parameter and cause said oscillator device to be adjusted in a manner that compensates for channel effects.

Said receiver can operate according to a synchronization process which has the following components: - frame alignment by adjusting said oscillator device in response to a frame synchronization deviation signal; equalization by adjusting said oscillator device in response to said signal representing said pilot carrier argument; and - only after an "establishment period" has ended, adjusting said oscillator device in response (said settling down period) to said signal representing said pilot carrier argument value calculation.

Said signal representing said pilot carrier argument value calculation can be used to smooth time variations in channel characteristics of a channel over which said pilot carrier is transmitted. monitoring device may be provided for monitoring frame synchronization deviations and for initiating resynchronization, if said frame synchronization deviations exceed a large predetermined value.

According to a second aspect of the present invention: there is provided a transceiver, including a transmitter and a receiver, characterized in that said receiver is a receiver as described in the preceding paragraphs.

According to a third aspect of the present invention, there is provided a multi-carrier transmission system using orthogonal carriers, in which a receiver sampling clock is phased to a pilot carrier, characterized in that said multi-carrier transmission system includes two transceivers as set forth in the preceding paragraph.

According to a fourth aspect of the present invention, in a multi-carrier transmission system in which a transmitter and a receiver are synchronized by means of a pilot carrier transmitted by said transmitter to said receiver, a method of recovering at said receiver, said transmitter, is provided. sampling clock from said pilot signal and synchronizing said transmitter with said receiver, characterized by the steps of: - receiving signal; (derive) a frame synchronization deviation - use said frame synchronization deviation signal to align a received frame structure to a transmitted frame structure; and - deriving an estimate of said pilot carrier argument and using it as an equalization parameter to compensate for channel influence.

According to a fifth aspect of the present invention, there is provided, in a multi-carrier transmission system using orthogonal carriers, in which a receiver sampling clock is synchronized with a transmitter sampling clock by phase locking said receiver sampling clock to a transmitter carrier. synchronizing the sampling clock of said receiver to the sampling clock of said transmitter, characterized by the steps of: - aligning the frame synchronization of said receiver by using a frame synchronization deviation signal to control said sampling clock of said receiver; and - compensating for channel effects by using a signal representing an argument value calculation of said pilot carrier to control said receiver's sampling clock.

Said frame synchronization deviation signal can be obtained, by correlation, from a stream of received data in the time domain.

Said frame synchronization deviation signal may be added to said signal representing an argument value calculation of said pilot carrier to produce a receiver sampling clock control signal. Said signal representing pilot argument value calculation may act as an equalization parameter and may cause adjustments to be made.

Said method may include the following components: frame alignment, between said receiver and said transmitter, by adjusting the sampling clock of said receiver in response to a frame synchronization deviation signal; smoothing a channel over which said pilot signal is transmitted by adjusting said transmitter's sampling clock in response to said signal representing said pilot carrier argument; and - only after an "establishment down period" (se: tling down period) has ended, adjusting said sampler clock in response to said signal representing said pilot carrier argument.

Said signal representing said value calculation of pilot carrier argument can be used to compensate for time variations in channel characteristics in a channel over which said pilot carrier is transmitted.

Said frame synchronization deviations can be monitored and resynchronization is initiated if said frame synchronization deviations exceed a large predetermined value.

Embodiments of the invention will now be described, by way of example, with reference to the accompanying figures, in which: Figure 1 shows, in schematic form, an asymmetric communication system.

Figure 2 shows, in schematic form, a DMT system. 506 U: 20 636 10 Figure 3 shows, graphically, the channel separations used in an asymmetric DMT transmission system.

Figure 4 shows, in schematic form, the cornerstones of a multitone carrier system modem contemplated in the present invention.

Figure 5 shows, in schematic form, a partitioning of the multitone carrier modem shown in Figure 4, which is used to facilitate implementation.

Figure 6 shows, in graphical form, spectral allocation for copper pairs.

Figure 7 shows, in schematic form, the frame structure used in the multitone carrier system described here.

Figure 8 shows, in schematic form, the analog interface of the multitone carrier system modem shown in Figure 4.

Figure 9 shows, in graphical form, the dependence on the signal-to-noise ratio (SNR-ratio) multitone carrier system described here. for frequency in that Figure 10 shows, in schematic form, the FFT algorithm used in the multitone carrier system modem shown in Figure 4.

Figure 11 shows, in schematic form, the frame correlation principle used in the multitone carrier modem shown in Figure 4.

Figure 12 shows, in schematic form, implementation of a correlator used in the multitone carrier system modem shown in Figure 4. 10 Ix) Un (U CD ON O \ (N Ch ll Figure 13 shows, in schematic form, the mean value generator (averager) ) used in the correlator in Figure 12.

Figure 14 shows, in schematic form, a correlation position detector used for the multitone carrier system modem shown in Figure 4.

Figure 15 shows, in schematic form, an overview of the synchronization unit used in the multitone carrier system modem shown in Figure 4.

Figure 16 shows, in schematic form, an overview of the FFT / IFFT unit used in the multitone carrier system modem shown in Figure 4.

Figure 17 shows, in schematic form, the use of a cyclic prefix.

Figure 18 shows, in schematic form, a “decision directed” channel value calculation and smoothing system for use in the multitone carrier system modem shown in Figure 4.

Figure 19 shows QAM coding for b = 6.

Figure 20 shows, in schematic form, the realization of the calculation of bit charge and energy charge factors used in the multitone carrier system modem shown in Figure 4.

Figure 21 shows, in schematic form, an overview of the system controller interface used in the multitozarway system modem shown in Figure 4.

Figure 22 shows, in schematic form, the manner in which two of the multitone carrier system modems shown in Figure 4 are interconnected to create a multitone carrier transmission system.

Figure 23 shows, in schematic form, the vector management system used in the multitone carrier system modem shown in Figure 4.

Figure 24 shows BSI length.

Figure 25 shows, in schematic form, NU SC load distribution for BSI interruptions for the multitone carrier system modem shown in Figure 4.

Figure 26 shows the SUS pattern of the multitone carrier modem shown in Figure 4.

Figure 27 shows the DAS pattern in schematic form, for the multitone carrier modem shown in Figure 4.

Figure 28 shows, in schematic form, "wake-up" signaling for the multitone carrier system modem shown in Figure 4.

Figures 29 to 31 show the set-up sequence of the multitone carrier system modem shown in Figure 4.

Figure 32 shows, in schematic form, a network overview of a network interface for a VDSL modem application.

To facilitate the understanding of the present invention, a list of abbreviations used in this patent application is presented below.

ADC: Analog-to-Digital Converter (A / D) AIS: “Alarm In Signal” 20 ASIC: BPSK: BSI: BSI-D: BSI-U: CCH: CM1: CM2: CM3 : CP: DAC: DAS: DF1: DF2: DF3: DMT: 506 636 13 Application Specific Integrated Circuit Binary Phase Shift Keying Base Synch Interval BSI for downlink connection BSI for downlink connection BSI for uplink connection Control channel Bärvàgstyp (mode) 1; bit-loaded and used carrier (Carrier mode 1, bit-loaded and used carrier) Carrier mode 2, masked or disabled carrier Carrier mode 2, carrier arranged 3 for zero bit-loading enabled (Carrier mode 3, zero bit-loading enabled Carrier) Cyclic Prefix Digital-to-Analog (D / A) converter (Digital-to-Analog converter) DF3 frame sequence (DF3 frame sequence) Data frame, random (random) data parallel CCH, (Data frame, random data parallel CCH) Data frame, random data one CCH (Data frame, random data one CCH) Data frame, fully bit loaded one CCH (Data frame, fully bit loaded one CCH) Discrete multiton ( Discrete Multi Tone) 506 636 10 30 DWMT: EMC: FEC: FEXT: FFT: FTTN: Gl MUSIC: G2 MUSIC: G3 MUSIC: IFFT: IIR: ISDN: ISI: JTAG: LEX: LP: NT: 14 Discrete Wavelet multiton ( Discrete Wavelet Multi-Tone Electro Magnetic Compatibility Forward Error Correction Far End Cross Talk "Fast Fourier Transform" Fiber To The Node First Generation, Prototype System (VME-Based) Three + Two, ASIC implementation (Three + two ASIC implementation) Two chips' silicon implementation (Two chips silicon implementation) Reverse "Fast Fourir" transformation (Inverse Fast Fourir Transformation) Infinite Impulse Response International standard for digital networks (International Standard for Digital Networks Inter-Symbol Interference Joint Test Action Group Local Pass Low Term Network Termination 20 OFDM: ONU: PGA: POTS: QAM: SC: SDH: SF: SNR: STB: SUS: SUS1: SUS2: TA: TDMA: UTP: VCXO: 506 636 15 Network Unit Orthogonal Frequency Division Multiplexing Optical Optical Unit Network Unit) Programmable for Progammable Gain Attenuator Conventional, Plain Old Telephony Service Quadrature Amplitude Modulation System Controller Synchronous Digital Hierarchy Synch Frame Sync Frame Signal-to-Interference Ratio -Noise Ratio) Set Top Box Synch Frame Sequence SF and DF1 Frame Sequence SF and DF2 Frame Sequence (SF and DF2 Frame Sequence) "Time Advance" Multiple Access with Time Division Multiple Access (Unshielded Twisted Pair) Voltage Controlled Crystal Oscillator 506 636 lS 20 25 30 16 VDSL: Very high bit-rate Digital Subscriber Lines The system to which the present invention relates is referred to for simplicity. as "MUSIC" (Multi-carrier System for the Installed Copper Network) installed copper network). MUSIC is intended to provide high-speed communication on copper pair cable for telephony to support broadband multimedia services. (pp. 9603189-3) and the patent specifications SE 9603187-7, SE 9603188-5, SE 9603190-1, SE 9603191-9, SE 9603192-7, SE 9603193-5, SE 9603194-3, SE 9603195- O, SE 9603196-8, SE 9603197-6 and SE 9603198-4, the MUSIC system described in this offers a cost-effective and robust customer implementation with silicon, which provides 26: 2 or 13: 2 Mbit / s asymmetric transmission over copper cable ( local telephone networks.

The MUSIC system can be accessed using the network concept known as Fiber To The Node (FTTN), which uses optical fiber, which each serves many users, to a switch cabinet near the users' homes. Thus, the cable length specification for MUSIC can be successfully limited to 1300 meters.

The MUSIC system is mainly intended for transmitting a high bit rate (26 Mbit / s) signal downstream to the subscriber, and a low bit rate signal (2 Mbit / s upstream, from the subscriber.

Figure 1 shows the MUSIC system. A network device, NOW, is connected to the fixed network through an optical fiber link, (FTTN). A network termination, NT, connected to a video-on-demand, is linked multimedia application, e.g.

UI 20 lx) UI 506 636 17 to the NOW via copper cable. The MUSIC system supports a high data rate downstream and a much lower data rate upstream.

The MUSIC system described here supports two fixed bit rates (13: 2 and 26: 2 Mbit / s), where the lower bit rate of 13: 2 Mbit / s can be implemented as an additional option for use at bad, or extremely long, copper cables.

For network termination (NT), the connection consists of a set of standardized interfaces, such as POTS, ISDN, ATM25 and Ethernet. All transmission protocols are supported by the carried by data flow in the modem, except the POTS service which is passively filtered out so that it is independent of (NOW) terminating in the fixed modem state. The network device network.

MUSIC separates up and downlink spectra by passive filtering in the analog parts.

The version of MUSIC described here is intended to provide the opportunity for future functional upgrades. For this reason, the FFT / IFFT block is designed to support full functionality so that it can be reused in future system upgrades.

The MUSIC system is a DMT-based, multi-carrier VDSL system that uses discrete Fourier transform to create and demodulate individual carriers. This is shown in Figure 2, which shows two transceivers each having a receiver, Rx, and a transmitter, Tx, connected to a twisted copper pair. Data is transmitted between the two transceivers using a plurality of carriers, some of which may not be used, e.g. when the channel quality is extremely poor. The number of bits transmitted by each of the carriers can also vary, depending on the channel quality. 506 636 10 25 18 A multi-carrier modulation technology such as DMT handles frequency-dependent losses and interference on twisted In the MUSIC system, the available bandwidth of 10 MHz is divided into 1024 carriers with a width of 9.77 kHz each. The assigned transmission power for the individual carriers depends on the pair cable in an efficient manner. the interference effect and the transmission losses on each of the belts. Each carrier transmits multilevel pulses that can represent up to 12 bits of data (4096 QAM). The signal / noise ratio (SNR) of the individual carrier is calculated on the receiver side. If a carrier has a high SNR, up to 12 pieces are placed on this carrier. For carriers with lower SNR values, fewer pieces are placed on the carrier. Carriers that are affected by narrow-band sources of interference are switched off. Forward error correction and data interleaving are used to mitigate the effects of temporary bursts of impulse interference.

Asymmetric VDSL is implemented in this version of the MUSIC system, which means that the downstream speed is much higher than the upstream speed. Two selected downstream speeds (26/13 Mbit / s) selected speed depends on the current cable length (supported by the system; the m) and / or the quality of the channel. The upstream speed is fixed at 2 Mbit / s.

The MUSIC system for separating the downstream channel from different frequency bands can be used in the upstream channel and both from POTS, see Figure 3.

Alternatively, other duplex methods can be used, e.g.

TDMA and / or a method where every other carrier is dedicated to the downstream and upstream channel.

Figure 4 shows an overview of a MUSIC modem to which the present invention relates. The most important hardware blocks are ADC and DAC, synchronization, fourir 20 30 506 636 19 transformation processing, channel value calculation / equalization, symbol mapping and detection, coding and decoding with interleaving, network interfaces and system monitors.

The modem can be considered in the form of four principal function blocks, namely: the digital receiver unit; - the digital transmitter unit; the analog input (front end); and “- system controller / PCI.

The analog input includes a hybrid transformer connected to an unshielded, twisted pair and POTS. On the receiver side, the hybrid is connected, via a low-pass filter, LP, a programmable gain attenuator, PGA, to an analog to digital (A / D) converter. A voltage controlled crystal oscillator, VCXO, is used to drive the analog to digital converter. On the transmitter side, the hybrid is connected to a digital to analog (D / A) converter via a low-pass filter.

The digital receiver unit includes a "fixed Fourir" rescaling unit, FFT, connected, as shown in Figure 4, to a synchronization unit and a channel estimator. The channel estimator is connected via a symbol detection unit and a "de-interleaving" and decoding unit, to a bit handling unit and from there to a network application interface.

The digital transmitter unit includes a bit handling unit connected to an inverted "fixed Fourir" transform and scaling unit, IFFT, via an encoding and 506 636 Un 10 20 (x) Un 20 interleaving unit and a symbol mapping unit.

The system control is connected to different functional units in the digital receiver and digital transmitter, and to the network application interface and a computer interface, as shown in Figure 4.

The network (work) interface connects the higher protocol level to the modem layer one functionality.

This block is responsible for providing the system with data at the configured bit rate, and adds “dummy- if required. frames ”(dummy frames) The data is then channel coded and interleaved. The MÜSIC system described here uses a convolutional code combined with interleaving. Using a depth with multiple frames, a combined frequency / time interleaving is obtained later in this specification).

The symbol mapping block receives input data as an integer vector. This vector is mapped into the configured constellation depending on the current bit load value. The mapping unit uses a Gray coding scheme to reduce the probability of bit errors.

A real (vector) vector multiplication is the first step in the IFFT block. This causes the system to scale the IFFT block then performs an FFT on the input data, which modulates each carrier path. As a final output power level on each carrier. real 2048 point inverted (inverse) step, an address “wrap around” is performed on the output data, where a copy of the forsïa 128 samples is added at the end of the frame. This is called the cyclic prefix (CP).

The modulated signal goes to a DAC which converts the signal with a minimum true dynamic range of 84 dB. The DAC is clocked by the system sample clock at 20 MHz. To get rid of Nyquist "ghosts", the signal is LP-filtered. The hybrid provides a balanced interface to the copper cable.

An overview of the signal path of the MUSIC transmitter and receiver is shown in Figure 4. The transmitter part uses the same hybrid design as the receiver.

At the receiver end, the splitter / hybrid transceiver separates the frequencies used by the POTS, from 0 to 4 kHz, from the frequencies used by the system. It also extracts the low-level reception signal from the combined high-level transmission signal and the low-level reception signal.

To reduce Nyquist effects on the signal, the received analog signal is low-pass filtered before being fed into the PGA (Programmable Gain Amplifier).

PGA n is necessary to make the best use of the dynamic range of the ADC. In this system, the dynamic range shall be at least 66 dB.

After the signal is converted to digital format, the synchronization and FFT blocks receive the data.

The synchronization block generates a frame clock (for controlling the FFT buffers) and a control signal for the VCXO.

Initially, the retrieve synchronization block retrieves the frame clock from the sampled signal. The frame clock is then used to calculate the frame synchronization value calculation and transmitted to VCXO feed back (20 MHz). (frame timing estimate) controller ". The VCXO generates the sampling clock A sampling clock controlled only by the" frame time estimate "is not sufficiently accurate in a DMT system.

Therefore, after the locking sequence, a dedicated pilot carrier is used to achieve a high synchronization precision on the sampling clock.

A BSI signal is also extracted from the pilot carrier.

BSI is the Base Synchronization Interval timing signal used to synchronize the CCH communication of the transmitter and receiver.

One of the new aspects of the MUSIC system is the algorithm used by the synchronization block, which is discussed in more detail later in this specification.

A 2048 point real FFT is performed on the input frames of the FFT block. After this, rescaling, which is based on the energy charge parameters, is performed before the data is transferred to the next block.

The channel value calculation and equalization is performed on the output data from the FFT block. All data frames are used to value the channel properties. These are then used to compute a bit charge vector that determines the number of bits to be transmitted on each of the carriers. This information is then transmitted to the transmitter through the upstream control channel (CCH).

In the symbol detection block, a "demapping" is performed for each carrier according to the bit-loading mask.

After mapping, “deinterleaving” and “Forward Error Correction” (FBC) are performed on the detected bitstream.

The data is then ready for the network (plant) / application interface block after bit handling. The dummy frames are removed in this block.

At the heart point of the system, shown in Figure 4, is SC). a general purpose processor that interfaces the system controller (System Controller, SC) is UI 25 30 506 636 23 against and controls the various sub-blocks using a local PCI bus. In the version of MUSIC described here , the CPU is programmable.An external port is provided, through a JTAG interface on the motherboard (on-board), to facilitate programming.

The main tasks of the SC are to control system start-up and construction during driving time and to perform bit charge and energy charge calculations. It communicates with the remote side of the modem through a dedicated control channel (CCH). This channel transmits data regarding changes in bit / energy charge and other system signaling.

To obtain a cost-effective product for high-volume use, the digital components of the system must be based on at least two ASIC circuits. Figure 5 shows how the system can be divided (partition) for chip design purposes.

One chip contains the FT / IFFT core. A second chip contains frame synchronization, channel value calculation and smoothing, symbol detection and symbol mapping. The analog block and the network interface block can be implemented on a third and a fourth chip, respectively.

The system parameters used by the MUSIC system described here are shown in Tables 1 to 3 attached hereto.

VDSL systems operate in the spectrum from 0 to 40 MHz.

In this band, the MUSIC system, as described here, occupies the lower 10 MHz, see Figure 6. A number of traditional bands are found in this spectrum, including POTS and some radio amateur bands. Different frequency bands are used in the MUSIC system described here to separate downstream from upstream channels. Since the MUSIC system described here uses 1024 carriers over 10 MHz, each carrier has a bandwidth of 9.77 kHz, where the first two carriers are allocated by the DC level and the POTS service. The last carrier is disabled because it is the Nyquist point. 506 636 20 IJ Un 30 24 Other carriers (on radio tapes) may need to be canceled. This is primarily a matter of immunity and charisma on the balanced copper pair.

By passively filtering the POTS spectrum, this service can be done independently of the MUSIC system described here, runtime status, or power supply.

There are two ways to provide ISDN services for a MUSIC modem connection. One way is to let the POTS and ISDN systems exist under the (below) MUSIC frequency bands. This can be achieved using a similar filtering process for ISDN band spectrum as for POTS. This filtering allows the service to be provided regardless of configuration.

The second way to provide ISDN is to allow ISDN to be a carrier service in the MUSIC system. This solution has the advantage in terms of spectrum efficiency. The use of 1024 carriers over 10 MHz gives each carrier a bandwidth of 9.77 kHz. The ISDN spectrum requires the allocation (150-4) /9.77 = 5, of these carriers. Depending on the channel characteristics, these five carriers must be chosen to have the best SNR in the system. For a standard connection, this gives 5 * 100 = 50O kbit / s bandwidth.

The optimal solution is therefore to use the modem as a carrier, and allocate only 64 kbit / s, compared to 500 kbit / s for the total bandwidth of the 64 kbit / s ISDN service.

The results of the measurements of attenuation and FEXT (Far End Cross Talk) performed on a telecommunications operator's network, showed that it is possible to achieve bit rates higher than 100 Mbit / s if the cable is shorter than 2C3-300 meters. For longer cables, attenuation at higher frequencies limits the maximum bit rate. 10 20 30 506 636 25 For cables of about 500 meters, 40 Mbit / s can be achieved, and for a 1 km cable, 15-20 Mbit / s is realistic.

Another factor that reduces performance is EMC, which limits the power used. Some parts of the frequency domain may also need to be excluded.

A typical PSTN can be expected to have the following characteristics in terms of impulse interference: - maximum duration 250 ps - median interval 67 ms - maximum peak amplitude 20 mV - main energy below 200 kHz - background interference -107 dBm / Hz The main source for synchronization in the system is the sampling clock. The reference for the sampling clock is located on the NU page and is common to all twisted copper pairs in a secondary cable.

The sampling clock frequency is 20 MHz at 10 ppm, with a phase jitter of less than 0.5 ns.

The sampling clock on the NT page is phase locked to the NOW page. The logic of the reading uses the frame synchronization value calculation (frame timing estimation) in a first stage, and then uses the pilot carrier to produce a fine adjustment of the reading. The load logic controls the frequency of a VCXO via an 18 bit digital / analog converter. The requirements for the VCXO are 20 MHz in 25 ppm range and 10 ppm / volt sensitivity. The final reading must have a precision of l / 100 samples, with a "phase jitter" of less than 0.5 ns.

The frame clock is l / (2048 + 128) of the sampling clock and controls the start of receiving and sending the frames. 506 636 30 26 The frame clock, which is used for both transmission and reception, deviates in phase on both the NU and NT side.

The frame clock for transmission on the NT side is the master and controls the start of the signal intervals, see Figure 7.

The reception frame clock on the NT side is obtained from the hardware function for the frame synchronization value calculation and controls the start of the frame sampling period, see Figure 7.

The frame clock for transmission on the NT side is the same as the frame clock for reception, but is a TA sample earlier in phase. TA is a parameter that is measured during system start-up on the NU side and is used to compensate for propagation delay on the copper conductor. This must be done to maintain the orthogonality, across the copper conductor, for the sampled periods, both on the uplink and downlink. The frame clock for transmission on the NT side controls the start of the signal intervals, see Figure 7.

The frame clock for reception on the NU side delays a number of sample clock cycles (TA) in relation to the frame clock for transmission, after TA calculation has been performed. The delay before the calculation of TA in the start-up sequence is determined by the hardware function for the frame synchronization value function (frame timing estimation hardware function) and the value is accessible to the control unit.

The frame clock for reception on the NOW page controls the start of the frame sampling period, see Figure 7.

The BSI clock is used to synchronize parameter changes between the sending and receiving taww __ * pages. The parameters can, for example, be bit charge, energy charge or control channel frequency. The parameters are updated by the system controller, on both sides, before the BSI clock initiates the switch for the new set-up. 20 BS 506 636 27 The BSI clock is 1/8192 of the frame clock. The uplink BSI clock is delayed by half a BSI clock cycle relative to the downlink BSI clock.

A short pseudo-random sequence on the pilot channel is used for BSI synchronization between the transmitting and receiving sides.

The cyclic prefix is an extension of the frames added by the FFT chipset. To maintain orthogonality throughout the signaling period, the last 128 samples of the frame are copied and placed before the actual frame. This arrangement addresses issues related to interference between symbols caused by time dispersion.

It is important that the part of the signaling period sampled only on the receiving side overlaps a signaling period in the other direction, along the entire copper conductor. TA is used to optimize this overlap period. The maximum cable length is limited by TA = 128 samples = 6.4 ps propagation delay. This corresponds to 1280 meters (if the propagation delay is 5 ns / m).

The analog interface connects the received and transmitted digital data stream at the Cl chip to the telephone line. There are also connections to the T1 chipset and the system controller for control end cases.

The analog interface is shown in Figure 8. The cable is connected to a hybrid transformer which is also linked to POTS. On the receiving side of the hybrid, the incoming signal passes through a low-pass filter and a programmable gain attenuator to an analog-to-digital converter, ADC, and from there to the C1 chipset. On the transmitter side of the hybrid, the output digital signal is converted to analog by a digital / analog converter, DAC, and goes from there via a low-pass filter LP to the hybrid transformer. A voltage controlled crystal oscillator, which drives both the ADC and the DAC, is connected to the sync block of the T1 chip.

An OFDM frame is a sum of sinusoidal carriers modulated in phase and amplitude and spaced in the frequency domain with a minimum of separation distance between carriers. The assumption that the symbols within the frame are evenly distributed and uncorrelated in relation to each other gives a signal in the time plane with an approximately normally distributed instantaneous amplitude. Thus, there is a small possibility that input data can interact with each other to create pulses with very high peak levels.

However, the maximum amplitude must be limited to a lower amplitude than this so that there are a sufficient number of quantization levels in the DAC to handle (average) average signals. Although the DAC n has sufficient resolution to accommodate a high peak level in the transmitter, there are limitations on the receiver side (ADC). However, the consequences on the recipient side do not have to be as serious as they may seem.

A short cable has lower attenuation in the high frequency range than a long cable, see Figure 9. This means that a temporary pulse can occur in the receiver almost unaffected by the cable characteristics. Therefore, a relatively large dynamic range is required in the receiver. However, this can be easily achieved because almost equal attenuations do not require a large dynamic range. The ADC needs to accommodate the area indicated in Figure 9 by the solid, rough, arrow-marked line.

However, the greater high frequency attenuation of long cables requires a large dynamic range.

The high frequency attenuation also means that several large peaks would be required from the transmitter to build up high amplitudes in the receiver; a case that is even less likely to occur at the ADC input (input) than single peaks. The “free height” (headroom) can therefore be reduced and the ADC should accommodate the area marked by the rough, dashed arrow line in Figure 9.

In summary, performance can be optimized by carefully setting the signal level at the ADC receiver depending on the cable length.

The line splitter / hybrid has two main tasks, namely to: - divide and combine telephony signal (POTS) and VDSL signal frequency bands; and - prevent the transmitted signal from appearing at the receiver on the same device by balancing the cable.

Since each transmission direction has its own frequency band, it is possible to optimize both sides in terms of their respective frequency bands to increase the overall performance.

The purpose of the low-pass filter on the input signal is to reduce aliasing effects on interference above the frequency range used.

The low-pass filter on the output side reduces the transmitted power on the "stop band". These filters can form part of the division / hybrid module.

The best commercially available ADC today is the "Analog Devices AD9042" which has a signal-to-noise ratio of approximately 66 dB, it is recommended that either this ADC, or one with equivalent performance, be used.

For this description, it is assumed that a DAC with 14 bit resolution is used. The 506 636 UI 25 30 30 FFT and IFFT algorithms are built up of 1024-point complex FFTs with data reorganization to allow the calculation of two real sequences at the same time.

Consequently, each of FFT and IFFT are effective 2048 points. The hardware realization is based on a radix-32 core that calculates the result in three “transformations” (passes), see Figure 10.

The relationship between the signal-to-noise ratio and the resolution in the algorithm can be expressed as: sNR = 22 '°' “'1 where b = number of bits, and v = ll (number of effective radix-2" transformations "). The b solution provides 17 bit resolution (based on ADC SNR), but since ADC is not the only source of analog signal degradation, 16 bit resolution in the algorithm should be sufficient to maintain the resolution throughout the system.

VCXO n generates the sampling frequency used in the NT part of the system. The control voltage is based on data from the synchronization unit. The clock frequency must be very stable and phase locked to maintain orthogonality between symbols. (phase locked) to the NU reference clock To take full advantage of the dynamic range of the ADC, a programmable attenuator must be inserted before the ADC.

The attenuation level is mainly a function of the cable length and can be determined by the value for "timing advance synchronization" through the system controller.

Attenuation resolution and range, and the relationship between the value for timing advance and the attenuation level, must be determined. Equalization and variance values can also be used in the calculations for improved results.

In a DMT system, a very precise synchronization between the transmitter and the receiver is necessary, especially when carriers are modulated with large constellations.

In the embodiment described here, a new frame synchronization method is used which is based on correlation properties built into the structure of the received signal.

On the NU side, a crystal frequency oscillator with a fixed frequency is used as a reference for generating the sampling clock. On the NT side, a sampling clock is generated by a VCXO (Voltage Controlled Crystal Oscillator) which is locked in phase with the oscillator on the NU side. The VCXO is initially controlled by the frame timing estimate.

However, the resolution of the frame synchronization value calculation is not sufficient in the present application. Therefore, a dedicated pilot carrier, after a lock-in sequence, is used to achieve a very high accuracy of the synchronized clock synchronization.

P 9 Depending on the long symbol duration of a DMT system, interference between symbols caused by channel time dispersion can be eliminated by using a guard interval as a prefix to each frame in the time domain. To maintain the orthogonality of the frames, the contents of each prefix are a copy of the last part of the following frame, making the frames appear to be partially cyclic.

The synchronization method used to estimate the frame synchronization uses the high correlation between a prefix and the corresponding part of a frame. By continuously correlating samples of the received signal, separated in time by the (known) frame length, the passage of a protection interval will cause a peak in the correlation value calculation. Therefore, these peaks will have a known synchronization relationship with the frames and can be used to create a frame start signal. The principle is shown in Figure ll.

The correlator and peak time estimator use a system clock generated by a VCXO. This clock is divided by (divided by) the total number of samples in a signal range (a cyclic prefix and a frame), to create a signal with the same period as the correlation peaks.

The frame time deviation between these two signals is used as input to a feed-back controller which adjusts the VCXO frequency to the correct sampling frequency. However, the phase of this sampling clock is not accurate enough to be used in a DMT system. Therefore, the frame synchronization value calculation is mainly used for a lock-in operation. It is also used to monitor frame synchronization to detect major anomalies that will necessitate resynchronization.

The correlation of the received data is calculated continuously. The time difference between the two signals is achieved by using a digital delay line of one frame length. The output of the delay line is multiplied by the non-delayed signal and integrated (accumulated) over an interval corresponding to the length of the cyclic prefix. The output from the integrator is the value calculation (estimate) of the correlation function.

Since only the synchronization information of the correlation value calculation is used, a simplified estimator is implemented which only uses the reduced complexity symbol of the input data compared to using it (sign). This hardware implementation has a very complete sample word length. Computer simulations have shown that the use of synchronous averaging of several signal intervals reduces the variance of the frame synchronization value calculation. Depending on the reduced data word length used in the multiplier part of the correlator, it is possible to implement such averaging multiplication function.

A block diagram showing the implementation of the correlator is shown in Figure 12. The incoming signal X (k) passes through a delay of N = 1024, i.e. a frame, and to a conjugator. The output of the delay and the conjugator is then multiplied to produce a signal Y (k) averaging, which Z (k) signal W (k) goes to an accumulator which gives an output signal C (k). which goes to an average value generator. The output from Z (k) goes to a subtractor from delayed by L = 128 is subtracted. This gives a The details of the averaging part of the correlator are shown in Figure 13. The averaging comprises a series of delay elements combined with adders, as shown. The output signal can be expressed as Mm Z (k) = Y (k-iM) '0 H ll where Y (k) is the input signal and Z (k) is the output signal.

For az: to make the averaging synchronous with the frame structure of the signal, the delays are equal to the signal interval.

A detector for finding the position of the maximum size of the correlation function value calculation is shown in Figure 14. It is implemented using a register (# 1) for the latest max. Value and a comparator. 506 656 10 20 30 34 The register contents and the correlation size are compared, and each time a value greater than the register contents is found, the new value is stored in the register. The current value of a counter that counts sampling intervals (modulo signal intervals) is also passed to a second register (# 2). When an entire signal interval has passed, this second register will contain an index to the maximum value found during this interval. This index is stored in a third register (# 3), once per signal interval, and the contents of the first register (1 #) are divided by two (using shift). (using The index stored in register # 3 is interpreted as the deviation between the counter value and the current synchronization of the input signal frames. The feedback controller will cause the mean value of this deviation to converge to zero. The counter value can be to the signal interval. ) using this counter value to indicate the frame start.

The value calculation of the complex representation of the pilot carrier in the frequency plane is performed using the FFT unit available in the system. The advantage of using this method is that the value calculation will be independent of the varying modulation of other carriers. This is due to the inherent orthogonality between the carriers. In order to achieve a value calculation with acceptably low variance, a certain average value formation is necessary. This is done using the first-order digital IIR filter.

Unfortunately, the value calculation is represented as a complex number in rectangular coordinates, so the argument is -v- not directly available. in the feedback loop it is necessary to detect very small 20 h) argument deviations. Therefore, the resolution of the argument must be high. The feedback controller will cause the pilot carrier argument to converge to zero. An approximation of the argument, which is linear only in a small area around zero, is then sufficient to achieve acceptable performance. A useful approximation that is "monotonic" in almost all four quadrants, and also easy to implement in digital logic, is described by the expression: A = M.KHC} - (1-sgn¶ {C}). K. ¶ {C} .sgn.3 {CH where C is the complex pilot carrier value calculation, M is a positive scaling constant, and K is a positive constant that affects the design of the function (here K = 2 is used).

The channel introduces phase shifts on the pilot carrier which can cause “misalignment” between the frame synchronization on the input signal and the pilot argument zero.

To eliminate this problem, the pilot carrier estimator also runs through the frequency domain equalizer. The smoothing parameter for this carrier is set during the start sequence, when the frame timing estimate has converged to its final value.

The choice of pilot carrier will be fixed, but logic for choosing other carriers as a pilot can also be provided. The feedback loop actually has two "controllers", each with its own input signal. The two controller outputs are added and fed via a D / A converter to the VCXO which generates the sampling clock. Both "controllers" are of the PI type (Proportional and Integrating). 506 656 10 25 30 36 Figure 15 gives an overview of the signal paths. The received data in the schedule passes through the correlator and the peak position estimator to result in the frame clock. The complex pilot carrier in the frequency plane derived from the equalizer is fed to a pilot argument estimator, the output of which is fed to "feedback controllers" which also receive output from the peak estimator. The output of the “feedback controllers” is then passed to a D / A converter to provide a signal used to control the VCXO.

During the startup sequence, only the frame synchronization controller is active. Once the frame synchronization has stabilized, the equalization parameter for the pilot carrier is calculated and set (by the SC}. This is done only once, and further updating of this parameter is suppressed. After this change of the equalization parameter, the averaging for the argument estimator is given sufficient setting time.

Finally, the frame synchronization controller is stopped and the pilot argument controller is activated. When the frame synchronization controller is stopped, its last value is locked so that the VCXO frequency remains close to its final value.

Thus, the synchronization technique of the present invention provides a phase lock loop, for recovering the sampling clock, with a very small bandwidth. This produces a sampling clock with an accurate phase, ie carefully aligned with the sampling clock in the transmitter. Since the locking area is very narrow, a special lock-in sequence is required.

As can be seen from the foregoing description, a frame time deviation signal from the time domain data stream is attenuated using a correlation method. This signal is used UI 10 25 30 506 636 37 to phase a oscillator which generates the receiver sampling clock. The average value of the clock frequency thus generated will coincide with the transmitter sampling clock frequency. Unfortunately, the phase difference between the transmitter sampling clock and the receiver sampling clock will have too great a variance.

A second feedback loop that uses an estimate of the pilot carrier argument is therefore used. The oscillator control signal is, as shown in Figure 15, the sum of the two outputs of the feedback control device. The pilot carrier argument is continuously calculated in value, but is not used in the first part of the synchronization sequence. The synchronization sequence comprises three steps, namely: 1. 2. The pilot carrier argument is used as a smoothing parameter for this carrier to compensate for channel induced effects. Both of these feedback loops are then used in parallel for a short "establishment period" (settling-down period). 3. The last output value from the frame synchronization deviation loop is maintained as part of the oscillator control. The feedback loop for the pilot carrier argument is then the only remaining variable parameter used to control the receiver sampling clock phase_ 506 636 38 The frame synchronization deviation is monitored separately for possible large values. If large values of frame synchronization deviation are detected, the system is resynchronized.

The present invention is thus characterized by: a combination of two synchronization techniques for resetting frame synchronization, in addition to fine-tuning a receiver's sampling clock; - a special sequence of synchronization operations, as set forth above; and n - a smoothing operation performed on the pilot carrier to place zero argument crossings at the correct sample interval.

The pilot carrier path is also used for the transmission of Base Synchronization Interval (BSI) synchronization information. The carrier argument is normally assumed to be constant.

A short pattern is BPSK modulated on the carrier using phases 0 and n and leaving the carrier on phase 0 for the remainder of the BSI interval. If this pattern is only a fraction (the pilot carrier argument value calculation is negligible. A correlator is used to detect the pattern and provide the synchronization signal for BSI. The "System Controller" (SC) must have read access, for detection of synchronization lock and for monitoring reasons, frame time deviation and pilot argument approximation_ Un 20 25 30 506 636 39 To handle the initial smoothing of the pilot carrier, it is necessary for the SC to read the mean-formed complex representation of the carrier and write to the smoothing parameter memory_ A compensation register (offset register) the input frames and the frame start signal are necessary and must be writable from the SC. This is used on the NT page.

The detected BSI event signals, for both reception and transmission, must be connected to the SC as interrupt inputs.

Alternatively, the pilot carrier can be recovered from the signal in the plane, using a bandpass filter, and used directly to phase lock a sampling clock oscillator. The frequency plan method described here has the advantage that the pilot carrier estimator is independent of the modulation of the other carriers. Another frame synchronization method would depend on introducing a known pattern into certain frames.

This would reduce system capacity.

The frame length and the length of the cyclic prefixes are fixed in the embodiment described here. The method, described above, is designed to work in a feedback loop with a VCXO. In a device using a specific sampling clock oscillator, the design of the frame synchronization estimator needs to be slightly modified. It is important that the VCXO has a very low phase fault, as the feedback loop is too slow to compensate for such a fault.

A discrete multitone system (DMT) modulates N complex data symbols on N carriers (here we use N = 1,024 carriers). This mapping is calculated as a reverse (inverse) discrete Fourir transform using Inverse 506 636 10 20 40 (IFFT).

N st carriers of an FFT.

Fast Fourier Transform In the receiver they are demodulated in the modem, described here, FFT and IFFT are performed by (radix) 16, 32 "cores", in different phases. This process is shown in the same unit, using the same base or schematically in Figure 16.

The main operation is divided into frames with lengths of 2048 real, or 1024 complex values. For each frame, this unit performs an FFT, IFFT, scaling, descaling, and adding cyclic prefix.

The FFT and IFFT n calculate 2048 points of real FFTs and work with a minimum of 16 bit arithmetic.

For the night terminal side, (NT), there is a requirement for synchronization between the input frame start and the IFFT output start. (A synchronization between the upstream and downstream carriers). The transmitter must be able to start transmitting a frame before it starts receiving a frame, so-called "timing advance".

A scaling should be provided before IFFT.

This scaling is a multiplication between the real coefficients stored in this unit, and the input values from the symbol mapper (SM). The coefficients are 16 bits each.

The coefficient memory consists of two banks of the same (l6X1024 bit).

Switching is made possible by size One bank is used while the other is updated. a PCI command and executed at the next BSI.

After the FFT, a rescaling must be performed before the data is transferred for smoothing and symbol detection.

This rescaling is a multiplication by the inverted value of the scaling values. The coefficients are represented by 16 bits. 20 k) UI 506 636 41 An exponent (resulting in a "post shift") of 4 bits may also be needed to maintain precision.

The coefficient memory consists of two banks of the same ((l6 + 4) Xl024 bit). others are updated. Switching is made possible by a PCI size One bank is used during the command and executed at the next BSI.

At the beginning of each frame, a cyclic prefix is added.

This process is shown schematically in Figure 17. The insertion of a cyclic prefix eliminates interference between symbols (ISI), and preserves the orthogonality between the tones, resulting in a simple input / output ratio that allows each carrier to be considered as a separate channel. .

This cyclic prefix consists of a repetition of the last part of the frame.

Provided that "timing advance" is used and the maximum cable length is 1300 m, a cyclic prefix of 128 samples will be required. Thus, the output for each frame will be a sample: 1920, l92l, ..., 2046, 2047, 0, l, 2, 2046, 2047 For each of the above components there is a FIFO as an interface to the external world with FFT / IFFT input and output memories. Thus, there are a total of 4 FIFOs.

It is recommended that the FIFOs with interfaces to it and the FIFOs that interface with Tl chips have a size of 448 words (32 bits). analog side has a size of 384 words (16 bit) Another DMT technology that does not use "Fourir is" Discrete Wavelet Multi-tone Transform "(DWMT). This method has been submitted to the ADSL Transformation "Standardization Committee" which rejected it. 506 636 10 20 25 30 42 The precision required in this technique depends on the required dynamic range, which in turn is determined by the analog components (especially DAC). The FIFO size will depend on clock speed differences and the amount of timing advance used. The use of clipping is a compromise between dynamic range (quantization perturbations) and clipping perturbations.

Channel value calculation is performed with a “decision-oriented” method, since all data frames are then used to update the channel model. Known data frames are necessary only at start-up. Under certain circumstances, interference on the channel can be calculated using all data frames. This is important for early detection of changes in channel transmission quality.

The basic principle for “decision directed” value calculation is that differences between received data and known, transmitted data are used to update a channel model. the channel model is accurate enough to be used for At some point in this process, the received data is smoothed, and the detector will produce correct data. This output can then be used in the same way as the known data for further updating of the channel model. Therefore, the predefined data frames are no longer necessary and random data transmitted through the channel is used instead.

By using data taken after the equalizer as input data, and data after the detector as the second input data, an adaptive update algorithm can be designed. It modifies the equalization parameters in small steps in such a direction that the equalizer converges towards a model of the "reverse" (inverse) channel. Figure 18 shows a block diagram of such a system. Input in the frequency plane enters the equalizer and is multiplied by the output of an update unit for_u: equalization parameters, EQ. The resulting signal, U, then goes to a detector (quantizer) whose output is Y. Y then goes to a symbol decoder which produces a decoded data bitstream. U and Y also go to an input (input) on the equalizer parameter update unit and to a variance estimator.

The output of the variance estimator is W.

An adaptive algorithm for calculating the value of (EQ), and the quantized data (Y) the equalization parameters the data (U) using the equalized as input, are described by the following equation: as = Book + ”.EQwUkÉ (Yk- Uk) | U1 <| 2 where u is a positive constant (p << 1), which affects the adaptation dynamics. A smaller value gives a slower adjustment than a larger value, but it also gives a greater insensitivity when there are disturbances on the input signals.

For implementation reasons, the division shown in should have too large a dynamic range to be replaced by a constant. That is, the equation is avoided. However, the expression p / IUKP is possible to quantify this expression in a logarithmic way as shown below: LL / ltjklz 2 2-1 == eger (z.1og2lUxl> + in = eger <1og2u> The exponent in the above expression can be produced using the absolute value of Uk as input in a binary priority encoder and negating characters (negating) on output.

Since the expression is an integer power of two, the multiplication in the algorithm is implemented by means of a “barrel shifter” 506 636 UI 20 30 44 The interference variance of each of the carriers is value calculated using the standard method of integrating the squared deviations from an average value. In this case, each quantized value, Y, is used as the mean of the range of data values, U, which is quantized to this Y. This method assumes that the symbol error rate is low enough for each data value to be associated with the correct mean. However, if suitable constellations are selected for the different carriers, this condition is met.

Figure 18 shows the variance estimator as part of the system. The algorithm used for the value calculation is described by the following equation: Wlvkl = .Wk + 8. [Yk_Uk'2 The integration is here replaced by an exponentially weighted average filter. The parameter s is a small, positive constant (S << 1) that affects the dynamic properties of the filter. This is not a critical parameter, and choosing s from integer powers of two will suffice.

If a value of 6 is selected which gives a good variance value calculator (estimator), the algorithm will not be able to detect sudden changes in the interference level.

Therefore, a separate algorithm, working in parallel with the variance estimator, may be necessary for this task.

The "System Controller" must have both read and write access to the memory that holds the smoothing parameters.

Initialization of the parameters is necessary at start-up. Monitoring of the parameters is also necessary to detect when they have leveled sufficiently close to their final values. 20 30 506 636 45 The channel variance memory must be available for the System Controller's read operations. Initialization of this memory to all zeros can be connected to a system reset.

The parameters that affect the dynamics of the estimators must be available for writing from the System Controller.

The method described here assumes a specific start-up sequence, both for the channel and interference value calculation. During normal execution, it is dependent on an appropriate bit charge selection that provides a sufficiently low symbol error rate.

It is important that the smoothing parameters are initialized to unit value at the beginning of the start sequence, as the input to the update algorithm passes through the equalizer.

The update algorithm is sensitive to scaling changes in the data path.

Any change in scaling in the transmitter must be compensated in the receiver. This also requires special care when using the analog gain control on the input side of the receiver. (encoder) maps a number of bits to the Symbol Map a complex number (I, Q) which indirectly determines the phase and amplitude of a carrier. The mapping of all values of a certain bit length is called a constellation, and is shown in Figure 19. The detection is the inverse function, ie from a complex value the value of the bits sent on the carrier is determined. The number of bits transmitted on a particular carrier is determined by the bit charge factor thereof.

The construction of a specific constellation is aimed at allowing each point to be moved as far as possible from all other points. At the same time, the average energy should be as low as possible. Another restriction is that the mapping and detection units should be as simple as possible. However, the decision as to which constellation to use will affect not only the symbol mapping and detection units, but also the bit charge and possibly the adaptive equalizer.

For a given carrier, the encoder selects an odd integer point (I, Q) from the square-grid constellation based on the b-bits (vb¿, v¿4, _ | vLv¿). For simplicity of description, these b-bits are identified by an integer label whose binary representation is (vg1'v¿4 '___, vLv2). For example, for b = 2, the four constellation points 0, 1, 2, 3 are "labeled" corresponding to (vLv¿) = (0,0), (0,1), (1,0), (1,1), respective.

For even values of b, the integer values of I and Q for the constellation point (I, Q) are determined from the b-bits (vbl vb 2 | ___ | vLv¿) as follows. Divide V by VI = (v¿¿I \% _ L ”_, vl) and VQ = (vb2, vb4, _, __ v0). Then apply the reverse Gray code to VI and VQ. This gives I and Q as I = 2Gra¶ (VI) + 1, and Q = 2Gray (VQ) + 1.

Figure 19 shows how the binary pattern for V folders on I and Q when b = 6.

Before these values are sent to IFFT n, they are normalized by shifting so that “msb” of these numbers becomes “msb” on the output (16 - [b / 2] steps left).

For a given carrier, the decoder uses a constellation point (I, Q) to determine the b-bits (vb¿_, vLv2). vbQ, ___ For simplicity of description, these b-bits are identified by an integer label whose binary representation is (vb¿, v¿4 'U lvllvz).

It is assumed that the values of I and Q are limited by saturation to the range (X, Y). To determine V, Gray-coded, i1, io) f and Q = (qis fl ln,, q1, qo) / And then combined to V as V = (giH, gqß, giM, gqn, .... J, the values I = (ilíin, where the upper b-bits are valid.

The number of bits each carrier transmits depends on their respective signal-to-noise ratio (SNR).

The signal-to-noise ratio is calculated for each carrier in the receiver. Based on the signal-to-noise ratios, bit charge factors are calculated for each carrier. Thus, the number of bits each carrier must transmit per transmitted symbol is determined.

These bit load factors are calculated in an initial training session and can be updated if required.

The MUSIC system uses 2-dimensional Quadrature Amplitude Modulation (QAM) on each carrier, with bit charge factors ranging from 0-12 bits.

The number of bits transmitted on each carrier can be expressed by: (l) SNRi) ßi = bi + log2 (L) = logz (1 + r where I ", the SNR gap, depends on modulation, possible coding and a system margin, and L is the constellation expansion depends on the extra bits needed for coding.

The use of QAM constellations and some form of coding gives: [Q fl psm>] 2 r = g - Vd + ymargin 3 (de) (2) IO 20 25 506 656 48 where Psär the desired symbol error rate, 'm is the "coding gain" ( gain of coding) in the system, Ymargin is the system margin.The system margin is a factor used to compensate for unmodeled losses, impulse disturbances, etc. Equation (1) gives a bit charge factor with infinite granularity.

The bit load factors are rounded to give the Supported Factors (0 - 12 bit).

The rounding procedure will reduce the performance of the DMT system. If the energy distribution is allowed to vary, energy charge factors can be calculated for each carrier. This provides the ability to tune the energy so that (1) results in a bit charge factor supported by the system. Reconciliation gives: (Qi-Uf E, _ 2 mi (3) However, this can result in very large differences between carrier energies. In an environment with several different DMT systems, peculiar effects can occur if the different energies are allowed to vary too much.

(FEXT) such an environment, and some DMT systems can get the entire cable Remote crosstalk will vary considerably in a capacity. To prevent these effects, only small changes in the carrier energies can be allowed. Another limiting factor is the maximum energy allowed on each carrier.

The input data to the bit load algorithm will depend on the selected frequency domain equalizer. If an adaptive DFE is used, SNR is obtained by: sNRi = wi (4) where Wi is the value-calculated interference variance described above.

For each carrier, a bit charge factor and an energy charge factor are calculated. The bit load factors can be represented by 3 bits, but to prepare the system even for odd bit load factors, 4 bits are recommended. For energy charging, n bit is used to give 2 "- 1 possible factors.

The implementation of the calculations of bit charge and energy charge factors can be done in four steps shown in Figure 20. To achieve a given bit rate, a required SNR can be calculated and the system margin adjusted so that the desired bit rate is achieved. The process, illustrated in Figure 20, includes the following steps; - First, the SNR is calculated using (4).

In the second step, four comparisons are performed, ie one for each of the four bits representing the bit load factor.

The thresholds depend on L and F, and can be pre-calculated. The first comparison determines if the bit charge factor is greater than 7, and the result of this comparison controls the first of the four bits representing the bit charge factor; it also controls the threshold for the next comparison. Similarly, this comparison controls the second bit and the threshold for the next comparison. After the four comparisons, the bit charge factor is determined.

- The third step is to value the scaling factor for the transmitted energy so that the channel is used more efficiently. The energy is scaled according to equation (3). 506 636 l0 20 30 50 - Finally, the scaling factor is quantized to n bits.

It should be noted that in order to implement a system of constant energy charging, only the first two steps are necessary.

The energy charge and shift performed for normalization in the symbol mapping determines the scaling and rescaling factors sent to the IFFT / FFT processor.

The purpose of channel coding is to reduce bit error rates. The type of coding that should be used depends on the error pattern characteristics. Expected sources of error include random noise (which induces random bit errors), impulse disturbance (which induces erroneous bursts) and clipping (which induces erroneous bursts).

Faults caused by impulse disturbances mainly affect one or two bits per carrier. The probability of a single bit error on a carrier is always higher than the probability of 2 bit errors, which in turn is higher than the probability of 3 bit errors, and so on. This depends on the way in which the bits in the symbol are coded (ie Gray coding).

All coding depends on a synchronization to determine the start bit for the codewords and / or the "interleaving" blocks. "Simple dead reckoning" should be sufficient, because an error in data flow In a system such as the MUSIC modem (data flow slip) can never occur without loss of frame synchronization, or error setting during bit loading. These errors necessitate a partial, or complete, system startup.

Un 20 30 506 636 51 The channel coding will also include interleaving to increase the possibility of correcting burst errors.

"Interleaving" should be as deep as possible to obtain optimal function.The limiting factor in depth is the time delay introduced into the system.

The difference between time and frequency interleaving is of little importance because the coding and interleaving function is not sensitive to frame boundaries.

Reed-Solomon codes have the disadvantage that they are mainly burst error correction over a small number of bits (usually eight), a so-called symbol. Pulse errors from impulse disturbances generally introduce a “single-bit error” in some of the symbols. To take advantage of Reed Solomon codes, the most "error prone" bits must be concentrated on one, or a few, of the Reed-Solomon symbols.

The system margin as such (in itself) is a kind of coding that uses the margin of each carrier as the redundancy of the symbol. This redundancy per symbol must be converted to a "shared" larger number of symbols to handle burst errors. The higher redundancy that can be used by a coding rate that this introduces, can be used by certain types of convolutional codes.

The use of a convolutional code combined with "soft" information is therefore the optimal solution for a system with MUSIC channel characteristics.

The folding code must be combined with interleaving.

It is possible to use a "top-level" Reed-Solomon code, or some other error correction code, e.g. Fire codes, to detect / correct the remaining bit errors. 506 636! 0 20 IQ Un 30 52 This is especially useful because these errors occur in bursts as a result of the decoding of the convolutional code.

The "System Controller" is based on a "micro controller", or signal processor, depending on capacity requirements, for the MUSIC system the processor can be placed externally.A PCI bus interface is used to connect the System Controller and the various ASICs that make up the modem.

The function of the System Controller is shown schematically in Figure 21, which shows the paths of interaction over a PCI bus, between the System Controller and the FFT chip, the data mapping and detection chip, and the coding and decoding chip. Functions performed by the system controller are: - management of "Control Channel Signaling", - calculation of bit charge and energy charging factors, - updating of system parameters in real time, and - system monitoring.

The System Controller, which is used for the modem described here, is programmable and accessible through a JTAG interface on the motherboard (on-board).

As shown in Figure 22, in a modem context with modem described here, the two data paths operate independently on the same physical copper cable, (NOW) the network termination (NT) on the user side. Both the transmitter Tx terminating in the network (work) unit on the network side, and and the receiver Rx are controlled by the System Controller.

The System Controller calculates and updates, after start-up, the bit charge and energy charge factors_ This update must be done at the same time as starting from the same frame, on both the transmitter and receiver side.

IO 30 506 636 53 The calculations are made and the update is initiated on the receiving page. The control channel, combined with the BSI clock, is used to ensure the synchronization of the update.

System Controller also monitors the system. Indications of system errors include the control channel starting to indicate errors, or receiving too many errors from the decoding channel unit.

The System Controller can initiate reboot at different levels; for example, go back to "idle mode", or do a full boot.

The control channel is a selected carrier that is only used for signaling between the two modems. The constellation on the carrier is initially 4 QAM and the data rate is approximately 16 kbit / s. The bit load can be changed to another constellation to increase the data rate.

The protocol on the control channel is partly based on HDLC for the physical layer. This means that the messages are packaged as a number of octets using "flag sequence" and "bit-stuffing". A 16-bit "frame check sequence" guarantees that each message is received correctly.

"Flag-sequence", "bit-stuffing" and "frame check sequence" are handled in the hardware on the mapping and detection chip. The contents of the messages are handled by the System Controller.

The maximum message length is limited to 64 octets depending on the size of the buffers on the mapping and detection chip.

Higher level protocols can be based in part on CCITT Q.92l recommendations.

In MUSIC modem SC several different vectors are handled; these are shown schematically in Figure 23. 506 636 10 20 25 30 54 For the transmitter part there is the bit charge and energy scaling vector. Corresponding on the receiver side is the bit charge, rescaling and equalization vector.

As previously described, the pilot carrier delivers a transmitter / receiver synchronization by transmitting and detecting a specific pattern. This clock is used by the system to synchronize changes in the transmitter and receiver vectors.

The time between the pilot synchronization patterns is called the Base Synchronization Interval (BSI) and is determined by the system response time, as shown in Figure 24.

This BSI is hardware dependent. Its length will not change, as the response time always remains the same.

When the system is running, there will be synchronization between the uplink transmitter: and the receiver, through "base (BSI-U) see Figure 25. These BSIs are of exact sync interval uplink" (BSI-D), the same length but are half shifted BSI interval and base sync interval downlink The SC at the NOW, or NT n, interrupts for both BSI-U and BSI-D will receive For the NOW there will be a broadcast BSI -D- interrupt and a receive-BSI-U-interrupt_ By switching BSI-U with BSI / 2, the SC charge will be better distributed over the BSI period.

The bit charge vector provides the system with the modulation pattern for each carrier. This is a vector that needs to be maintained and updated at exactly the same time on the transmitter and receiver side to provide a faultless connection. By using the BSI, the vector changes synchronously on the receiver and transmitter side. 20 IJ Uu 30 506 636 55 The bit charge factors, constellations used on each carrier, are handled by two memories for reception and two memories for transmission on the mapping and detection chip. Each of the four memories contains a 4-bit word for each carrier (1024x4).

The System Controller identifies which of the memories to use to send and which to use after receiving from the next BSI interval.

The bit load factor can have values between 0 and 12, where 0 indicates an unused carrier; 1-12 indicates the number of bits in the constellation (eg 2 for 4QAM, 4 for 16QAM, 10 for 1024 QAM).

The energy vector pours information on how the carrier paths are scaled / rescaled for energy. This is a vector that needs to be updated synchronously, otherwise it will generate a distorted channel value calculation and bit error. The scaling vector will also be used as a pattern (mask) for canceled carrier paths.

Scaling of the various carriers on the transmitter side is handled by a memory area on the FFT chipset. The memory consists of a 16-bit word for each carrier (1024 x 16). These values are multiplied by the vector of each carrier in the frequency domain (I and Q are multiplied by the value separately).

The memory is doubled to ensure a synchronous update. The System Controller points out which of the two memories will be used from the start of the next BSI interval.

A corresponding memory (doubled) is implemented on the receiver side to rescale the carriers before symbol detection. If these memories contain a complex 506 636 UI 20 56 value for each carrier (32 bits / carrier), only the I value will be used for rescaling.

The scaling and rescaling factors have values between 0.5 and 2.0. The value O is used for carrier cancellation.

The smoothing vector is used to smooth the received frame according to the channel characteristics. This vector is updated periodically, independently of the other side, as the channel value calculation is calculated by the receiver.

Depending on the specific transmission characteristics of the carrier, it will be assigned one of the following modes: - normal carrier - this carrier transmits data according to the calculated bit charge value and is "transmitter scaled" and "receiver scaled"; - canceled carrier - no energy is transmitted on this frequency the scaling vector is therefore set to zero; or - poor carrier; SNR is too low to transmit any data and the bit charge is therefore set to zero.

In carrier mode 1 (CM1), the system operates normally.

The receiver continuously equalizes the channel.

Equalization changes are made for each new value calculation. Using the characteristic, the SC calculates the optimal bit charge factor. This value is transmitted to the transmitter using CCH, and a synchronous change is made.

In carrier mode 2 (CM2), the energy scaling / rescaling value is set to 0 to disable all out / in energy. The value of the bit charge vector is also set to zero to indicate that the carrier is set out of the position of LJ: 10 20 IJ UI 30 506 636 57. No channel value calculation can be made for this carrier.

In carrier mode 3 (CM3), the receiver has calculated a zero for the bit charge factor. On the transmitter side, this means that no data can be transmitted, and therefore no channel value calculation can be made at the receiver. To avoid this, the corresponding carrier value is transmitted from the synchronization frame and makes it possible to perform a channel value calculation at the receiver. The scaling / rescaling value can be used to lower the output power.

The carrier modes are presented briefly in Table 4.

The basic functionality of the "startup" sequence in the system, ie "cold" and "warm" boot, will now be treated.

Initially, the power supply in the system is considered to be switched off at one or both ends, NU and NT. This occurs if the power supply is lost due to a power failure, or by the user disconnecting (unplugging) the NT equipment. The most important thing to take into account when starting up is, in addition to the connection function, to minimize the level of interference for other modems that use adjacent cables.

The different frame types used by the system are discussed below. l. The synchronization frame is used for channel value calculation. This frame maintains a specific modulation pattern for each carrier and thus enables easy channel value calculation. By having the modulation pattern described by a random sequence, the cross-correlation within the frame is kept low, so that the frame correlation used for synchronization is improved. 10 h) KJ! 58 2. Data frame 1, (DF1), transmits 'random data' on all carriers, except on four predefined carriers which transmit the control channel (CCH) in parallel. It is used at start-up when the CCH carrier is indeterminate and enables the receiver to select the least disturbed carrier, thereby guaranteeing the CCH connection. Data frame 2 (DF2) transmits "random data" on all carriers except one, which carries the control channel (CCH), which is used when the CCH carrier has been determined and the bit load factors have not yet been set.

(DF3) bit load function to maximize bandwidth. Data frame 3 conveys data and uses A carrier is always dedicated to the control channel (CCH).

The system uses a special frame sequence, shown in Figure 26, at start-up and in idle mode, called the Start-Up Sequence (SUS).

SUS can be composed by using the different .a data frames, DF1 and DF2, which are consequently called SUS1 and SUS2. The SUS frame sequence uses the synchronization frames for channel value calculation.

After start-up, the synchronization frames are replaced with data frames, as shown in Figure 27, and the channel value calculation process shifts from the use of the synchronization frames to the use of the data frame. The type of data frame for this sequence is DF3.

At system startup, neither side of the modem, NOW and NT, sends any energy across the copper pair.

The default setting for each side is at this stage to drive the receiver, leaving the transmitter "dead".

The receiver tries, on each side, to perform a frame correlation to detect a frame start. This correlation is run through a threshold function which gives the receiver a distinct indication of when the other side starts transmitting. It is this indication that serves as a "wake-up" signal.

The “wake-up” signal is used only by the NT side. If the start-up decision is made on the NU page, the system goes directly to the set-up sequence described below.

This part of the start-up procedure is subjected to "time out" if a transition to the set-up sequence is not detected.

The basic wake-up signaling for the modem is shown in Figure 28. Initially, both modems search for frame correlation. One of the modems, on the right in Figure 28, sends a "wake-up" signal in the form of a SUSI. The second modem detects frame correlation and starts the set sequence described below.

When the wake-up state has passed, the web page (NOW) initiates the set-up sequence.

The set-up sequence will now be processed. This set-up sequence starts after the web page has detected a wake-up signal, or the network initiates the set-up.

The first step in the setup sequence is shown in Figure 29. In this phase, NOW starts to send the SUS1 pattern. NOW repeatedly sends a timing advance (TA) setting, with TA = 0, on the CCH. The master clock in the system is now the NOW transmitter frame and the sample clock in NOW.

The pilot is sent continuously.

The NT receiver side, which looks for frame correlation, detects frames and can retrieve the frame and sample clock. It now starts the channel value calculation which at the current speed of synchronization frames makes an accurate value calculation within 300 ms. Using 506 636 10 30 60 this value calculation, the receiver starts polling the predefined CCH carriers and, at "message receive", selects this carrier for the CCH. The NT transmitter now starts with TA = 0 for local synchronization and sends receipt (acc.) on the CCH carrier for each received TA selection message, repeating the received TA value, it also shifts the outgoing pilot with BSI / 2 from the incoming pilot, so that the SC charge is distributed over time. detects the frame correlation, the transition to step 2 of the set sequence is made.

Thus, step 1 of the set-up sequence begins with the transmitter, in the network modem, transmitting a SUS1 and a TA message with TA = 0 at periodic intervals. Upon receipt of this, the receiver in the terminal modem will: - perform frame correlation and retrieve the frame clock; - start FFT treatment; enable pilot decoding; - recover the BSI; enable channel value calculation; - select a CCH; and - decoding the TA selection message.

The transmitter in the terminal unit then sends a receipt (ack), SUS1, a TA = O message and a pilot shifted by BSI / 2. The receiver in the network unit is waiting for frame correlation.

Step 2 in the set-up sequence, see Figure 30, begins with the NU page now calculating a “timing advance” value (TA). the value.

The CCH message changes to the new, corrected TA-2 IQ KJ! O 506 636 61 When the NT page receives the new TA value, it changes the local synchronization and continues to send the acknowledgment message, with a new TA value, for each TA selection message.

In the NOW receiver, the frame clock is lost, depending on that and the device After the frame clock has been recovered, the CCH is decoded and, at the acknowledgment NT transmitter, the changing frame clock needs to recorrelate. detection, which contains the new TA value, the system terminates the TA message and goes to the third step of the set sequence.

Thus, step 2 of the set-up sequence starts with the transmitter in the network unit, NOW, sending a TA message containing the correct TA, say X, SUS1, in response to SUS1 and TA = being transmitted from the transmitting terminal. together with an O message as the Terminal Unit, NT: - receives the new TA message; - corrects the outgoing frame clock; and - sends a receipt SUS1 and TA = X.

The network unit, NOW: - performs frame correlation; - retrieves the frame clock; - starts FFT data processing; - enables pilot decoding; - recovers the BSI; - enables channel value calculation; 506 636 62 - selects a CCH; and - decodes the message.

The last set-up sequence, step 3, see Figure 31, handles the CCH selection for uplink and downlink. For the uplink, the NU receiver has selected the most suitable carrier and sends a CCH message containing this selection to the NT page. The message is sent repeatedly until it receives a receipt (acc.).

On the NT side, the receiver decodes the CCH message and terminates SUS1 and transmits a SUS2, ie terminates parallel CCH transmission by transmitting only the CCH on the selected carrier.

The uplink CCH carrier has now been configured. For the downlink, the same step is performed in parallel, initiated through the NT page after receiving the first CCH selection message from NOW.

Thus, in step 3, the network unit will: - send the selected CCH for the uplink; - wait for a receipt; and - exit the CCH message.

The terminal unit: receives the CCH selection for the uplink; terminates SUSI; starts SUS2; and acknowledges each CCH selection.

U: 10 20 h) UI 506 636 63 The network unit: - receives the CCH selection for the downlink; - terminates SUS1; - starts SUS2; and - acknowledges each CCH selection.

The terminal unit: - sends the selected CCH for the downlink; - waiting for a receipt; - ends the CCH message.

Once these steps have been taken, the modem has idle mode, transmitting SUS2. Using CCH, the bit charge factors can now be changed according to channel characteristics and DAS transmission can be started.

The VDSL modem can have interfaces to different network elements, depending on the physical location of the modem, ie in the space for access nodes or in customer premises. In the customer premises, the VDSL modem can interface with an active night termination equipment. At the access node, the VDSL modem will interface with an access-specific interface, see Figure 32, which shows a logical view of the network elements that interface with the VDSL modem.

The VDSL modem can be physically integrated with the network termination equipment, and the VDSL modem at the access node can be physically located in the cabinet in which the access node is located.

NT (interface A1) and the access node (interface A2) require a layer 1 frame format of the VDSL modem. Integrated in the layer 1 frame, apart from the frame head and the payload, there are a number of information fields for handling and control information. These handling and control fields include various alarm indicators, such as SDH alarms, e.g. AIS (valid only if SDH is taken all the way to customer premises) measurements of bit error rate for performance monitoring, indications of whether synchronization is poor, or lost, equipment management alarm for loss of power supply and too high temperature etc. Management fields also include activation of various loop tests on the modem , for operation 10 and maintenance purposes. 506 636 65 TABLE l System parameters for the overall system Orthogonality between modems No Duplex method Separate bands Frequency intervals between up- Depending on duplex filter / down data flow characteristic Net bit rate, - upstream 2 Mbit / s - downstream 13 or 26 Mbit / s - upstream Coding dependent - downstream Coding dependent Cable length <1300 meters Cable bandwidth 10 MHz Modulation, single carrier - upstream O-4096 QAM - downstream 0-4096 QAM Number of carriers, a total of 1024 Bandwidth for each carrier 9, 77 kHz 128 Cycling (Cycling) DMT Access technology VDSL Signal power -60 dBm / Hz 506 636 66 Bit error rate 104 Interleaving delay 0.5 ms (Interleaving delay) System margin 6 dB CCH - bandwidth 1 carrier, minimum 16 kbit / s - protocol HDLC Sample clk 20 MHz il0ppm Frame clk 20 MHz (2048 + 1l2) = 9.19 kHz 506 636 67 TABLE 2 System parameters for the Transmitter Interleaving - depth 2 x frames - delay 0.5 ms DAC resolution 84 dB Cutting gs-algorithm No (Clipping algorithm) IFFT - type Real - points 2048 - resolution 16 bit LP filter LP 10 MHz Bit charge Yes, 0, 2, 4, 6, 8, 10, 12 bit Energy charge Yes, 4 bit BSI distance 1 s 506 656 TABLE 3 68 System parameters for the Receiver ADC resolution 66 dB FFT - type Real - points 2048 - resolution 16 bit LP filter LP 10 MHz Synchronization - jitter <0.5 ns VCXO i25 ppm, lOppm / V sensitivity - DAC 18 bit, range O-5 V - resolution 1/100 of a sample 506 636 69 TABLE 4 Carrier mode Mode Sent Bit charge Smoothing Scaling CM1 Data 2 - 12 Yes Yes cM2 No o No o CM3 Sync info O Yes, sync Yes, low

Claims (26)

506 636 W N 70 PATENT REQUIREMENTS A receiver for use in a multi-carrier transmission system using orthogonal carriers, in which a receiver sampling clock is synchronized with a transmitter sampling clock by phase locking said receiver sampling clock to a pilot carrier, characterized in that said receiving receiver includes: frame synchronization by using a frame synchronization deviation signal to control an oscillator device arranged to produce said receiver sampling clock; and - a second feedback loop arranged to compensate for channel effects by using a signal representing an argument value calculation of said pilot carrier to control said oscillator device. A receiver according to claim 1, characterized in that said oscillator device is a VCXO. A receiver according to either claim 1, or claim 2, characterized in that said multi-carrier transmission system is a DMT transmission system. A receiver according to any one of the preceding claims, characterized in that said multi-carrier transmission system is a DMT-based VDSL system. A receiver according to any one of the preceding claims, characterized in that said receiver includes a correlation device connected to a peak position estimator device arranged to produce said frame time synchronization deviation signal. A receiver according to any one of the preceding claims, characterized in that said receiver includes a pilot argument value calculation device arranged to produce said signal representing said pilot argument value calculation. A receiver according to claim 6, characterized in that said top position value calculation device and said pilot argument value calculation device are each connected to a feedback control device which is connected, via a D / A, to said oscillator device. A receiver according to claim 7, characterized in that said feedback control device comprises two feedback control devices whose output is summed to produce a control signal for said oscillator device. A receiver according to any one of the preceding claims, characterized in that said signal representing said pilot argument value calculation acts as a smoothing parameter and causes said oscillator device to be adjusted in a manner that compensates for channel effects. A receiver according to any one of the preceding claims, characterized in that said receiver operates according to a synchronization process having the following components; 726 frame alignment by adjusting said oscillator device in response to a frame synchronization deviation signal; equalization by adjusting said oscillator device in response to said signal representing said pilot carrier argument; and - only after an "establishment period" has ended, adjusting said oscillator device in response to said signal representing said pilot carrier argument value calculation. A receiver according to any one of the preceding claims, characterized in that said signal representing said pilot carrier argument value calculation is used to compensate for time variations in channel characteristics of a channel over which said pilot carrier is transmitted. A receiver according to any one of the preceding claims, characterized in that a monitoring device is provided for monitoring frame synchronization deviations and for initiating resynchronization if said frame synchronization deviations exceed a large predetermined value. A transceiver, including a transmitter and a receiver, characterized in that said receiver is a receiver according to any one of the preceding claims. A multi-carrier transmission system using orthogonal carriers, in which a receiver sampling clock is phased to a pilot carrier, characterized in that said multi-carrier transmission system includes two transceivers according to claim 13. In a multi-carrier transmission system, in which a transmitter and a receiver are synchronized by means of a pilot carrier transmitted by said transmitter to said receiver, a method of retrieving, at said receiver, said transmitter's sampling clock from said pilot signal and synchronizing said transmitter with said receiver. , characterized by the steps of: retrieving a frame synchronization deviation signal; - using said frame synchronization deviation signal to align a received frame structure with a transmitted frame structure; and - retrieve a value calculation from said pilot carrier argument and use it as an equalization parameter to compensate for channel influence. A transceiver, a multicarrier transmission system, or a method according to any one of claims 13 to 15, characterized in that said multicarrier transmission system is a DMT system. A transceiver, a multicarrier transmission system, or a method according to claim 16, characterized in that said multicarrier transmission system is a DMT-based VDSL system. 18. In a multi-carrier transmission system using orthogonal carriers, in which a receiver sampling clock is synchronized with a transmitter sampling clock by phasing said receiver sampling clock to a pilot carrier as ßw-vu fi. 506 636 74 is transmitted by said transmitter, a method of synchronizing said receiver's sampling clock to said transmitter sampling clock, characterized by the steps of: - Aligning said receiver's frame synchronization by using a frame synchronization deviation signal to control; and - compensating for channel effects by using a signal representing an argument value calculation of said pilot carrier to control said receiver's sampling clock. A method according to claim 18, characterized in that said multi-carrier transmission system is a DMT transmission system. A method according to either claim 18, or 19, characterized in that said multi-carrier transmission system is a DMT-based VDSL system. 25 A method according to any one of claims 18 to 20, characterized in that said frame synchronization deviation signal is obtained, by correlation, from a stream of received time domain data. 30 A method according to any one of claims 18 to 21, b: UI characterized in that said frame synchronization deviation signal is added to said signal representing an argument value calculation of said pilot carrier to produce a receiver sampling clock control signal_UI 506 636 75 A method according to any one of claims 18 to 22, characterized in that said signal representing said pilot argument value calculation acts as a smoothing parameter and causes said oscillator device to be adjusted in a manner that compensates for channel effects. A method according to any one of claims 18 to 23, characterized in that said method includes the following components: frame direction, between said receiver and said transmitter, by adjusting said receiver's sampling clock in response to a rate synchronization deviation signal. smoothing a channel over which said pilot signal is transmitted by adjusting the sampling clock of said receiver in response to said signal representing said pilot carrier argument; and - only after an "establishment period" has ended, adjusting the sampling clock of said receiver in response to said signal representing said pilot carrier argument. A method according to any one of claims 18 to 24, characterized in that said signal representing said pilot carrier argument value calculation is used to compensate for time variations in channel characteristics in a channel over which said pilot carrier is transmitted. A method according to any one of claims 18 to 25, 506 636 76 characterized in that said frame synchronization deviations are monitored and that initiation of a resynchronization takes place if said A frame synchronization deviations exceed a large predetermined value.