SE506644C2 - Channel value calculating and equalisation system for use in multiple carrier wave system - Google Patents

Abstract

The modifying auxiliary device is used to modify the compensation parameters in small stages so that an equalisation auxiliary device converges in the inverted channel model. An output signal (U) from the auxiliary device is fed to a detector/quantifying auxiliary device, and an output signal (Y) from the detector/quantifying auxiliary device is fed to a first input on the modifying auxiliary device. An output signal (EQ) from the modifying auxiliary device is fed to the compensating auxiliary device. The output signal, Y, is fed to a symbol decoding auxiliary device which produces a decoded data flow. The modifying auxiliary device is operatively connected to a variance value calculating auxiliary device, which is arranged to produce a signal (W) which indicates an interference variance on each of the carrier waves in the multiple carrier wave system.

Description

Since interference between pairs in copper pair cable is higher where data is transmitted in both directions, ie symmetrical duplex, the use of asymmetric solutions in which high data rates are transmitted only in one direction has been proposed for a number of transmission proposals. Such solutions meet many of the requirements for high bandwidth services, such as video-on-demand, but in the long run symmetrical duplex systems will be required.

VDSL technology is very similar to ADSL, although ADSL has to provide much greater dynamic ranges and as a result is much more complex. VDSL is lower in cost and lower in energy (lower in power), and VDSL units in real estate (premises) need to implement an access control for media in the physical layer for multiplexing upstream data.

Four line codes have been proposed for VDSL: - CAP; a version of QAM with suppressed carrier, AM / PM, for passive NT "carrierless" configurations, CAP would use QPSK upstream and a type of TDMA for multiplexing (although CAP does not exclude a solution with FDM for upstream multiplexing ); - DMT; Discrete Multi-Tone, a multi-carrier system that uses discrete Fourir Transforms to create and demodulate individual carriers, for passive NT configurations; DMT would use FDM for upstream multiplexing (although DMT does not exclude a TDMA multiplexing strategy); UI 10 25 30 (fl CD Ö \ O \ ¥> 4> - DWMT; Discrete Wavelet multitone Multi-Tone), a multi-carrier system that uses (Discrete Wavelet "Wavelet transforms" (Wawelet transforms) to create and demodulate individual carriers; DWMT also uses FDM for upstream multiplexing, but also allows TDMA; and - SLC; four-level baseband signaling Simple Line Code, one that filters the baseband and resets it at the receiver, for passive NT configurations; it is likely that SLC will use TDMA for upstream multiplexing, although FDM is possible.

Early versions of VDSL will use frequency division multiplexing to separate downstream from upstream channels, and both of these from POTS and ISDN. Echo quenching may be required for later generations of systems with symmetric data rates. A fairly large distance, in frequency, will be maintained between the lowest data channel and POTS to enable very simple and cost-effective POTS line splitters. Normal use would place the downstream duct above the upstream duct. However, the DAVIC specification reverses this scheme to enable the distribution of VDSL signals over coaxial cable systems in buildings.

Modern multi-carrier technology using orthogonal carriers with high order QAM constellations for the transmission of a plurality of bits per carrier and symbol, uses some method to determine an inverse anal model to be used in a smoothing / adaptation process ( equalization). In the frequency plane 506 644, this is normally based on a value calculation of the channel attenuation and the phase for each carrier.

An object of the present invention is to provide a simplified equalization method which uses data at the symbol detector input (input) and the output (output) to in an adaptive manner calculate the value of an inverse channel model.

Another object of the present invention is to provide a simplified channel value calculation and equalization system that uses data in the symbol detector measurement and output to adaptively value a reverse channel model.

Another object of the present invention is to provide a multi-carrier transceiver that includes a simplified equalizer that uses data in the symbol detector input and output to adaptively value a reverse channel model.

According to a first aspect of the present invention, there is provided a channel value calculation and equalization system for use in a multi-carrier system, arranged to adaptively update equalization parameters in channel model, characterized in that modification aids are provided in the frequency plane of an inverse step to modify an equalization aid converges in said inverted channel model.

In use, an output signal, U, from said equalization aid may be supplied to a detector / quantization aid, an output signal, Y, from said detector / quantization aid may be supplied to a first input of said modification aid, and an output signal, EQ, from said modifying aid can be fed to said leveling aid.

In use, said output signal, Y, can be fed to a symbol decoding aid adapted to produce a decoded data stream.

Said modification aid may be operatively connected to variance value calculation means adapted to produce a signal, W, which indicates a variance of interference on each carrier in said multi-carrier system.

Said modification aid can work with an algorithm defined by: .U as = nok + ___ .EQVUKÉ (Yk- Uk) [Uklz where p is a positive constant Ip << 1) to determine successive values of said;: equation; parameters .

I 2 The expression p / | Uk in the algorithm can be replaced by: 2-integer (2.log IUM), integer fl and p) zz The exponent: -integer (2.log2 | Uk |) + integerílogzp) can be produced by using an absolute value of Uk as an input value to a binary priority encoder and negate an output thereof.

Multiplicative operations in said algorithm can be implemented by means of a barrel shifter (barrel shifterš. 506 644 20 30 A value of the interference variance of each carrier in said multi-carrier system can be value calculated using a standard method of integrating squared deviations from an average value, in which each quantized value, Y, is used as an average value for a range of data values, U, which is quantized to Y.

A value of the interference variance for each carrier in said multi-carrier system can be valued using an algorithm defined by: WN = (1-s) .wk + s. | Yk_Uk | 2 in which integration is simulated by means of an exponentially weighted averaging filter and 8 is a small positive constant (8 << 1).

According to a second aspect of the present invention, there is provided a modem, for use in a multi-carrier system, characterized in that said modem includes such a channel value calculation and equalization system as stated in the preceding paragraphs.

According to a third aspect of the present invention, there is provided a transceiver, for use in a multi-carrier system, characterized in that said transceiver includes such a modem as stated in the preceding paragraph.

Said multi-carrier system may be a DMT VDSL transmission system that uses discrete Fourier transform to create and demodulate individual carriers.

According to a fourth aspect of the present invention, there is provided a DMT VDSL transmission system using discrete Fourier transform to create and demodulate individual carriers, characterized in that said DMT VÉSL Un 20 506 644 transmission system includes at least two transceivers as set forth above.

According to a fifth aspect of the present invention, there is provided a method of adaptively updating equalization parameters in the frequency plane of an inverse channel model in a multi-carrier system, characterized in that said equalization parameters are modified in small steps so that equalization converges in said reversal channel.

A signal, U, representing equalized data, can be transmitted to a detector / quantization aid using an output signal, Y, from said detector / quantization aid, together with said v11 signal, U, to obtain estimators, EQ, for said equalization parameters.

Said output signal, Y, can be transmitted to a symbol decoding aid adapted to produce a decoded data stream.

A signal, W, indicating an interference variance of the respective carrier in said multi-carrier system, can be obtained from said output signal, Y, and said signal, U, representing smoothed data.

Successive values of said equalization parameters can be calculated from an algorithm defined by: .EQwUkÉ (Yk- Uk) EIQk _-_ = EQR + Uklz (p << l). where p is a positive constant The expression p / ÉUKP in the algorithm can be replaced by: 2 -integer (2.log §uk |) + intege fi log p) 2 z 506 644 20 The exponent: -integer (2.log2 | Uk |) + integer (log2p) can be produced by using an absolute value of Uk as an input value to a binary priority encoder and negating an output thereof.

Multiplicative operations in said algorithm can be implemented by means of a barrel shifter.

A value of the interference variance of each carrier in said multi-carrier system can be value calculated using a standard method of integrating squared deviations from an average value, in which each quantized value, Y, is used as an average value for a range of data values, U, which is quantized to Y.

A value of the interference variance of each carrier in said multi-carrier system can be value calculated by means of an algorithm defined by: I 2 Wk + l = (l "8) .wk + 8. | Yk_Uk in which integration is simulated using an exponentially weighted mean value formation filter, and 8 is a small positive constant (8 << 1).

Embodiments of the invention will now be described, by way of example, with reference to the accompanying figures, in which: Figure 1 shows, in schematic form, an asymmetric communication system.

Figure 2 shows, in schematic form, a DMT system.

Figure 3 shows, graphically, the channel separations used in an asymmetric DMT transmission system. U: 20 Ia) UI 506 644 Figure 4 shows, in schematic form, the cornerstones of a multitone carrier system modem contemplated in the present invention.

Figure 5 shows, in schematic form, a partitioning of the multitone carrier system modem shown in Figure 4, which is used to facilitate implementation.

Figure 6 shows, in graphical form, spectral allocation for copper pairs.

Figure 7 shows, in schematic form, the frame structure used in the multitone carrier system described here.

Figure 8 shows, in schematic form, the analog interface of the multitone carrier system modem shown in Figure 4.

Figure 9 shows, in graphical form, the dependence of the signal-to-noise ratio (SNR ratio) on frequency in the multitone carrier system described here.

Figure 10 shows, in schematic form, the FFT algorithm used in the multitone carrier system modem shown in Figure 4.

Figure 11 shows, in schematic form, the frame correlation principle used in the multitone carrier system modem shown in Figure 4.

Figure 12 shows, in schematic form, implementation of a correlator used in the multitone carrier system modem shown in Figure 4.

Figure 13 shows, in schematic form, the averager used in the correlator of Figure 12. 506 U: 20 25 644 10 Figure 14 shows, in schematic form, a correlation position detector used for the multitone carrier system modem shown in Figure 4.

Figure 15 shows, in schematic form, an overview of the synchronization unit used in the multitone carrier system modem shown in Figure 4.

Figure 16 shows, in schematic form, an overview of the FFT / IFFT unit used in the multitone carrier system modem shown in Figure 4.

Figure 17 shows, in schematic form, the use of a cyclic prefix.

Figure 18 shows, in schematic form, a "decision directed" channel value calculation and smoothing system for use in the multitone carrier system modem shown in Figure 4.

Figure 19 shows QAM coding for b = 6.

Figure 20 shows, in schematic form, the realization of the calculation of bit charge and energy charge factors used in the multitone carrier system modem shown in Figure 4.

Figure 21 shows, in schematic form, an overview of the system controller interface used in the multitone carrier system modem shown in Figure 4.

Figure 22 shows, in schematic form, the manner in which two of the multitone carrier system modems shown in Figure 4 are interconnected to create a multitone carrier transmission system.

Un 10 20 k) LI: 30 506 644 ll Figure 23 shows, in schematic form, the vector management system used in the multitone carrier system modem shown in Figure 4.

Figure 24 shows BSI length.

Figure 25 shows, in schematic form, NU SC load distribution for BSI interruptions for the multitone carrier system modem shown in Figure 4.

Figure 26 shows the SUS pattern of the multitone carrier modem shown in Figure 4.

Figure 27 shows the DAS pattern in schematic form, for the multitone carrier modem shown in Figure 4.

Figure 28 shows, in schematic form, “wake-up” signaling for the multitone carrier system modem shown in Figure 4.

Figures 29 to 31 show the set-up sequence of the multitone carrier system modem shown in Figure 4.

Figure 32 shows, in schematic form, a network overview of a network interface for a VDSL modem application.

To facilitate the understanding of the present invention, a list of abbreviations used in this patent application is presented below.

ADC: Analog-to-Digital (A / D) Converter (Analog-to-Digital Converter) AIS: “Alarm In Signal” ASIC: Application Specific Integrated Circuit 506 644 20 30 BPSK: BSI: BSI-D : BSI-U: CCH: CM1: CM2: CM3: CP: DAC: DAS: DF1: DF2: DF3: DMT: DWMT: 12 Binary Phase Shift Keying BSI for Downlink Connection BSI for downlink connection BSI for uplink connection Control channel 1; bit-loaded and used carrier (Carrier mode 1, bit ~ loaded and used carrier) Carrier mode (mode) 2, (removed) masked or worn carrier (Carrier mode 2, masked out or disabled carrier) Carriage type (mode) 3, carrier arranged for zero bit charging, (Carrier mode 3, zero bit-loading enabled carrier) Cyclic Prefix Digital-to-Analog (D / A) converter (Digital-to-Analog converter) DF3 frame sequence (DF3 frame sequence) Data frame, random (random) data parallel CCH, (Data frame, random data parallel CCH) Data frame, random data one CCH (Data frame, random data one CCH) Data frame, fully bit loaded one CCH (Data frame, fully bit loaded one CCH) Discrete multiton ( Discrete Multi-Tone Discrete Wavelet Multi-Tone WUX 30 EMC: FBC: FEXT: FFT: FTTN: Gl MUSIC: G2 MUSIC: G3 MUSIC: IFFT: IIR: ISDN: ISI: JTAG: LEX: LP: NT : 13 Electro Magnetic Compatibility Electro Magnetic Compatibility Forward Error Correction End Cross Talk "Fast Fourier Transform" Fast Fourier Transform Fiber To The Node First generation, prototype system (VME-based) (Generation one, prototype system VME-based) Three + two, ASIC implementation (Three + two ASIC implementation) Two chips' silicon implementation (Inverse Fas: Fourir Transformation) Infinite Impulse Response International Standard for Digital Networks Inter-Symbol Interference Joint Test Action Group Local Exchange Low Pass Network Termination Network Termination 506 644 20 N OFDM: ONU: PGA: POTS: QAM: SC: SDH: SF: SNR: STB: SUS: SUSl: SUS2: TA: TDMA: UTP: VCXO: VDSL: 14 Orthogonal Frequency Division Multiplexing Optical network (works) unit ( Optical Network Unit) Programmable understand Progammable Gain Attenuator Conventional Plain Old Telephony Service Quadrature Amplitude Modulation System Controller Synchronous Digital Hierarchy Synch Frame Sync Frame to Signal to Interference Ratio -Noise Ratio) Set Top Box Synch Frame Sequence SF and DFI Frame Sequence SF and DF2 Frame Sequence SF and DF2 Frame Sequence Time Advance Multiple Access with Time Division Multiple Access (Unshielded Twisted Pair) Voltage Controlled Chrystal Oscillator Very high bit-rate Digital Subscriber Lines 15 506 644 The system to which the present invention relates, (Multi-carrier System for the Installed Copper Network - referred to for simplicity as "MUSIC" Multi-carrier system for the installed cup network). MUSIC is intended to provide high-speed communication on copper pair cable for telephony to support broadband multimedia services.

(SE 9603197-6) and the patent specifications arranged in cross-reference SE 9603187-7, SE 9603188-5, SE 9603189-3, SE 9603190-1, SE 9603191-9, SE 9603192-7, SE 9603193-5, SE 9603194- 3, SE 9603195-O, SE 9603196-8 and SE 9603198-4, offers a cost-effective and robust customer implementation with silicon, the MUSIC system described in this which provides 26: 2 or 13: 2 Mbit / s asymmetric transmission over copper cable ( local telephone networks.

The MUSIC system can be accessed using it (Fiber To which is each a network concept known as Fiber to the Node The Node = FTTN), serves many users, up to a control cabinet in which uses optical fiber, the proximity of the users' homes. Thus, the cable length specification for MUSIC can be successfully limited to 1300 meters.

The MUSIC system is mainly intended for transmitting a high bit rate (26 Mbit / s) signal downstream to the subscriber, and a low bit rate (2 Mbit / s) signal upstream, from the subscriber.

Figure 1 shows the MUSIC system. A network device, NOW, is connected to the fixed network through an optical fiber link, (FTTN). A network termination, NT, connected to a multimedia application, e.g. video-on-demand, is linked to the NOW via copper cable. The MUSIC system supports a high data rate downstream and a much lower data rate upstream. 506 644 10 IS 20 30 16 In the MUSIC system described here, two fixed bit rates are supported (l3: 2 and 26: 2 Mbit / s), the lower bit rate l3: 2 Mbit / s can be implemented as one where the extra option for use in case of poor, or extremely long, copper cables.

For network termination (NT), the connection consists of POTS, ISDN, ATM25 and Ethernet. All transmission protocols are supported by a set of standardized interfaces, (carried by) the data flow in the modem, except the POTS service which is filtered out passively, so that it is independent of the Network Unit (NOW) modem status. terminates in the fixed network.

MUSIC separates up and downlink spectra by passive filtering in the analog parts.

The version of MUSIC described here is intended to provide the opportunity for future functional upgrades. For this reason, the FFT / IFFT block is designed to support full functionality so that it can be reused in future system upgrades.

The MUSIC system is a DMT-based, multi-carrier VDSL system that uses discrete Fourier transform to create and demodulate individual carriers. This is shown showing two transceivers each having an Rx twisted copper pair. Data is transmitted between the two transceivers in Figure 2, a receiver, and a transmitter, Tx, connected to one using a plurality of carriers, some of which may not be used, e.g. when the channel quality is extremely poor. The number of bits transmitted by each of the carriers can also vary, depending on the channel quality.

A multi-carrier modulation technology such as DMT handles frequency-dependent losses and interference on twisted pair cable efficiently. In the MUSIC system, the available bandwidth of 10 MHz is divided into 1024 carriers with W 506 644 17 a width of 9.77 kHz each. The assigned transmission power for the individual carriers depends on the interference power and the transmission losses on each of the belts. Each carrier transmits multilevel pulses that can represent up to 12 bits of data (4096 QAM). The signal / noise ratio (SNR) of the individual carrier is calculated on the receiving side. If a carrier has a high SNR, up to 12 pieces are placed on this carrier. For carriers with lower SNR values, fewer pieces are placed on the carrier. Carriers that are affected by narrow-band sources of interference are switched off. Forward error correction and data interleaving are used to mitigate the effects of temporary bursts of impulse interference.

Asymmetric VDSL is implemented in this version of the MUSIC system, which means that the downstream speed is much higher than the upstream speed. The selected two-speed (26/13 Mbit / S) selected speed depends on the current cable length (<13000 downstream speeds supported by the system; the m) and / or the quality of the channel. The upstream speed is fixed at 2 Mbit / s. Different frequency bands can be used in the MUSIC system to separate the downstream channel from the upstream channel and both from POTS, see Figure 3.

Alternatively, other duplex methods can be used, e.g.

TDMA and / or a method where every other carrier is dedicated to the downstream and upstream channel.

Figure 4 shows an overview of a MUSIC modem to which the present invention relates. The most important hardware blocks are ADC and DAC, synchronization, fourir transform processing, channel value calculation / equalization, symbol mapping and detection, coding and decoding with interleaving, network interfaces and system monitors. 506 644 20 30 18 The modem can be considered in the form of four basic function blocks, namely: - the digital receiver unit; - the digital transmitter unit; - the analog input (front end); and system controller / PCI.

The analog input includes a hybrid transformer connected to an unshielded, twisted pair and POTS. On the receiver side, the hybrid is connected, via a low-pass filter, LP, a programmable gain damper, PGA, to an analog to digital (A / D) converter. A VCXO, power analog to digital converter. On the transmitter side is a voltage-controlled crystal oscillator, used to connect the hybrid to a digital to analog (D / A} converter via a low-pass filter.

The digital receiver unit includes a "fixed Fourir" transform and rescaling unit (rescaling FFT, to a synchronization unit and a channel estimator. Unit), connected, as shown in Figure 4, the channel estimator is connected via a symbol detection unit and a "deinterleaving" unit. -interleaving) and decoding unit, to a bit handling unit and thence to a network application interface.

The digital transmitter unit includes a bit handling unit which is connected to an inverted "fixed Fourir" transform and scaling unit, IFFT, via an encoding and interleaving unit and a symbol mapping unit.

The system control is connected to various functional units in the digital receiver and the digital transmitter, and to the network application interface and a computer interface, as shown in Figure 4.

The network (plant) interface connects the higher protocol level to the modem layer a ~ functionality.

This block is responsible for providing the system with data at the configured bit rate, and adds “dummy- if required. frames ”(dummy frames) The data is then channel coded and interleaved. The MUSIC system described here uses a convolutional code combined with interleaving. Using a depth with a plurality of frames, a combined frequency / time interleaving is obtained (see later in this specification).

The symbol mapping block receives input data as an integer vector. This vector is mapped into the configured constellation depending on the current bit load value. The mapping unit uses a Gray coding scheme to reduce the probability of bit errors.

A real (real) step in the IFFT block. This causes the system to scale vector multiplication is the first output power level on each carrier. The IFFT block then performs an FFT on which modulates each carrier. As a final real 2048 point inverted (inverse) input data, step is performed an address "wrap around" on the output data, where a copy of the first 128 samples is added at the end (CP). of the frame. This is called the cyclic prefix The modulated signal goes to a DAC that converts the signal with a minimum true dynamic range of 84 dB. The DAC is clocked by the system sample clock at 20 MHz. To get rid of Nyquist "ghosts", the signal is LP-filtered. The hybrid provides a balancing: interface to the copper cable. 506 644 UI W 20 25 30 20 An overview of the signal path of the MUSIC transmitter and receiver is shown in Figure 4. The transmitter part uses the same hybrid design as the receiver.

At the receiver end, the splitter / hybrid transceiver separates the frequencies used by the POTS, from 0 to 4 kHz, from the frequencies used by the system. It also extracts the low level reception signal from the combined high level transmission signal and the low level reception signal.

To reduce Nyquist effects on the signal, the received analog signal is low-pass filtered before being fed into the PCA (Programmable Gain Amplifier).

The PGA is necessary to get the best use In this system, the dynamic range must be at least 66 dB. of the dynamic range of the ADC.

After the signal is converted to digital format, the synchronization and FFT blocks receive the data.

The synchronization block generates a frame clock (for controlling the FFT buffers) and a control signal for the VCXO.

Initially, the retrieve synchronization block retrieves the frame clock from the sampled signal. The frame clock is then used to calculate the frame synchronization value calculation (frame timing estimate) and is transferred to VCXO feed back (20 MHz). controller ”. VCXO n generates the sampling clock A sampling clock that is only controlled by a “frame time estimate” is not sufficiently accurate in a DMT system.

Therefore, after the locking sequence, a dedicated pilot carrier is used to achieve a high synchronization precision on the sampling clock.

A BSI signal is also extracted from the pilot carrier.

BSI is the Base Synchronization Interval timing signal used to synchronize the CCH communication of the transmitter and receiver.

One of the new aspects of the MUSIC system is the algorithm used by the synchronization block, which is discussed in more detail later in this specification.

A 2048 point real FFT is performed on the input frames of the FFT block. After this, rescaling, which is based on the energy charge parameters, is performed before the data is transferred to the next block.

The channel value calculation and equalization is performed on the output data from the FFT block. All data frames are used to value the channel properties. These are then used to compute a bit charge vector that determines the number of bits to be transmitted on each of the carriers. This information is then transmitted to the transmitter through the upstream control channel (CCH).

In the symbol detection block, a “demapping” is performed for each carrier according to the bit-loading mask.

After unmapping, “deinterleaving” and “Forward Error Correction” (FEC) are performed on the detected bitstream.

The data is then ready for the network (plant) / application interface block after bit handling. The dummy frames are removed in this block.

At the heart point of the system, shown in Figure 4, is SC). a general purpose processor that interfaces the system controller (System Controller, SC) is against and controls the various sub-blocks using a local PCI bus. In the version of MUSIC described here, the CPU controller is programmable. An external port is provided, (on-board), to facilitate programming through a JTAG interface on the motherboard 506 644 22 The main tasks of the SC are to control system start-up and performance during runtime and to perform bit charge and energy charge calculations. communicates with the remote side of the modem through a dedicated (CCH) changes in bit / energy charge and other control channel This channel transmits data regarding system signaling.

To obtain a cost-effective product for high-volume use, the digital components of the system must be based on at least two ASIC circuits. Figure 5 shows how the system can be divided (partition) for chip design purposes.

One chip contains the FT / IFFT core. A second chip contains frame synchronization, channel value calculation and smoothing, symbol detection and symbol mapping. The analog block and the network interface block can be implemented on a third and a fourth chip, respectively.

The system parameters used by the MUSIC system described here are shown in Tables 1 to 3 attached hereto.

VDSL systems operate in the spectrum from 0 to 40 MHz.

In this band, the MUSIC system, as described here, occupies the lower 10 MHz. A number of traditional bands exist in this spectrum, see Figure 6. including POTS and some radio amateur bands. Different frequency bands are used in the MUSIC system described here to separate downstream from upstream channels. Because the MUSIC system described here uses 1024 carriers over 10 MHz, each carrier has a bandwidth allocated by the DC level and the POTS service. The last 9.77 kHz, where the first two carriers are the carrier is disabled because it is the Nyquist point.

Other carriers (on radio bands) may need to be canceled. This is primarily a matter of immunity and charisma on the balanced copper pair.

Un 10 15 20 k) Uu 596 644 23 Through passive filtering of the POTS spectrum, this service can be done independently of the MUSIC system described here, runtime status, or power supply.

There are two ways to provide ISDN services for a MUSIC modem connection. One way is to let the POTS and ISDN systems exist under the (below) MUSIC frequency bands. This can be achieved using a similar filtering process for ISDN band spectrum as for POTS. This filtering allows the service to be provided regardless of configuration.

The second way to provide ISDN is to allow ISDN to be a carrier service in the MUSIC system. This solution has the advantage in terms of spectrum efficiency. The use of 1024 carriers over 10 MHz gives each carrier a bandwidth of 9.77 kHz. The ISDN spectrum requires the allocation (150-4) /9.77 = 5, of these carriers. Depending on the channel characteristics, these five carriers must be chosen to have the best SNR in the system. For a standard connection, this gives 5 * 100 = 500 kbit / s bandwidth.

The optimal solution is therefore to use the modem as a carrier, and allocate only 64 kbit / s, compared to 500 kbit / s for the total bandwidth of the 64 kbit / s ISDN service.

The results of the attenuation and FEXT (Far End Cross Talk) measurements performed on a telecommunications operator's network showed that it is possible to achieve bit rates higher than 100 Mbit / s if the cable is shorter than 200-300 meters. For longer cables, attenuation at higher frequencies limits the maximum bit rate.

For cables of around 500 meters, 40 Mbit / s can be achieved, and for a 1 km cable, 15-20 Mbit / s is realistic. 506 644 IO 20 IQ Un 24 Another factor that reduces performance is EMC, which limits the power used. Some parts of the frequency domain may also need to be excluded.

A typical PSTN can be expected to have the following characteristics in terms of impulse disturbances: - maximum duration 250 us - median interval 67 ms - maximum peak amplitude 20 mV - the majority of the energy below 200 kHz background disturbance -107 dBm / Hz The main source for synchronization in the system is the sampling clock. The reference for the sampling clock is located on the NU page and is common to all twisted copper pairs in a secondary cable.

The sampling clock frequency is 20 MHz at 10 ppm, with a "phase jitter" of less than 0.5 ns.

The sampling clock on the NT page is phase-read to the NOW page. The logic of the reading uses the frame synchronization value calculation (frame timing estimation) in an initial stage, and then uses the pilot carrier to produce a fine adjustment of the reading. The read logic controls the frequency of a VCXO via an 18 bit dig: speech / analog converter_ The requirements for the VCXO are 20 MHz in 25 ppm range and 10 ppm / volt sensitivity. The final reading must have a precision of 1/100 sample, with a "phase jitter" of less than 0.5 ns.

The frame clock is 1 / (2048 + 128) controls the start of receiving and sending the frames. of the sampling clock and the Frame clock, which are used for both transmission and reception, differ in phase on both the NU and NT side. 20 25 30 506 644 25 The frame clock for transmission on the NT side is the master and controls the start of the signal intervals, see Figure 7.

The reception frame clock on the NT side is obtained from the hardware function for the frame synchronization value calculation and controls the start of the frame sampling period, see Figure 7.

The frame clock for transmission on the NT side is the same as the frame clock for reception, but is a TA sample earlier in phase. TA is a parameter that is measured during system start-up on the NU side and is used to compensate for propagation delay on the copper conductor. This must be done to maintain the orthogonality, across the copper conductor, for the sampled periods, both uplink and downlink. The frame clock for transmission on the NT side controls the start of the signal intervals, see Figure 7.

The frame clock for reception on the NU side is delayed by one (TA) for transmission, after the TA calculation (calculation) number of sample clock cycles in relation to the frame clock has been performed. The delay before the calculation of TA in the start-up sequence is determined by the hardware function for the frame synchronization value function (frame timing estimation hardware function) and the value is accessible to the control unit.

The frame clock for reception on the NU page controls the start of the frame sampling period, see Figure 7.

The BSI clock is used to synchronize parameter changes between the sending and receiving sides. The parameters can be, for example, bit charge, energy charge or control channel frequency. The parameters are updated by the system controller, on both sides, before the BSI clock initiates the switch for the new set-up. 506 644 lJl 20 26 The BSI clock is 1/8192 of the frame clock. The uplink BSI clock is delayed by half a BSI clock cycle relative to the downlink BSI clock.

A short pseudo-random sequence on the pilot channel is used for BSI synchronization between the transmitting and receiving sides.

The cyclic prefix is an extension of the frames added by the FFT chipset. To maintain orthogonality throughout the signaling period, the last 128 samples of the frame are copied and placed before the actual frame. This arrangement addresses issues related to interference between symbols caused by time dispersion.

It is important that the part of the signaling period that is sampled only on the receiving side overlaps a signaling period in the other direction, along the entire copper conductor. TA is used to optimize this overlap period. The maximum cable length is limited by TA = 128 samples = 6.4 us propagation delay. This corresponds to 1280 meters (if the propagation delay is 5 ns / m).

The analog interface connects the received and transmitted digital data stream at the Cl chip to the telephone line. There are also connections to the Tl chipset and the system controller for control purposes.

The analog interface is shown in Figure 8. The cable is connected to a hybrid transformer which is also linked to POTS. On the receiving side of the hybrid, the incoming signal passes through a low-pass filter and a programmable gain attenuator to an analog-to-digital converter, ADC, and from there to the C1 chipset. On the transmitter side of the hybrid, the output digital signal is converted to analog by a digital / analog converter, DAC, and goes from there via a low-pass filter LP to the hybrid transformer UI 20 506 644 27. A voltage controlled crystal oscillator, which drives both the ADC and the DAC, is connected to the sync block of the T1 chip.

An OFDM frame is a sum of sinusoidal carriers modulated in phase and amplitude and spaced in the frequency domain with a minimum of separation distance between carriers. The assumption that the symbols within the frame are evenly distributed and uncorrelated in relation to each other gives a signal in the time plane with an approximately normally distributed instantaneous amplitude. Thus, there is a small possibility that input data can interact with each other to create pulses with very high peak levels.

However, the maximum amplitude must be limited to a lower amplitude than this so that there is a sufficient number of quantization levels in the DAC to handle average signals. Although the DAC has sufficient resolution to accommodate a high peak level in the transmitter, there are limitations on the receiver side (ADC). However, the consequences on the recipient side do not have to be as serious as they may seem.

A short cable has lower attenuation in the high frequency range than a long cable, see Figure 9. This means that a temporary pulse can occur in the receiver almost unaffected by the cable characteristics. Therefore, a relatively large dynamic range is required in the receiver. However, this can be easily achieved because almost equal attenuations do not require a large dynamic range. The ADC needs to accommodate the area indicated in Figure 9 by the solid, rough, arrow-marked line.

However, the greater high frequency attenuation of long cables requires a large dynamic range.

The high frequency attenuation also means that several large peaks would be required from the transmitter to build up high amplitudes in the receiver; a case that is even less likely to occur at the ADC input (input) than individual peaks, The "free height" (headroom) can therefore be reduced and the ADC should accommodate the area marked by the rough, dashed arrow line in Figure 9 .

In summary, performance can be optimized by carefully setting the signal level at the ADC receiver depending on the cable length.

The line splitter / hybrid has two main tasks, namely to: - divide and combine telephony signal (POTS) and VDSL signal frequency bands; and - preventing the transmitted signal from appearing at the receiver on the same device by balancing the cable.

Since each transmission direction has its own frequency band, it is possible to optimize both sides in terms of their respective frequency bands to increase the overall performance.

The purpose of the low-pass filter on the input signal is to reduce aliasing effects on interference above the frequency range used.

The low-pass filter on the output side reduces the transmitted power on the "stop band". These filters can form part of the division / hybrid module_ The best commercially available ADC today is the "Analog Devices AD9042" which has a signal / noise ratio of approximately 66 dB. It is recommended that either this ADC, or one with equivalent performance, be used.

For this description, it is assumed that a DAC with 14 bit resolution is used. The FFT and IFFT algorithms are built up of 1024-point complex FFTs with data reorganization to allow the calculation of two real sequences at the same time.

Consequently, each of FFT and IFFT are effective 2048 points. The hardware realization is based on a radix-32 core that calculates the result in three “transformations” (passes), see Figure 10.

The relationship between the signal-to-noise ratio and the resolution in the algorithm can be expressed as: SNR = 22b-v-1 and v = ll The solution for b gives 17 bit resolution where b = number of bits, (number of effective radix-2 "transformations"). (based on ADC SNR), but since ADC is not the only source of analog signal degradation, 16 bit resolution in the algorithm should be sufficient to maintain the resolution throughout the system.

The VCXO generates the sampling frequency used in the NT part of the system. The control voltage is based on data from the synchronization unit. The clock frequency must be very stable and phase read to the NU reference clock to maintain orthogonality between symbols. (phase locked) To take full advantage of the dynamic range of the ADC, a programmable attenuator must be inserted before the ADC.

The attenuation level is mainly a function of the cable length and can be determined by the value for "timing advance" through the system controller.

Attenuation resolution and range, and the relationship between the value for timing advance and the attenuation level, must be determined. Equalization and variance values can also be used in the calculations for improved results.

In a DMT system, a very precise synchronization between the transmitter and the receiver, 506 IS 20 25 30 644 30, is necessary, especially when carriers are modulated with large constellations.

In the embodiment described here, a new frame synchronization method is used which is based on correlation properties built into the structure of the received signal.

On the NU side, a crystal frequency oscillator with a fixed frequency is used as a reference for generating the sampling clock. On the NT side, a sampling clock is generated by a VCXO Controlled Crystal Oscillator = Voltage that is locked in phase with the oscillator on the NU side. The VCXO is initially controlled by the frame timing value calculation.

However, the resolution of the frame synchronization value calculation is not sufficient in the present application. Therefore, a dedicated pilot carrier, after a lock-in sequence, is used to achieve a very high accuracy of the sampling clock synchronization. Depending on the long symbol duration of a DMT system, interference between symbols caused by channel time dispersion can be eliminated by means of a guard interval. interval) as a prefix to each frame in the time domain. To maintain the orthogonality of the frames, the contents of each prefix are a copy of the last part of the following frame, making the frames appear to be partially cyclic.

The synchronization method used to estimate the frame synchronization uses the high correlation between a prefix and the corresponding part of a frame. By continuously correlating samples of the received signal, separated in time by the (known) frame length, the passage of a protection interval will cause a peak in the therefore correlation value calculation.

Un 50 30 646 31 31, these peaks will have a known synchronization relationship to the frames and can be used to create a frame start signal. The principle is shown in Figure ll.

The correlator and peak time estimator use a system clock generated by a VCXO. This clock is divided by (divided by) the total number of samples in a signal range (a cyclic prefix and a frame), to create a signal with the same period as the correlation peaks.

The frame time deviation between these two signals is used as input to a "feed-back controller" that adjusts the VCXO frequency to the correct sampling frequency. However, the phase of this sampling clock is not accurate enough to be used in a DMT system. Therefore, the frame synchronization value calculation is mainly used for a lock-in operation. It is also used to monitor frame synchronization to detect major anomalies that will necessitate resynchronization.

The correlation of the received data is calculated continuously. The time difference between the two signals is achieved by using a digital delay line of one frame length. The output of the delay line is multiplied by the non-delayed signal and integrated (accumulated) over an interval corresponding to the length of the cyclic prefix. The output from the integrator is the value calculation (estimate) of the correlation function.

Since only the synchronization information of the correlation value calculation is used, a simplified estimator is implemented which only uses the reduced complexity symbol of the input data compared to using it (sign). This hardware implementation has a very complete sample word length. 506 644 UI 10 20 25 30 32 Computer simulations have shown that the use of synchronous averaging of several signal intervals reduces the variance of the frame synchronization value calculation. Depending on the reduced data word length used in the multiplier portion of the correlator, it is possible to implement such an averaging function immediately after the multiplier.

A block diagram showing the implementation of the correlator is shown in Figure 12. The incoming signal X (k) passes through a delay of N = 1024, i.e. a frame, and to a conjugator. The output of the delay and the conjugator are then multiplied to produce a signal Y (k) the averaging, Z (k) goes to a subtractor from which Z (k) signal W (k) goes to an accumulator which gives an output signal C (k) . which goes to an average value generator. The output from delayed by L = 128 is subtracted. This gives a The details of the averaging part of the correlator are shown in Figure 13. The averaging comprises a series of delay elements combined with adders, as shown. The output signal can be expressed as 6 z = Z: Mk-im i = Û where Y (k) is the input signal and Z (k) is the output signal.

To make the averaging synchronous with the frame structure of the signal, the delays are equal to the signal interval.

A detector for finding the position of the maximum size of the correlation function value calculation is shown in Figure 14. It is implemented using a register (# 1) for the latest max. Value and a comparator. 20 30 506 644 33 The register contents and the correlation size are compared, and each time a value greater than the register contents is found, the new value is stored in the register. The current value of a counter that counts sampling intervals (modulo signal intervals) is also passed to a second register (# 2). this second register to contain an index to it When a whole signal interval has passed, the max. value found during this interval. This index is stored in a third register (# 3), once per signal interval, and the contents of the first register (l #) are divided by two (using shift). (using The index stored in register # 3 is interpreted as the deviation between the counter value and the current synchronization of the input signal frames. The feedback controller will cause the mean value of this deviation to converge to zero. The counter value can then be used as a pointer to the signal interval. using this counter value to indicate the frame start.

The value calculation of the complex representation of the pilot carrier in the frequency plane is performed using the FFT unit available in the system. The advantage of using this method is that the value calculation will be independent of the varying modulation of other carriers. This is due to the inherent orthogonality between the carriers. In order to achieve a value calculation with acceptably low variance, a certain average value formation is necessary. This is done using the first-order digital IIR filter.

Unfortunately, the value calculation is represented as a complex number in rectangular coordinates, so the argument is not directly available. In the feedback loop, it is (detect) necessary to: detect very small 506 644 10 15 20 h) Un 30 34 argument deviations. Therefore, the resolution of the argument must be high. The feedback controller will cause the pilot carrier argument to converge to zero. An approximation of the argument, which is linear only in a small range around zero, is then sufficient to achieve acceptable performance. A useful approximation that is "monotonic" in almost all four quadrants, and also easy to implement in digital logic, is described by the expression: A = M. [S {c} - <1-sgn9¶ {C}) .K. 9ï {c} .sgn.3 {c}] where C is the complex pilot carrier value calculation, M is a positive scaling constant, and K is a positive constant that affects the design of the function (here K = 2 is used).

The channel introduces phase shifts on the pilot carrier which can cause "misalignment" between the frame synchronization of the input signal and the pilot argument zero.

To eliminate this problem, the pilot carrier estimator also passes through the frequency domain equalizer. The equalization parameter for this carrier is set during the start sequence, when the frame timing estimate has converged to its final value.

The choice of pilot carrier will be fixed, but logic for choosing other carriers as a pilot can also be provided. The feedback loop actually has two "controllers", each with its own input signal. The two controller outputs are added and fed via a D / A converter to the VCXC which generates the sampling clock. Both "controllers" are of the PI type (Proportional and Integrating). 10 15 25 30 506 644 35 Figure 15 gives an overview of the signal paths. The received data in the schedule passes through the correlator and the peak position estimator to result in the frame clock. The complex pilot carrier in the frequency plane derived from the equalizer is fed to a pilot argument estimator, the output of which is fed to "feedback controllers" which also receive output from the peak estimator. The output of the “feedback controllers” is then passed to a D / A converter to provide a signal used to control the VCXO.

During the startup sequence, only the frame synchronization controller is active. Once the frame synchronization has stabilized, the equalization parameter for the pilot carrier is valued and set (by the SC). This is done only once, and further updating of this parameter is suppressed. After this change of equalization parameters, the averaging of the argument estimator is given sufficient setting time.

Finally, the frame synchronization controller is stopped and the pilot argument controller is activated. When the frame synchronization controller is stopped, its last value is locked so that the VCXO frequency remains close to its final value.

The pilot carrier is also used for transmitting synchronization information for the Base Synchronization Interval (ESI). The carrier argument is normally assumed to be constant.

A short pattern is BPSK modulated on the carrier using phases 0 and n and leaving the carrier on phase 0 for the remainder of the BSI interval. If this pattern is only a fraction (<1%) of the BSI interval, the disturbance of the pilot carrier argument value calculation is negligible. A correlator is used to detect the pattern and provide the synchronization signal for BSI. 506 644 Un 20 IQ lll 36 The "System Controller" (SC) must have read access, for detection of synchronization lock and for monitoring reasons, to registers which pour the estimator for frame time deviation and the pilot argument approximation.

To handle the initial smoothing of the pilot carrier, it is necessary for the SC to read the averaged complex representation of the carrier and write to the smoothing parameter memory_ An offset register to determine the relative synchronization between the input frames and the frame start signal is necessary and SC n. This is used on the NT page. for both must be connected to the SC as The detected BSI event signals, reception and transmission, interrupt inputs.

Alternatively, the pilot carrier can be recovered from the signal in the time plane, using a bandpass filter, and used directly for phase locking of a sampling clock oscillator. The frequency plan method described here has the advantage that the pilot carrier estimator is independent of the modulation of the other carriers, depending on the orthogonality. Another frame synchronization method would depend on introducing a known pattern into certain frames.

This would reduce system capacity.

The frame length and the length of the cyclic prefixes are fixed in the embodiment described here. The method, described above, is designed to operate in a feedback loop with a VCXO. In a device using a specific sampling clock oscillator, the design of the frame synchronization estimator needs to be slightly modified. It is important that the VCXO has a very low phase fault, as the feedback loop is too slow to compensate for such a fault.

W 20 25 30 506 644 37 A discrete multitone system (DMT) modulates N complex data symbols on N carriers (here we use N = 1024 carriers). This mapping is calculated as a reverse (inverse) discrete Fourir transform using Inverse (IFFT).

N st the carriers of an FFT.

Fast Fourier Transform “In the receiver they are demodulated, FFT and IFFT are performed by (radix) 16, (cores), in different phases. This process is shown in the modem, as described here, the same device, using the same base or 32 "cores" schematically in Figure 16.

The main operation is divided into frames with lengths of 2048 real, this unit performs an FFT, or 1024 complex values.

IFFT, and addition of cyclic prefix.

For each frame scaling, descaling, the FFT and the IFFT calculate 2048 points real FFTs and work: ed a minimum of 16 bit arithmetic.

(NT), synchronization between the input frame start and IFFT- For the night terminal side, there is a requirement for the output start. (A synchronization between the upstream and downstream carriers). The transmitter must be able to start transmitting a frame before it starts receiving a frame, so-called "timing advance". (scaling) should be provided before IFFT.

This scaling is a multiplication between the real A scaling coefficients stored in this unit, and the input values from the symbol mapper (SM). The coefficients are 16 bits each.

The coefficient memory consists of two banks of the same second updated. Switching is made possible by size One bank is used while a PCI command and executed at the next BSI. 506 644 UI 20 30 38 After the? FT, a rescaling must be performed before the data is transferred for smoothing and symbol detection.

This rescaling is a multiplication by the inverted value of the scaling values. The coefficients are represented by 16 bits.

An exponent (resulting in a 4-bit post shift) may also be needed to maintain precision.

The coefficient memory consists of two banks of the same size ((16 + 4) x1024 bit). others are updated. Switching is made possible by a PCI- One bank is used while the command and executed at the next BSI.

At the beginning of each frame, a cyclic prefix is added.

This process is shown schematically in Figure 17. The insertion of a cyclic prefix eliminates interference between symbols (ISI), and preserves the orthogonality between the tones, resulting in a simple input / output ratio that allows each carrier to be considered as a separate channel. .

This cyclic prefix consists of a repetition of the last part of the frame.

Provided that "timing advance" is used and the maximum cable length is 1300 m, a cyclic prefix of 128 samples will be required. Thus, the output for each row: will be samples: 1920, l92l, ..., 2046, 2047, 0, l, 2, 2046, 2047 For each of the above components there is a FIFO as an interface to the external world with FFT / IFFT input and output memories. Thus, there are a total of 4 FIFOs.

It is recommended that the FIFOs with interfaces to the analog side: have a size of 384 words (16 bits) and the FIFOs that have interfaces to Tl chips have a size of 448 words (32 bits). 20 30 506 644 39 Another DMT technology that does not use "Fourir transformation" is "Discrete Wavelet Multi-tone Transform" (DWMT). This method has been submitted to the ADSL Standardization Committee, which rejected it.

The precision required in this technology depends on what is in turn determined by (especially DAC). The FIFO size will depend on the clock speed differences and the amount of dynamic range required, the analog components "timing advance" used. The use of clipping is a compromise between dynamic range (quantization perturbations) and clipping perturbations.

Channel value calculation is performed using a "decision directed" method, as all data frames are then used to update the channel model. Known data frames are necessary only at start-up. In some circumstances, interference on the channel can be value calculated using all data frames. detection of changes in channel transmission quality.

The basic principle for “decision directed” value calculation is that differences between received data and known, transmitted data are used to update a channel model. At some stage of this process, the channel model is: accurate enough to be used to smooth the received data, and the detector will produce correct data. This output can then be used in the same way as the known data for further updating of the channel model. Therefore, the predefined data frames are no longer necessary and random data transmitted through the channel is used instead.

By using data taken after the equalizer as input data, and data after the detector as the second input data, an adaptive update algorithm can be designed. It modifies the equalization parameters in small steps in such a way that the equalizer converges towards a model of the "reverse" 50 Llu 10 20 IQ Un 30 0 644 40 (inverse) channel. Figure 18 shows a block diagram of such a system. Input in the frequency plane enters the equalizer and is multiplied by the output of an equalizer parameter update unit, EQ. The resulting signal, U, then goes to a detector (quantizer) whose output is Y. Y then goes to a symbol decoder that produces a decoded data bitstream. U and Y also go to an input on the equalization parameter updater and to a variance estimator.

The output of the variance estimator is W.

An adaptive algorithm for calculating the value of the smoothing parameters (EQ), which uses the smoothed data (U) and the quantized data (Y) as input data, is described by the following equation: FL Q EQkçl = EQK + .EQk.Uk. (Yk 'Uk) lukïz where p is a positive constant (u << 1), which affects the adaptation dynamics. A smaller value gives a slower adjustment than a larger value, but it also gives a greater insensitivity when there are disturbances on the input signals.

For implementation reasons, the division shown in the equation should be avoided. The expression u / iUkP has too large a dynamic range to be replaced by a constant. However, it is possible to quantize this expression in a logarithmic way as shown below: -integerlllog iUk | ) + integerílog u) 2 2 2 ~ ~ p / lUklz The exponent in the above expression can be produced using the absolute value of Uk as input in a binary priority encoder and change the sign (negating) of the output. IQ Un 30 506 644 41 Since the expression is an integer power of two, the multiplication is implemented in the algorithm using a "barrel shifter".

The interference variance of each of the carriers is value calculated using the standard method of integrating the squared deviations from a mean value. In this case, each quantized value, Y, is used as the mean of the range of data values, U, which is quantized: ill this Y. This method assumes that the symbol error rate is low enough for each data value to be associated with the correct mean. However, if suitable constellations are selected for the different carriers, this condition is met.

Figure 18 shows the variance estimator as part of the system. The: algorithm used for the value calculation is described by the following equation: Wk + l = .Wkj-a. lYk_Uk | 2 The integration is here replaced by an exponentially weighted average value filter. The parameter S is a small, positive constant (8 << 1) which affects the dynamic properties of the filter. This is not a critical parameter, and choosing s from integer powers of two will suffice.

If an: value of s is selected that provides a good variance value calculator (estimator), the algorithm will not be able to detect sudden changes in the interference level.

Therefore, a separate algorithm, working in parallel with the variance estimator, may be necessary for this task.

The "System Controller" must have both read and write access to the: memory that holds the equalization parameters.

Initialization of the parameters is necessary at start-up. Monitoring (monitoring) of the parameters is also necessary 506 644 20 IJ Un 42 to detect when they have leveled sufficiently close to their final values.

The channel variance memory must be available for the System Controller's read operations. Initialization of this memory to all zeros can be connected to a system reset.

The parameters that affect the dynamics of the estimators must be available for writing from the System Controller.

The method described here assumes a specific start-up sequence, both for the channel and interference value calculation. During normal execution, it is dependent on an appropriate bit charge selection that provides a sufficiently low symbol error rate.

It is important that the smoothing parameters are initialized to unit value at the beginning of the start sequence, as the input to the update algorithm passes through the equalizer.

The update algorithm is sensitive to scaling changes in the data path.

Any change in scaling in the transmitter must be compensated in the receiver. This also requires special care when using the analog gain control on the input side of the receiver.

The symbol mapper (encoder) maps a number of bits to a complex number (I, Q) the amplitude of a carrier. The mapping of all values of one that indirectly determines the phase and certain bit length is called a constellation, and is shown in figure 19. The detection is the inverse function, ie from a complex value the value of the bits sent on the carrier is determined. The number of bits transmitted on a particular carrier is determined by the bit charge factor thereof. 10 20 25 30 506 644 43 The construction of a specific constellation is aimed at allowing each point to be moved as far as possible from all other points. At the same time, the average energy should be as low as possible. Another restriction is that the mapping and detection units should be as simple as possible. However, the decision as to which constellation to use will affect not only the symbol mapping and detection units, but also the bit charge and possibly the adaptive equalizer.

For a given carrier path, the encoder selects an odd integer point (I, Q) from the square-grid constellation based on the b-bits (vb1_vb¿, __4, vLv¿). For simplicity of description, these b-bits are identified by an integer label whose binary representation is (vb1, vbQ, ___, vLv2). For example, for b = 2, the four constellation points 0, 1, 2, 3 are "labeled" corresponding to (v¿v¿) = (0.2), (0.1, (1.0), (1.1) , respectively.

For even values of b, the integer values of I and Q of the constellation point (I, Q) are determined from the b-bits (vb-i, Vb- L H_lv¿jQ) as follows. Divide V by VI = (vb1, vb¿, _H 'v¿) and VQ = (vbz path ___Iv0). Then apply the reverse Gray code to VI and VQ. This gives I and Q as I = 2GraW (VI) + I, and Q = 2Graw (VQ) + 1.

Figure 19 shows how the binary pattern for V folders on I and Q when b = 6.

Before these values are sent to the IFFT, they are normalized by shifting so that “msb” of these numbers becomes “msb” on - (b / z output __ steps left).

For a given carrier path, the decoder uses a constellation point (I, Q) to determine the b-bits (vb fl l 506 644 Un 25 N 44 vbQ, ___, vLv2). For simplicity of description, these b-bits are identified by an integer label whose binary representation is (vbl vbq ___ 'vLv2).

It is assumed that the values of I and Q are limited by saturation to the range (X, Y). To determine V, Gray encodes the values I = (iu, iu ...., iLio) f and Q = (qm, qn, ..., qLqo) f OCh is then combined into V as V = (giß, gqß , gin, gqM, .....), where the upper b-bits are valid.

The number of bits each carrier transmits depends on their respective signal-to-noise ratio (SNR).

The signal-to-noise ratio is calculated for each carrier in the receiver. Based on the signal-to-noise ratios, bit charge factors are calculated for each carrier. Thus, the number of bits each carrier must transmit per transmitted symbol is determined.

These bit load factors are calculated in an initial training session and can be updated if required.

The MUSIC system uses 2 ~ dimensional Quadrature Amplitude Modulation (QAM) on each carrier, with bit charge factors ranging from 0-12 bits.

The number of bits transmitted on each carrier can be expressed by: SNRi F where F, the SNR gap, depends on modulation, possible coding and a system margin, and L the constellation expansion depends on the extra bits needed for coding.

The use of QAM constellations and some form of coding gives: 20 l 30 30 506 644 45 P lchf-rn: r =. _ .Yd + Ymargin (dB) (2) 3 where Psär is the desired symbol error rate, yd is the “gain of coding” in the system, nßmnïär the system margin. The system margin is a factor used to compensate for non-modeled losses, impulse disturbances, etc. Equation (1) gives a bit charge factor with infinite granularity.

The bit load factors are rounded to give the supported factors (0 - 12 bits).

The rounding procedure will reduce the performance of the DMT system. If the energy distribution is allowed to vary, energy charge factors can be calculated for each carrier. This provides the ability to tune the energy so that (1) results in a bit charge factor supported by the system. Reconciliation provides: However, this can result in very large differences between carrier energies. In an environment with several different DMT systems, strange effects can occur if the different energies are allowed to vary too much.

(FEXT) such an environment, and some DMT systems can get the entire cable's Remote Crosstalk will vary considerably in a capacity. To prevent these effects, only small changes in the carrier energies can be allowed. Another limiting factor is the maximum energy allowed on each carrier. 506 644 Un 15 20 30 46 The input data to the bit load algorithm will depend on the selected frequency domain equalizer. If an adaptive DFE is used, SNR is obtained by: where Wi is the value-calculated interference variance described above.

For each carrier, a bit charge factor and an energy charge factor are calculated. The bit load factors can be represented by 3 bits, but to prepare the system even for odd bit load factors, 4 bits are recommended. For energy charging, n bit is used to give 2n - 1 possible factors.

The implementation of the calculations of bit charge and energy charge factors can be done in four steps shown in Figure 20. To achieve a given bit rate, a required SNR can be calculated and the system margin adjusted so that the desired bit rate is achieved. The process, illustrated in Figure 20, includes the following steps: - First, the SNR is calculated using (4).

In the second step, four comparisons are performed, ie one for each of the four bits representing the bit load factor.

The thresholds depend on L and F, and can be pre-calculated. The first comparison determines if the bit charge factor is greater than 7, and the result of this comparison controls the first of the four bits representing the bit charge factor; it also controls the threshold for the next comparison. Similarly, this comparison controls the second bit and the threshold for the next comparison. After the four comparisons, the bit charge factor is determined. 10 20 25 30 506 644 47 - The third step is to value the scaling factor for the transmitted energy so that the channel is used more efficiently. The energy is scaled according to equation (3).

Finally, the scaling factor is quantized to n bits.

It should be noted that in order to implement a system of constant energy charging, only the first two steps are necessary.

The energy charge and shift performed for normalization in the symbol mapping determines the scaling and rescaling factors sent to the IFFT / FFT processor.

The purpose of channel coding is to reduce bit error rates. The type of coding that should be used depends on the error pattern characteristics.

Faults caused by impulse disturbances mainly affect one or two bits per carrier. The probability of a single bit error on a carrier is always higher than the probability of 2 bit errors, which in turn is higher than the probability of 3 bit errors, and so on. This depends on the way in which the bits in the symbol are coded (ie Gray coding).

All coding depends on a synchronization to determine the start bit for the codewords and / or the "interleaving" blocks. "Simple dead reckoning" should be sufficient, since an error in data flow in a system such as the MUSIC modem will (data flow slip) can never occur without loss of frame synchronization, or error setting at 506 644 UI IO 15 20 25 30 48 bit charge. These errors necessitate a partial, or complete, system startup.

Channel coding will also include "interleaving" to increase the ability to correct burst errors.

"Interleaving" should be as deep as possible to obtain optimal function.The limiting factor in depth is the time delay introduced into the system.

The difference between time and frequency interleaving is of little importance because the coding and interleaving function is not sensitive to frame boundaries.

Reed-Solomon codes have the disadvantage that they are mainly burst error correction over a small number of bits (usually eight), a so-called symbol. Pulse errors from impulse disturbances generally introduce a “single-bit error” in some of the symbols. To take advantage of Reed Solomon codes, the most "error prone" bits must be concentrated on one, or a few, of the Reed-Solomon symbols.

The system margin as such (in itself) is a kind of coding that uses the margin of each carrier as the redundancy of the symbol. This redundancy per symbol must be converted to a "shared" larger number of symbols to handle burst errors. The higher redundancy that can be used by a coding rate that this introduces, can be used by certain types of convolutional codes.

The use of a convolutional code combined with "soft" information is therefore the optimal solution for a system with MUSIC channel characteristics.

The folding code must be combined with interleaving.

It is possible to use a "top-level" Reed-Solomon code, or any other burst error correction code, such as Fire-UI 10 20 IQ Un 30 49 codes, to detect / correct the remaining bit errors.

This is especially useful because these errors occur in bursts as a result of the decoding of the convolutional code.

The "System Controller" is based on a "micro controller", or signal processor, depending on capacity requirements, for the MUSIC system the processor can be placed externally.A PCI bus interface is used to connect the System Controller and the various ASICS that make up the modem.

The function of the System Controller is shown schematically in Figure 21, which shows the paths of interaction over a PCI bus, between the System Controller and the FFT chip, the data mapping and detection chip, and the coding and decoding chip. Functions performed by the system controller are: - control of "Control Channel Signaling"; - calculation of bit charge and energy charge factors; - updating of system parameters in real time; and - system monitoring.

The System Controller used for the modem described here is programmable and accessible through a JTAG interface on the motherboard (on-board).

As shown in Figure 22, in a modem context with modem described here, the two data paths operate independently on the same physical copper cable, terminating in the network (NU) unit (NOW) on the network side, and the network termination (NT) on the user side. Both the transmitter Tx and the receiver Rx are controlled by the System Controller.

The System Controller calculates and updates, after start-up, the bit charge and energy charge factors.

This update must be done at the same time starting from the same frame, on both the transmitter and receiver side. 506 644 UI 10 20 la) UI 30 50 The calculations are made and the update is initiated on the receiving page. The control channel, combined with the BSI clock, is used to ensure the synchronization of the update.

System Controller also monitors the system. Indications of system errors include the control channel starting to indicate errors, or receiving too many errors from the decoding channel unit.

The System Controller can initiate reboot at different levels; for example, go back to "idle mode", or do a full boot.

The control channel is a selected carrier that is only used for signaling between the two modems. The constellation on the carrier is initially 4 QAM and the data rate is approximately 16 kbit / s. The bit load can be changed to another constellation to increase the data rate.

The protocol on the s: yr channel is partly based on HDLC for the physical layer :. This means that the messages are packaged as a number of octets using "flag sequence" and "bit-stuffing". A 16-bit "frame check sequence" guarantees that each message is received correctly.

"Flag-sequence", "bit-stuffing" and "frame check sequence" are handled in the hardware on the mapping and detection chip. The contents of the messages are handled by the System Controller.

The maximum message length is limited to 64 octets depending on the size of the buffers on the mapping and detection chip.

Higher level protocols can be based in part on CCITT Q.92l recommendations.

In MUSIC modem SC several different vectors are handled; these are shown schematically in Figure 23. 20 Ix) Un 30 01 CD Ö \ O \ Jä -Ph 51 For the transmitter part there is the bit charge and energy scaling vector. Corresponding on the receiver side is the bit charge, rescaling and equalization vector.

As previously described, the pilot carrier delivers a transmitter / receiver synchronization by transmitting and detecting a specific pattern. This clock is used by the system to synchronize changes in the transmitter and receiver weights.

The time between the pilot synchronization patterns is called the Base Synchronization Interval (BSI) and is determined by the system response time, as shown in Figure 24.

This ESI is hardware dependent. Its length will not change, as the response time always remains the same.

When the system is running, there will be synchronization between: the uplink end and the receiver, (BSI-U) see Figure 25. These BSIs are of exactly through "base sync interval aplink" (BSI-D), the same length but are half shifted BSI interval. and the base sync interval downlink SC at NU n, or NT n, will receive interrupts for both BSI-U and BSI-D.

For the NOW there will be a transmission BSI-D- By switching BSI-U with BSI 2, the SC charge will be better distributed interrupt and e :: receive BSI-U interrupt_ over the BSI period.

The bit load vector provides the system with the modulation pattern for each carrier. This is a vector that needs to be maintained and updated at exactly the same time on the transmitter and receiver side to provide a faultless connection. By using the BSI, the vector changes synchronously on the receiver and transmitter side. 506 644 20 30 52 The bit charge factors, constellations used on each carrier, are handled by two memories for reception and two memories for transmission on the mapping and detection chip. Each of the four memories contains a 4-bit word for each carrier (l024x4).

The System Controller identifies which of the memories to use to send and which to use after receiving from the next BSI interval.

The bit load factor can have values between 0 and 12, where 0 indicates an unused carrier; 1-12 indicates the number of bits in the constellation (eg 2 for 4QAM, 4 for 16QAM, 10 for 1024 QAM).

The energy vector holds information on how the carriers are scaled / rescaled for energy. This is a vector that needs to be updated synchronously, otherwise it will generate a distorted channel value calculation and bit error.

The scaling vector will also be used for canceled as a pattern (mask) carriers.

Scaling of the various carriers on the transmitter side is handled by a memory area on the FFT chipset. The memory consists of a 16-bit word for each carrier (1024 x 16). These values are multiplied by the vector of each carrier in the frequency domain (I and Q are multiplied by the value separately).

The memory is doubled to ensure a synchronous update. The System Controller points out which of the two memories will be used from the start of the next BSI interval. (doubled) the receiver side to rescale the carrier waves before A corresponding memory is implemented on symbol detection. If these memories contain a complex 10 20 25 30 506 644 53 value for each carrier (32 bits / carrier), only the I value will be used for rescaling.

The scaling and rescaling factors have values between 0.5 and 2.0. The value O is used for carrier cancellation.

The smoothing vector is used to smooth the received frame according to the channel characteristics. This vector is updated periodically, independent of the other side, when the channel value calculation is calculated by the receiver.

Depending on the specific transmission characteristics of the carrier, it will be assigned one of the following modes: - normal carrier - this carrier transmits data according to the calculated bit charge value and is "transmitter scaled" and ": receiver scaled"; - canceled carrier - no energy is transmitted the frequency and scaling vector are therefore set to zero; or - poor carrier; SNR is too low to transmit any data and the bit charge is therefore set to zero. (cm) The receiver continuously smooths the channel.

In carrier mode l, the system operates normally.

Equalization changes are made for each new value calculation. Using the characteristic, the SC calculates the optimal bit charge actuator. This value is transmitted to the transmitter using CCH, and a synchronous change is made.

(CM2) / rescaling value to 0 to exclude In carrier mode 2, energy scaling (disable) is set to all out / in energy. The value of the bit charge vector is also set to zero to indicate that the carrier is set to 506 644 10 20 30 54 stand. No channel value calculation can be made for this carrier.

(CM3) zero for the bit charge factor. On the transmitter side, this means that in carrier mode 3, the receiver has calculated that no data can be transmitted, and therefore no channel value calculation can be made at the receiver. To avoid this, the corresponding carrier value is transmitted from the synchronization frame and makes it possible to perform a channel value calculation at the receiver. The scaling / rescaling value can be used to lower the output power.

The carrier modes are presented briefly in Table 4.

The basic functionality of the "startup" sequence in the system, ie "cold" and "warm" boot, will now be treated.

Initially, the power supply in the system is considered to be NU and NT. This occurs if the power supply is lost due to a power failure, turned off at one or both ends, or by the user disconnecting (unplugging) the NT equipment. The most important thing to take into account when starting up is, in addition to the connection function, to minimize the level of interference for other modems that use adjacent cables.

The different frame types used by the system are discussed below. 1. The synchronization frame is used for channel value calculation. This frame maintains a specific modulation pattern for each carrier and thus enables easy channel value calculation. By having the modulation pattern described by a random sequence, the cross-correlation within the frame is kept low, so that the frame correlation used for synchronization is improved 2. Data frame 1, (DF1), transmits "random data" on all carriers, except for four predefined carriers that transmit the control channel (CCH) in parallel. It is used at start-up when the CCH carrier is indeterminate and enables the receiver to select the least disturbed carrier, thereby guaranteeing the CCH connection. Data frame 2 (DF2) transmits 'random data' on all carriers except one, which carries the control channel (CCH). It is used when the CCH carrier has been determined, and the bit charge factors are not yet set.

(DF3) conveys data and uses the bit load function to maximize bandwidth. 4. Data frame 3 A carrier is always dedicated to the control channel (CCH).

The system uses a special frame sequence, shown in Figure 26, at start-up and in idle mode, called the Start-Up Sequence (SUS).

SUS can be composed by using the different DF1 and DF2, which are consequently called SUS1 and SUS2. The SUS frame sequence uses the synchronization frames for the data frames, channel value calculation.

After start-up, the synchronization frames are replaced with data frames, as shown in Figure 27, and the channel value calculation process shifts from the use of the synchronization frames to the use of the data frame. The type of data frame for this sequence is DF3.

At system startup, neither side of the modem, NOW and NT, sends any energy across the copper pair.

The default setting for each side is at this stage to drive the receiver, leaving the transmitter "dead".

The receiver tries, on each side, to perform a frame correlation to detect a frame start. This correlation is run through a threshold function that gives the receiver a distinct indication of when the other side starts transmitting. It is this indication that serves as a "wake-up" signal.

The “wake-up” signal is used only by the NT side. If the start-up decision is made on the NOW page, the system goes directly to the set-up sequence described below.

This part of the start-up procedure is subjected to "time out" if a transition to the set-up sequence is not detected.

The basic wake-up signaling for the modem is shown in Figure 28. Initially, both modems search for frame correlation. One of the modems, on the right in Figure 28, sends a “wake-up” signal in the form of a SUS1. The second modem detects frame correlation and starts the set sequence described below.

When the wake-up state has passed, the web page (NOW) initiates the set-up sequence.

The set-up sequence will now be processed. This set-up sequence starts after the web page has detected a wake-up signal, or the network initiates the set-up.

The first step in the set-up sequence is shown in Figure 29. In this phase, NOW starts to send the SUS1 pattern. NOW repeatedly sends a timing advance (TA) setting, with TA = 0, on the CCH. The master clock in the system is now the NOW transmitter frame and the sample clock in NOW.

The pilot is sent continuously.

The NT receiver side, which looks for frame correlation, detects frames and can retrieve the frame and sample clock. It now starts the channel value calculation which at the current speed of synchronization frames makes an accurate value calculation within 300 ms. Using Un 30 57 this value calculation, the receiver starts polling the predefined CCH carriers and, at message receive, selects this carrier for the CCH. The NT transmitter now starts with the TA = CCH carrier for each received TA selection message , 0 for local synchronization and sends receipt (acc.) On repeating the received TA value.It also shifts the outgoing pilot with BSI / 2 from the incoming pilot, so that the SC charge is distributed over time.When the NOW detects the frame correlation , the transition to step 2 of the set-up sequence is made.

Thus, step 1 of the set-up sequence begins with the transmitter, in the network modem, transmitting a SUS1 and a TA message with TA = 0 at periodic intervals. Upon receipt of this, the receiver in the terminal modem will: - perform frame correlation and retrieve the frame clock; - start FFT treatment; enable pilot decoding; - recover the BSI; enable channel value calculation; - select a CCH; and - decoding the TA selection message.

The transmitter in the terminal unit then sends a receipt (acc.), SUS1, a TA = O message and a pilot shifted by BSI / 2. The receiver in the network unit is waiting for frame correlation.

Step 2 i with the NU page now calculating a "timing advance" value (TA) The CCH message changes to the new, corrected TA set sequence, see Figure 30, the value begins 506 644 58 When the NT page receives the new TA value, it changes the local synchronization and continues to send the acknowledgment message, with a new TA value, for each TA selection message 5 In the NU receiver, the frame clock is lost, due to the NT transmitter changing (changing) frame clock, and After the frame clock has been recovered, the CCH is decoded and, upon acknowledgment detection, which contains the new TA value, the system terminates the TA message and goes to the third step of the set sequence.

Thus, step 2 of the set-up sequence starts with the transmitter in the network unit, NOW, sending a TA message containing the correct TA t, say X, together with a SUS1, in response to SUS1 and the TA = 0 message transmitted from the transmitting terminal.

Terminal Unit, NT; - receives the new TA message; - corrects the outgoing frame clock; and 20 - sends a receipt SUS1 and TA = X.

The network unit, NOW: - performs frame correlation; - retrieves the frame clock; - starts FFT data processing; IQ 5 - enables pilot decoding; - recovers the BSI; - enables channel value calculation; LII k) KJ! 506 644 59 - selects a CCH; and - decodes the message.

The last set-up sequence, step 3, see Figure 31, handles the CCH selection for uplink and downlink. For the uplink, the NU receiver has selected the most suitable carrier and sends a CCH message containing this selection to the NT page. The message is sent repeatedly until it receives a receipt (oh).

On the NT side, the receiver decodes the CCH message and terminates SUS1 and transmits an SUS2, ie terminates parallel CCH transmission by transmitting only the CCH on the selected carrier.

The uplink CCH carrier has now been configured. For the downlink, the same step is performed in parallel, initiated through the NT page after receiving the first CCH selection message from NOW.

Thus, in step 3, the network unit will: - send the selected CCH for the uplink; - wait for a receipt; and - exit the CCH message.

The terminal unit: receives the CCH selection for the uplink; - ternines SU = -; - starts SUS2; and acknowledges each CCH selection. 506 644 60 The network unit: - receives the CCH selection for the downlink; - terminates SUS1; starts SUS2; and 5 - acknowledges each CCH selection.

The terminal unit: - sends the selected CCH for the downlink; - waiting for a receipt; - ends the CCH message. When these steps have been taken, the modem has idle mode, transmitting SUS2. Using CCH, the bit charge factors can now be changed according to channel characteristics and DAS transmission can be started.

The VDSL modem can have interfaces to different network elements, depending on the physical location of the modem, ie in space for access nodes or in customer premises. In the customer premises, the VDSL modem can interface with an active night termination equipment. At the access node, the VDSL modem will interface with an access-specific interface, see Figure 32, which shows a logical view of the network elements that interface with the VDSL modem.

The VDSL modem can be physically integrated with the network termination equipment, and the VDSL modem at the access node can be physically located in the cabinet in which the IQ Un access node is located.

NT (interface A1) and the access node (interface A2) require a layer 1 frame format of the VDSL modem. Integrated in the layer 1 frame, apart from the frame head and the payload, there is a number of control information. These various alarm indicators, only if SDH is taken whole by bit error rate for 506 644 61 information fields for handling and handling and control fields include ex. AIS path to customer premises) measurements such as SDH alarms, t. (Valid performance monitoring, indications of whether synchronization is poor or lost, equipment management alarms for loss of power supply and too high temperature, etc. Management fields also include activation of various loop tests on the modem, for 506 644 62 TABLE l System parameters for the overall system Orthogonality between modems No Duplex method Separate bands Frequency intervals between up- Depending on duplex filter / down data flow characteristics Net bit rate, - upstream 2 Mbit / s / down 26 Mbit / s 26 M Gross bit rate, - upstream Coding dependency - downstream Coding dependence Cable length <1300 meters Cable bandwidth 10 MHz Modulation, single carrier - upstream 0-4096 QAM - downstream O-4096 QAM Number of carriers, total 1024 Bandwidth for each carrier 128 CW ) Modulation DMT Access technology VDSL Signal power -60 dBm / Hz 5Û6 644 63 Bit error free frequency 10 ”Interleaving delay 0.5 ms (Interleaving delay) System margin 6 dB CCI-I - bandwidth l carrier, minimum 16 kbit / s - protocol HDLC Sample clk 20 MHz tlüppm Frame clk 20 MHz / (2048 + 1l2) = 9.19 kHz 506 644 64 TABLE 2 System parameters for the Transmitter Interleaving - depth 2 x frames - delay 0.5 ms DAC resolution 84 dB Clipping algorithm No (Clipping algorithm) IFFT - type Real - points 2048 - resolution 16 bit LP- filter LP 10 MHz Bit charge Yes, 0, 2, 4, 6, 8, 10, 12 bit Energy charge Yes, 4 bit BSI distance 1 s 506 644 65 TABLE 3 System parameters for the Receiver ADC resolution 66 dB FFT ~ type Real - points 2048 - resolution 16 bit LP filter LP 10 MH2 Synchronization - jitter <0.5 ns VCXO i25 ppm, l0ppm / V sensitivity - DAC 18 bit, range 0-5 V - resolution l / 100 of a sample 506 644 66 TABLE 4 Carriage Mode Mode Transmit Bit Charge Equalize Scaling CM3. Data 2 - 12 Yes Yes cm No o No o CM3 Sync info 0 Yes, sync Yes, low

Claims (2)

10 20 25 30 é? A channel value calculation and equalization system for use in a multi-carrier system, arranged to adaptively update equalization parameters in the frequency plane of an inverted channel model, characterized in that modification aids are provided for modifying said step equalizer. reverse channel model by, in use, an output signal, U, from said equalization aid being fed to a detector / quantization aid, an output signal, Y, from said detector / quantization aid being fed to a first input of said modification aid, and an output signal, EQ, modification aids are fed to said leveling aids. A channel value calculation and equalization system according to claim 1, characterized in that, in use, said output signal, Y, is supplied to a symbol decoding aid arranged to produce a decoded data stream. A channel value calculation and equalization system according to either claim 1 or 2, characterized in that said modification aid is operatively connected to a variance value calculation aid arranged to produce a signal, W, indicating an interference variance on each of said carrier systems. A channel value calculation and equalization system according to any one of claims 1 to 3, characterized in that said modification aid operates with an algorithm defined by: 506 644 68 ”20 25 H Rom = Book + .EQk fi Jkï (Yk- Uk) | Uk | 2 where p is a positive constant (u << 1) to determine successive values of said equalization parameters. A channel value calculation and equalization system according to claim 4, characterized in that the expression U / | UkP in the algorithm is replaced by: 2-integer (2.1og2lUk |) + integer (log2ß) 6. A channel value calculation and equalization system according to claim 5, characterized by the fact that -integer (2.log2 | Uk |) + integer (log2p) is produced by using an absolute value of Uksom an input value to a binary priority encoder and changing the characters of the output. A channel value calculation and equalization system according to claim 6, characterized in that multiplicative operations in said algorithm are implemented by means of a barrel shifter. A channel value calculation and equalization system according to any one of claims 3 to 7, characterized in that a value for the interference variance of each of the carriers in said multi-carrier system is value calculated using a standard method of integrating squared deviations from an average value, in which each quantized value, Y, is used as an average value for a class of data values, U, which is quantized to Y. A channel value calculation and equalization system according to claim 8, characterized in that a W Ü 20 25 6? 506 644 interference variance value for each carrier in said multi-carrier system is value calculated by means of an algorithm defined by: WN = ( 1. -s) .wk + s. | Yk-Uk | 2 in which integration is simulated using an exponentially weighted average filter and 6 is a small positive constant (6 << 1). A method of adaptively updating channel model in a multi-carrier system, characterized in that said smoothing parameters are modified in small steps, so that the smoothing converges in said reverse channel model by: - representing a signal, U, which data, transferred to a detector / quantization aid; and - an output signal, Y, from said detector / quanti- together with said EQ, sering aid is used, signal, U, to derive value calculations, for said equalization parameters. ll. A method according to claim 10, characterized in that said output signal, Y, is transmitted to a symbol decoding aid arranged to produce a decoded data stream. A method according to either claim 10, or 11, characterized in that a signal, W, is retrieved, which indicates an interference variance on each carrier in said and said multi-carrier system, from said output signal, Y, signal, U, which represents equalized data. A method according to any one of claims 10 to 12, characterized in that successive values of said equalization parameters are calculated by an algorithm defined by: H EQM = EQk + .Eok fl kï | Uk | 2 where p is a positive constant (p << 1). A method according to claim 13, characterized in that u / | UkP in the algorithm is replaced by: 2. -integer (2.log21Uk \) + integer (log2N 15. A method according to claim 14, characterized in that -integer (2.log2 | Uk |) + integer (log2p) is produced using an absolute value on Uksom a value to a binary priority encoder and change of characters on the output 16. characterized in that multiplicative operations in said algorithm A method according to claim 14, is implemented by means of a barrel shifter. A method according to any one of claims 12 to 16, characterized in that a value of the interference variance of each carrier in said multi-carrier system is value calculated using a standard method of integrating squared deviations from a mean value used, in which each quantized value, Y, as an average value for a class of data values, U, which is quantized to Y. W sne 644 18. A method according to claim 17, characterized in that a value for the interference variance of each carrier in said multi-carrier system is calculated using an algorithm defined by: Wk + 1 = (lS) .Wk-fS. | Yk-Uk | 2 in which integration is simulated using an exponentially weighted average filter and S is a small positive constant (E << 1).