SE506634C2 - Multiple carrier wave transmission system - Google Patents

Abstract

Each carrier wave comprises a channel, such that the number of bits per symbol, or bit loading, varies between channels and, within a channel, in time, so that each channel has an associated bit loading parameter. In operation, the multiple carrier wave transmission system is arranged synchronously to update, on the first and second transceivers, the bit loading parameters associated with each channel by transmission of data over a control channel. The control channel is established at the system start, on a predetermined channel in the multiplicity of carrier waves, whose identity is known by the first and second transceivers. The control channel, after the start, is altered from the predetermined channel to a further channel which is selected by the first transceiver on the basis of the channel characteristics.

Description

506 634 solutions meet many of the requirements for high bandwidth services, such as video-on-demand, but in the long run symmetrical duplex systems will be required. VDSL technology is very similar to ADSL, although ADSL has to provide much larger dynamic ranges and as a result is much more complex. VDSL is lower in cost and lower in energy (lower in power), and VDSL units in premises 10 (premises) need to implement an access control for media in the physical layer for multiplexing upstream data.

Four line codes have been proposed for VDSL: 25 30 35 CAP; of QAM with suppressed carrier, AM / PM, a version for passive NT- "Carrierless" configurations, CAP would use QPSK upstream and a type of TDMA for multiplexing (although CAP does not exclude a solution with FDM for upstream multiplexing ); DMT; Discrete Multi-Tone, a multi-carrier system that uses Discrete Fourier Transforms to create and demodulate individual carriers, for passive NT configurations; DMT would use FDM for upstream multiplexing (although DMT does not rule out a TDMA multiplexing strategy); DWMT; Discrete Wavelet multitone (Discrete Wavelet Multi-Tone), a multi-carrier system that uses "Wawelet transforms" to create and demodulate individual carriers; DWMT also uses FDM for upstream multiplexing, but also allows TDMA; and 50,506,634 - SLC; Simple Line Code, a four-level version of baseband signaling that filters the baseband and resets it at the receiver, for passive NT configurations; it is most likely that SLC will use TDMA for upstream multiplexing, although FDM is possible.

Early versions of VDSL will use frequency division multiplexing to separate downstream from upstream channels, and both of these from POTS and ISDN. Echo quenching may be required for later generations of systems with symmetric data rates. A fairly large distance, in frequency, will be maintained between the lowest data channel and POTS to enable very simple and cost-effective POTS line splitters. Normal use would place the downstream duct above the upstream duct. However, the DAVIC specification reverses this scheme to enable the distribution of VDSL signals over coaxial cable systems in buildings.

In a multi-carrier transmission system, there is always a need to exchange control information between a transmitter and a receiver. This information is generated in the receiver and terminated in the transmitter. This information contains information about the momentary characteristics of the channel and information about decisions regarding system changes that are required to handle the changes in channel characteristics.

In systems using bit charging technology, the number of bits transmitted per symbol is adjusted, or regulated (SNR). This control dynamically affects the signal-to-noise ratio of the current carrier. in time, the total bandwidth of the system. This variation in bandwidth leads to a 506 634 IQ Un 30 absolute system requirement for synchronous configuration of the transmitter and receiver in terms of the number of encoded / decoded bits per symbol and carrier. If this requirement is not met, the system will not be able to maintain a connection.

The present invention achieves this requirement, in a multi-carrier modulated system with bit load capacity, by dynamically changing the number of coded / decoded bits per carrier. The receiver continuously measures and values (estimates) the characteristics and changes of / in the channel. From this information, the performance of each sub-channel (sub-wave) is identified. Then, on the basis of this information, it is decided to reconfigure the transmitted number of bits per symbol for each individual carrier. To transmit this information, from a transmitter to a receiver, a special control channel is established. The control channel is used primarily for the exchange of channel information and changes in bit allocation for carriers. It is of utmost importance that this reallocation of bits per carrier is performed synchronously to maintain a connection. The present invention relates to a method of, by means of a special algorithm, ensuring the synchronization in the system during configuration changes.

An object of an present invention is to provide a method for use in a multicarrier transmission system to maintain synchronization between two transceivers during dynamic system reconfiguration of bit charge factors. Yet another object of the present invention is to provide a multicarrier transmission system in which synchronization between two transceivers is maintained during dynamic system reconfiguration of bit charge factors.

LJ: 30 506 634 Another object of the present invention is to provide a transceiver for use in a multi-carrier transmission system in which synchronization between two transceivers is maintained during dynamic system reconfiguration of bit charge factors.

Yet another object of the present invention is to provide a receiver for use in a multicarrier transmission system in which synchronization between two transceivers is maintained during dynamic system reconfiguration of bit charge factors.

A further object of the present invention is to provide a transmitter for use in a multicarrier transmission system in which synchronization between two transceivers is maintained during dynamic system reconfiguration of bit charge factors.

According to a first aspect of the present invention, there is provided a multi-carrier transmission system having a first and a second transceiver, each of said transceivers having a receiver and a transmitter, in which data is transmitted between said transceivers by modulating said data on a plurality ( multiplicity) of carriers in the form of multibit symbols, in which each of said carriers constitutes a channel, and in which the number of bits per symbol (bit charge) varies between channels and, within a channel, so that each channel has associated therewith one in operation , multi-carrier system is adapted to synchronously update, in time, bit charge parameters, characterized in that, said first and second transceivers, the bit charge parameters associated with respective channel by transmitting data over a control channel, of said control channel being established, at system start-up, on a predetermined one of said plurality of carriers whose identity is known from said first and second transceivers, and in that said control channel, after start-up, changes from said predetermined channel to an additional channel selected by said first transceiver on the basis of channel characteristics.

Decisions regarding changes in bit charge and control channel selection may be initiated by said first transceiver transmitting command signals over said control channel, said second transceiver may perform changes in bit charge and control channel selection carrier, and said second transceiver may measure changes in channel characteristics and transmit data thereon. said control channel to said first transceiver.

Said multi-carrier transmission system may be a DMT transmission system.

Said multi-carrier transmission system may be a DMT-based VDSL system.

Said multi-carrier transmission system may be a DMT-based ADSL system.

Said predetermined carrier can be selected from said multiplicity of carriers on the basis of SNR characteristics of the channel so that said control channel is subject to minimal interference from interference.

Upon activation of said multi-carrier transmission system, said control channel can be established by means of a process comprising the following three steps: - establishing said control channel on a predetermined carrier; 506 634 - transmission of said control channel to a carrier selected by said multi-carrier system and "enabling" of bit charge control, and - "enabling" of all carriers.

Said step of establishing said control channel may include, in each of said first and second transceivers: including "booting" of said transmitter; said transmitter continuously transmits frames in which all carrier paths, except said predetermined wave, are modulated at random ( random) data; said transmitter transmits a system "heartbeat"; "boot" of said receiver; said receiver initiates channel equalization; synchronization of clocks in said first and second transceivers; and establishing said control channel on said predetermined carrier when receiving a heartbeat.

Said step of transmitting said control channel may in said first transceiver: receiving data, by the transmitter, regarding measured channel characteristics from receivers in both said first and second transceivers; 506 654 Un 25 ~ selecting a carrier to which said control channel is to be reallocated by said transmitter; transmitting, by said transmitter, a signal identifying said carrier, to which said control channel is to be reallocated, to said second transceiver; upon receiving a confirmation signal from said second transceiver, said transmitter terminates said control channel on said transmitter said control channel on said predetermined carrier path; said transmitter starts said control channel on the unallocated carrier at a "heartbeat"; said receiver measures channel characteristics and transmits data relating thereto (characteristics) to said transmitter in said first transceiver; said receiver equalizes said equal channel; said receiver receives a channel value calculation (estimation) from the second transceiver and sends data relating thereto to said transmitter in said first transceiver; said receiver receives data identifying the carrier for reallocating said control channel; said receiver receives a confirmation signal from said second transceiver; Said receiver 50 506 634 terminates the control channel on said predetermined carrier path; said receiver establishes the control channel on the unallocated carrier; and if said control channel cannot be established, return to said step of establishing said control channel.

Said step "to enable" all carriers may include, on a continuous basis, in said first transceiver that: said transmitter receives data regarding measured channels from receivers in both said transceivers; said transmitter determines the bit charge parameter for each carrier; said transmitter transmits data regarding the bit charge parameter to said second transceiver; said transmitter changes the bit charge parameter upon confirmation from said second transceiver; the receiver measures channel characteristics on said multiplicity of channels and transmits data regarding said measurements to said transmitter; the receiver equalizes said diversity of channels according to said measured channel characteristics; 506 634 10 25 b) The Ul 10 receiver receives a channel value calculation from said second transceiver for each of said plurality of channels; the receiver receives a new bit charge parameter for each of said plurality of channels; - the receiver receives a confirmation signal from said second transceiver; - the receiver updates the bit load parameters for each of the plurality of channels.

Channel characteristics can be valued by periodic transmission, by one of the transceivers, of a base synchronization frame having a predetermined content and comparison, in the other of said transceivers, of the received synchronization frame with a reference frame.

Said channel characteristics may include attenuation, phase shift and variance.

Said base synchronizing frames can be transmitted at intervals, BSI, and said BSI is locked in said transceivers, thereby enabling said transceivers to identify a frame as a synchronizing frame.

Extra (additional) synchronization frames can be transmitted at intervals between said base synchronization frames.

The first transceiver may issue system reconfiguration commands at the start of one BSI, and system reconfiguration may be performed at the start of the next BSI.

IJ: 25506 634 ll The BSI can be greater than twice the system transit time for signals.

According to a second aspect of the present invention, there is provided a multicarrier transmission system having a first and a second transceiver, each of said transceivers having a receiver and a transmitter, wherein data is transmitted between said transceivers by modulating said data on a multiplicity of carriers in the form of multi-bit symbols, each of said carriers constituting a channel, and wherein the number of bits per symbol (bit charge) varies between channels and, within a channel, in time, so that each channel has an associated bit charge parameter, a method of operate a control channel characterized by: - synchronous updating, at said first and second transceivers, of the bit charge parameters associated with each channel by transmitting data over the control channel; establishing said control channel, at system start, on a predetermined carrier of said plurality of carriers whose identity is known by said first and second transceivers; and - after starting, changing said control channel from said predetermined channel to a further channel, selected by said first transceiver on the basis of channel characteristics.

Said method may include the steps of: - initiating decisions regarding changes in bit charge and control channel selection, in said first 506 654 Uu 12 transceiver, and transmitting command signals over said control channel; said second transceiver effects changes in bit charge and selection of control channel carrier; and said second transceiver measures changes in channel characteristics and forwards related data over said control channel to said first transceiver.

Said multicarrier transmission system may be a DMT transmission system. Said multi-carrier transmission system may be a DMT-based VDSL system.

Said multi-carrier transmission system may be a DMT-based ADSL system. Said predetermined carrier path can be selected from said plurality of carrier paths on the basis of SNR characteristics of the channel so that said control channel is subjected to minimal interference from noise. Said control channel can be established, upon activation of said multi-carrier transmission system, by means of a process comprising the following three steps: - establishing said control channel on a Lu u | predetermined carrier path; transmitting said control channel to a carrier selected by said multi-carrier system and for creating enabling bit load control; and 506 634 13 - "enabling" of all carriers.

Said step of establishing said control channel may include, in each of said first and second transceivers: - "booting" of said transmitter; - said transmitter continuously transmits frames in which all carriers, except said predetermined wave, are modulated with random data; - said transmitter transmitting a system "heartbeat"; - "booting" of said receiver; - said receiver initiates channel equalization / channel equalization; synchronization of clocks in said first and second transceivers; and - establishing said control channel on said predetermined carrier path upon receipt of a "heartbeat".

Said step of transmitting said control channel may include, in said first transceiver: - receiving data, by the transmitter, regarding measured channel characteristics from receivers in both the first and second transceivers; - selection of a carrier path to which said control channel is to be reallocated by said transmitter; Transmitting, by said transmitter, a signal identifying said carrier, to which said control channel is to be reallocated, to said second transceiver; upon receiving confirmation signal from said second transceiver, said transmitter terminates said control channel on said predetermined carrier; said transmitter starts said control channel on the unallocated carrier at a "heartbeat"; said receiver measures channel characteristics and sends data regarding this (characteristic) to said transmitter in said first transceiver; said receiver equalizes said equal channel; said receiver receives channel; a channel value calculation from the second transceiver and transmits data relating thereto to said transmitter in said first transceiver; said receiver receives data identifying the carrier for reallocation of said control channel; said receiver receives a confirmation signal from said second transceiver; said receiver terminates said control channel on predefined carrier; said receiver establishes the control channel on the unallocated carrier; and ua VI 506 634 15 - if said control channel cannot be established; return to said step of establishing said control channel.

Said step "to enable" all carriers may include, on a continuous basis, in said first transceiver that: - said transmitter receives data regarding measured channels from receivers in both said transceivers; - said transmitter determines the bit charge parameter for each carrier; - said transmitter transmits data regarding the bit charge parameter to said second transceiver; - said transmitter changes the bit charge parameter upon confirmation from said second transceiver; the receiver measures the channel characteristic of said plurality of channels and transmits data relating to said measurements to said transmitter; the receiver equalizes / adjusts (said) the plurality of channels according to said measured channel characteristics; the receiver receives a channel value calculation from said second transceiver for each of said plurality of channels; the receiver receives a new bit charge parameter for each of said plurality of channels; 506 634 (J: IQ UI 16 - the receiver receives a confirmation signal from said second transceiver; - the receiver updates the bit charge parameters for each of the plurality of channels.

Channel characteristics can be valued by periodic transmission, by one of the transceivers, of a base synchronization frame having a predetermined content and comparison, in the other of said transceivers, of the received synchronization frame with a reference frame.

Said channel characteristics may include attenuation, phase shift and variance.

Said base synchronizing frames can be transmitted at intervals, BSI, and said BSI is locked in said transceivers, thereby enabling said transceivers to identify a frame as a synchronizing frame. (additional) Additional synchronization frames can be transmitted at intervals between said base synchronization frames.

The first transceiver may issue system reconfiguration commands at the start of one BSI, and system reconfiguration is performed at the start of the next BSI.

The BSI may be greater than twice the system transit time for signals.

According to a third aspect of the present invention: there is provided a receiver, characterized in that it is adapted for use in a multi-carrier transmission system as set forth above, or adapted to implement the method set forth above. According to a fourth aspect of the present invention, there is provided a transmitter, characterized in that it is adapted for use in a multi-carrier transmission system as set forth above, or adapted to implement the method set forth above.

According to a fifth aspect of the present invention, there is provided a transceiver, characterized in that it includes a receiver as set forth above, and a transmitter as set forth above.

Embodiments of the invention will now be described, by way of example, with reference to the accompanying figures, in which: Figure 1 shows, in schematic form, an asymmetric communication system.

Figure 2 shows, in schematic form, a DMT system.

Figure 3 shows, graphically, the channel separations used in an asymmetric DMT transmission system.

Figure 4 shows, in schematic form, the cornerstones of a multitone carrier system modem contemplated in the present invention.

Figure 5 shows, in schematic form, a partitioning of the multitone carrier system modem shown in Figure 4, which is used to facilitate implementation.

Figure 6 shows, in graphical form, spectral allocation for copper pairs.

Figure 7 shows, in schematic form, the frame structure used in the multitone carrier system described here. Figure 8 shows, in schematic form, the analog interface of the multitone carrier system modem shown in Figure 4.

Figure 9 shows, in graphical form, the dependence of the signal-to-noise ratio (SNR ratio) on frequency in the multitone carrier system described here.

Figure 10 shows, in schematic form, the FFT algorithm used in the multitone carrier system modem shown in Figure 4.

Figure 11 shows, in schematic form, the frame correlation principle used in the multitone carrier system modem shown in Figure 4.

Figure 12 shows, in schematic form, implementation of a correlator used in the multitone carrier system modem shown in Figure 4.

Figure 13 shows, in schematic form, the averager used in the correlator in Figure 12.

Figure 14 shows, in schematic form, a correlation position detector used for the multitone carrier system modem shown in Figure 4.

Figure 15 shows, in schematic form, an overview of the synchronization unit used in the multitone carrier system modem shown in Figure 4.

Figure 16 shows, in schematic form, an overview of the FFT / IFFT unit used in the multitone carrier system modem shown in Figure 4.

Figure 17 shows, in schematic form, the use of a cyclic prefix. Figure 18 shows, in schematic form, a “decision directed” channel value calculation and smoothing system for use in the multitone carrier system modem shown in Figure 4.

Figure 19 shows QAM coding for b = 6.

Figure 20 shows, in schematic form, the realization of the calculation of bit charge and energy charge factors used in the multitone carrier system modem shown in Figure 4.

Figure 21 shows, in schematic form, an overview of the system controller interface used in the multitone carrier system modem shown in Figure 4.

Figure 22 shows, in schematic form, the manner in which two of the multitone carrier modems shown in Figure 4 are interconnected to create a multitone carrier transmission system.

Figure 23 shows, in schematic form, the vector management system used in the multitone carrier system modem shown in Figure 4.

Figure 24 shows BSI length.

Figure 25 shows, in schematic form, NU SC load distribution for BSI interruptions for the multitone carrier system modem shown in Figure 4.

Figure 26 shows the SUS pattern of the multitone carrier modem shown in Figure 4.

Figure 27 shows the DAS pattern in schematic form, for the multitone carrier system modem shown in Figure 4. 506 634 10 IQ Vu 20 Figure 28 shows, in schematic form, wake-up signaling for the multitone carrier system modem shown in Figure 4 .

Figures 29 to 31 show the set-up sequence of the multitone carrier system modem shown in Figure 4.

Figure 32 shows, in schematic form, a network overview of a network interface for a VDSL modem application.

Figure 33 is a diagrammatic illustration of the control channel architecture used in the present invention.

Figure 34 shows the initial set-up of a control channel.

Figure 35 shows control channel allocation.

Figure 35 shows the channel configuration in a fully configured system.

Figure 37 shows a synchronization frame.

Figure 38 shows the outline, in time, of additional (additional) synchronization frames.

Figure 39 shows the signal flow.

Figure 40 shows signal synchronization.

To facilitate the understanding of the present invention, a list of abbreviations used in this patent application is presented below.

ADC: Analog-to-Digital (A / D) Converter (Analog-to-Digital Converter) AIS: “Alarm In Signal” UI 20 h.) O ASIC: BPSK: BSI: BSI-D: BSI-U: CCH: CMI: CM2: CM3: CP: DAC: DAS: DF1: DF2: DF3: DMT: 506 634 21 Application Specific Integrated Circuit Binary Phase Shift Keying Base Synch Interval BSI for Downlink Connection BSI for downlink connection BSI for uplink connection Control channel Bärvågstyp (mode) 1; bit-loaded and used carrier (Carrier mode 1, bit-loaded and used carrier) Carrier mode (mode) 2, (removed) masked or obscured carrier (Carrier mode 2, masked out or disabled carrier) Carry type (mode) 3, carrier arranged for zero bit charging, (Carrier mode 3, zero bit-loading enabled carrier) Cyclic Prefix Digital-to-Analog (D / A) converter (Digital-to-Analog converter) DF3 frame sequence (DF3 frame sequence) Data frame, random (random) data parallel CCH, (Data frame, random data parallel CCH) Data frame, random data one CCH (Data frame, random data one CCH) Data frame, fully bit loaded one CCH (Data frame, fully bit loaded one CCH) Discrete multiton ( Discrete Multi Tone) 506 634 20 IQ lJn DWMT: EMC: FEC: FEXT: FFT: FTTN: Gl MUSIC: G2 MUSIC: G3 MUSIC: IFFT: IIR: ISDN: ISI: JTAG: LEX: LP: NT: 22 Discrete Wavelet multiton (Discrete Wavelet Multi-Tone) Electromagnetic Compatibility (Forward Error Correction) Remote Ass Far End Cross Talk "Fast Fourier Transform" Fiber To The Node First Generation, Prototype System (VME-Based) Three + Two, ASIC implementation (Three + two ASIC implementation) Two chips silicon implementation (Inverse Fast Fourir Transformation) Infinite Impulse Response International standard for digital networks for Digital Networks Inter-Symbol Interference Joint Test Action Group Local Pass Low Term Network Termination 20 IJ Un OFDM: ONU: PGA: POTS: QAM: SC: SDH: SF: SNR: STB: SUS: SUSl: SUS2: TA: TDMA: UTP: VCXO: 506 634 23 Network Unit Orthogonal Frequency Division Multiplexing Optical network (Optical Network Unit) Program Progammable Gain Attenuator Conventional Plain Old Telephony Service Quadrature Amplitude Modulation System Controller Synchronous Digital Hierarchy Synch Frame Signal / Interference Ratio to-Noise Ratio) Set Top Box Synch Frame Sequence SF and DFl Frame Sequence SF and DF2 Frame Sequence (SF and DF2 Frame Sequence) Time Advance Multiple Access with Time Division Multiple Access Unshielded Twisted Pair Voltage Controlled Crystal Oscillator 506 634 Un 20 fi 30 24 VDSL: Very High Bit-Rate Digital Subscriber Lines The system of the present invention is referred to for simplicity. due to as “MUSIC” (Multi-carrier System for the Installed Copper Network - Multi-carrier system for the installed copper network). MUSIC is intended to provide high-speed communication on copper pair cable for telephony to support broadband multimedia services.

(SE 9603187-7) and the patent specifications arranged in cross-reference SE 9603188-5, SE 96C3l89-3, SE 9603190-1, SE 9603191-9, SE 9603192-7, SE 9603193-5, SE 9603194-3, SE 9603195- O, SE 9603196-8, SE 9603197-6 And SE 9603198-4, cost-effective and robust customer implementation with silicon, the MUSIC system described in this offers one that provides 26: 2 or 13: 2 Mbit / s asymmetric transmission over copper cable ( local telephone networks.

The MUSIC system can be accessed using it (Fiber To which is each a network concept known as Fiber to the Node The Node = FTTN), serves many users, up to a switch cabinet in which uses optical fiber, the proximity of the users' homes. Thus, the cable length specification for MUSIC can be successfully limited to 1300 meters.

The MUSIC system is mainly intended for transmitting a high bit rate (26 Mbit / s) signal downstream to the subscriber, and a low bit rate (2 Mbit / s) signal upstream, from the subscriber.

Figure 1 shows the MUSIC system. A network device, NOW, is connected to the fixed network through an optical fiber link, (FTTN). multimedia application, A network termination, NT, connected to a e.g. video-on-demand, is linked UI 10 20 IJ Un 30 506 654 25 to the NOW via copper cable. The MUSIC system supports a high data rate downstream and a much lower data rate upstream.

In the MUSIC system described here, two fixed bit rates (l3: 2 and 26: 2 Mbit / s) are supported, where the lower bit rate l3: 2 Mbit / s can be implemented as an additional option for use in bad, or extremely long, copper cables.

For network termination (NT), the connection consists of a set of standardized interfaces, such as POTS, ISDN, ATM25 and Ethernet. All transmission protocols are supported by (carried by) the data flow in the modem, except the POTS service which so that it is independent of (NOW) is filtered out passively, modem status. The network device terminates in the fixed network.

MUSIC separates up and downlink spectra by passive filtering in the analog parts.

The version of MUSIC described here is intended to provide the opportunity for future functional upgrades. For this reason, the FFT / IFFT block is designed to support full functionality so that it can be reused in future system upgrades.

The MUSIC system is a DMT-based, multi-carrier VDSL system that uses discrete Fourier transform to create and demodulate individual carriers. This is shown in Figure 2, which shows two transceivers each having a receiver, Rx, and a transmitter, TX, connected to a twisted copper pair. Data is transmitted between the two transceivers using a plurality of carriers, some of which may not be used, e.g. when the channel quality is extremely poor. The number of bits transmitted by each of the carriers can also vary, depending on the channel quality. 506 634 20 26 A multi-carrier modulation technology such as DMT handles frequency-dependent losses and interference on twisted In the MUSIC system, the available bandwidth of 10 MHz is divided into 1024 carriers with a width of 9.77 kHz each. The assigned transmission power for the individual carriers depends on the pair cable in an efficient manner. the interference effect and the transmission losses on each of the belts. Each carrier transmits multilevel pulses that can represent up to 12 bits of data (4096 QAM). The signal / noise ratio (SNR) of the individual carrier is calculated on the receiving side. If a carrier has a high SNR, up to 12 pieces are placed on this carrier. For carriers with lower SNR values, fewer pieces are placed on the carrier. Carriers that are affected by narrow-band sources of interference are switched off. Forward error correction data interleaving is used to mitigate the effects of: malignant bursts of impulse interference.

Asymmetric VDSL is implemented in this version of the MUSIC system, which means that the downstream speed is much higher than the upstream speed. Two specified (26/13 Mbit / s) selected speeds depend on the current cable length (<1300 downstream speeds are supported by the system; the m) and / or the quality of the channel. The upstream speed is fixed at 2 Mbit / s.

The MUSIC system for separating the downstream channel from different frequency bands can be used in the upstream channel and both from POTS, see Figure 3.

Alternatively, other duplex methods can be used, e.g.

TDMA and / or a method where every other carrier is dedicated to the downstream and upstream channel.

Figure 4 shows an overview of a MUSIC modem to which the present invention relates. The most important hardware blocks are ADC and DAC, synchronization, fourir LJ! (J: IQ UI 506 634 27 transformation processing, channel value calculation / equalization, symbol mapping and detection, coding and decoding with interleaving, network interfaces and system monitors.

The modem can be considered in the form of four principal function blocks, namely: - the digital receiver unit; - the digital transmitter unit; - the analog input (front end); and system controller / PCI.

The a: a_oga input includes a hybrid transformer connected to an unshielded, twisted pair and POTS. On the receiver side, the hybrid is connected, via a low-pass filter, LP, a programmable gain attenuator, PGA, to an analog to digital (A / D) converter. A VCXO, power analog to digital converter. On the transmitter side, the voltage control is a crystal oscillator, used to connect the hybrid to a digital to analog (D / A) converter via a low-pass filter.

The digital receiver unit includes a "fixed Fourir" transmission and rescaling unit (rescaling FFT, synchronization unit and a channel estimator. Unit), connected, as shown in Figure 4, to a channel estimator connected via a symbol detection unit and a (de-interleaving) " deinterleaving "and decoding unit, to a bithazzer unit and thence to a network application interface.

The digital transmitter unit includes a bit handling unit which is connected to an inverted "phase" Fourir transform and scaling unit, IFFT, via an encoding and interleaving unit and a symbol mapping unit.

The system control is connected to different functional units in the digital receiver and digital transmitter, and to the network application interface and a computer interface, as shown in Figure 4.

The network (plant) interface connects the higher protocol level to the modem layer one functionality.

This block is responsible for providing the system with data at the configured bit rate, and adds “dummy frames” if required.

The data is then channel coded and interleaved. The MUSIC system described here uses a convolutional code combined with interleaving. Using a depth with multiple frames, a combined frequency / time interleaving is obtained (see later in this specification).

The symbol mapping block receives input data as an integer vector. This vector is mapped into the configured constellation depending on the current bit load value. The mapping unit uses a Gray coding scheme to reduce the probability of bit errors.

A real (vector) vector multiplication is the first step in the IFFT block. This causes the system to scale the IFFT block then performs an FPT on which modulates each carrier. As a final output power level: on each carrier. real 2048 dots inverted (inverse) input data, step is performed an address "wrap around" on the output data, where a copy of the first 128 samples is added at the end of the frame.They are called the cyclic prefix (CP).

The modulated signal goes to a DAC which converts the signal with a minimum true dynamic range of 84 dB. The DAC is clocked by the system sample clock at 20 MHz. To get rid of Nyquist "ghosts", the signal is LP-filtered. The hybrid provides a balanced interface to the copper cable.

An overview of the signal path of the MUSIC transmitter and receiver is shown in Figure 4. The transmitter part uses the same hybrid design as the receiver.

At the receiver end, the splitter / hybrid separates from 0 to 4 kHz, from the frequencies used by the system. The transceiver of the frequencies used by the POTS also extracts the low level reception signal from the combined high level transmission signal and the low level reception signal.

To reduce Nyquist effects on the signal, the received analog signal is low-pass filtered before being fed into the PGA (Programmable Gain Amplifier).

PGA n is necessary to make the best use of the dynamic range of the ADC. In this system, the dynamic range shall be at least 66 dB.

After the signal is converted to digital format, the synchronization and FFT blocks receive the data.

The synchronization block generates a frame clock (for controlling the EFT buffers) and a control signal for the VCXO.

Initially, the retrieve synchronization block retrieves the frame clock from the sampled signal. The frame clock is then used to calculate the frame synchronization value calculation “VCXO feed back (20 MHz). (frame timing estimate) and transferred to controller ”. The VCXO generates the sampling clock A sampling clock that is only controlled by a “frame time estimate” is not sufficiently accurate in a DMT system. a dedicated Therefore, after the locking sequence, 506 634 N IJ Vi N 30 pilot carrier is used to achieve a high synchronization precision on the sampling clock.

A BSI signal is also extracted from the pilot carrier.

BSI is the Base Synchronization Interval timing signal used to synchronize the CCH communication of the transmitter and receiver.

One of the new aspects of the MUSIC system is the algorithm used by the synchronization block, which is discussed in more detail later in this specification.

A 2048 point real FFT is performed on the input frames of the FFT block. After this, rescaling, which is based on the energy charge parameters, is performed before the data is transferred to the next block.

The channel value calculation and equalization is performed on the output data from the FFT block. All data frames are used (estimate) to calculate the value of the channel properties. These are then used to compute a bit charge vector that determines the number of bits to be transmitted on each of the carriers. This information is then transmitted to the transmitter through the upstream control channel (CCH).

In the symbol detection block, a "demapping" is performed for each carrier according to the bit-loading mask (de- (FEC), on the detected bitstream.

After unmapping, “deinterleaving” interleavingl and “error correction on receipt” are performed. Forward Error Correction The data is then ready for the network (application) / application interface block after bit handling.The dummy frames are removed in this block.

At the heart point of the system, shown in Figure 4, is SC). general purpose) processor that interfaces the control unit of the system (System Controller, SC is a general purpose and controls the various sub-blocks using a local PCI bus. In the version of MUSIC described here, the control unit is CPU programmable An external port is provided, through a JTAG interface on the motherboard (on-board), to facilitate programming.

The main tasks of the SC are to control system start-up and construction during driving time and to perform bit charge and energy charge calculations. It communicates with the remote side of the modem through a dedicated control channel (CCH). This channel transmits data regarding changes in bit / energy charge and other system signaling.

To obtain a cost-effective high-volume product, the digital components of the system must be two ASIC circuits. based on at least Figure 5 shows how the system can be divided (partition) for chip design purposes.

One chip contains the FT / IFFT core. A second chip contains frame synchronization, channel value calculation and smoothing, symbol detection and symbol mapping. The analog block and the network interface block can be implemented on a third and a fourth chip, respectively.

The system parameters used by the MUSIC system described here are shown in Tables 1 to 3 attached hereto.

VDSL systems operate in the spectrum from 0 to 40 Mz.

In this band, the MUSIC system, as described here, occupies the lower 10 MHz, see Figure 6. A number of traditional bands are found in this spectrum, including POTS and some radio amateur bands. Different frequency bands are used in the MUSIC system described here to separate downstream from upstream channels. Since the MUSIC system described here uses 1024 carriers over 10 MHz, each carrier has a bandwidth of 9.77 kHz, where the first two carriers are allocated by the DC level and the POTS service. The last carrier is disabled because it is the Nyquist point. 506 654 V »20 32 Other carriers (on radio bands) may need to be canceled. This is primarily a matter of immunity and charisma on the balanced copper pair.

By passively filtering the POTS spectrum, this service can be done independently of the MUSIC system described here, runtime status, or power supply.

There are two ways to provide ISDN services for a MUSIC modem connection. One way is to let the POTS and ISDN systems exist under the (below) MUSIC frequency bands. This can be achieved using a similar filtering process for ISDN band spectrum as for POTS. This filtering allows the service to be provided regardless of configuration.

The second way to provide ISDN is to allow ISDN to be a carrier service in the MUSIC system. This solution has the advantage in terms of spectrum efficiency. The use of 1024 carriers over 10 MHz gives each carrier a bandwidth of 9.77 kHz. The ISDN spectrum requires the allocation (150-4) /9.77 = 5, of these carriers. Depending on the channel characteristics, these five carriers must be chosen to have the best SNR in the system. For a standard connection, this gives 5 * 100 = 500 kbit / s bandwidth.

The optimal solution is therefore to use the modem as a carrier, and allocate only 64 kbit / s, compared to 500 kbit / s for the total bandwidth of the 64 kbit / s ISDN service.

The results of the attenuation and FEXT (Far End Cross Talk) measurements performed on a telecommunications operator's network showed that it is possible to achieve bit rates higher than 100 Mbit / s if the cable is shorter than 200-300 meters. For longer cables, attenuation at higher frequencies limits the maximum bit rate.

UI 20 506 634 33 For cables of about 500 meters, 40 Mbit / s can be achieved, and for a 1 km cable, 15-20 Mbit / s is realistic.

Another factor that reduces performance is EMC, which limits the power used. Some parts of the frequency domain may also need to be excluded.

A typical PSTN can be expected to have the following characteristics in terms of impulse interference: - maximum duration 250 ps - median interval 67 ms - maximum peak amplitude 20 mV - main energy below 200 kHz - background interference -107 dBm / Hz The main source for synchronization in the system is the sampling clock. The reference for the sampling clock is located on the NOW page and is common to all twisted copper pairs in a secondary cable.

The sampling clock frequency is 20 MHz at 10 ppm, with a "phase jitter" of less than 0.5 ns.

The sampling clock on the NT page is phase locked to the NOW page. The logic of the reading uses the frame synchronization value calculation (frame timing estimation) in a first stage, and then uses pilot carrier: to produce a fine adjustment of the reading. The locking logic controls the frequency of a VCXO via an 18 bit digital / analog converter. The requirements for the VCXO are 20 MHz in 25 ppm range and 10 ppm / volt sensitivity. The final reading must have a precision of 1/100 sample, with a "phase jitter" of less than 0.5 ns.

The frame clock is l / (2048 + 128) of the sampling clock and controls the start of receiving and sending the frames. 506 634 UI 20 34 The frame clock, which is used for both transmission and reception, deviates in phase on both the NU and NT side.

The frame clock for transmission on the NT side is the master and controls the start of the signal intervals, see Figure 7.

The reception frame clock on the NT side is obtained from the hardware function for the frame synchronization value calculation and controls the start of the frame sampling period, see Figure 7.

The frame clock for transmission on the NT side is the same as the frame clock for reception, but is a TA sample earlier in phase. TA is a parameter that is measured during system start-up on the NU side and is used to compensate for propagation delay on the copper conductor. This must be done to maintain the orthogonality, across the copper conductor, for the sampled periods, both uplink and downlink. The frame clock for transmission on the NT side controls the start of the signal intervals, see Figure 7.

The frame clock for reception on the NOW page is delayed a number of sample clock cycles (TA) in relation to the frame clock for transmission, after TA calculation has been performed. The delay before the calculation of TA in the start-up sequence is determined by the hardware function for the frame timing estimation hardware function and the value is accessible to the control unit.

The frame clock for reception on the NU side controls the start of the frame sampling period, see Figure 7.

The BSI clock is used to synchronize parameter changes between the sending and receiving sides. The parameters can be, for example, bit charge, energy charge or control channel frequency. The parameters are updated by the system controller, on both sides, before the BSI clock initiates the switch for the new set-up.

LJ »20 30 506 634 35 The BSI clock is 1/8192 of the frame clock. The uplink BSI clock is delayed by half a BSI clock cycle relative to the downlink BSI clock.

A short pseudo-random sequence on the pilot channel is used for BSI synchronization between the transmitting and receiving sides.

The cyclic prefix is an extension of the frames added by the FFT chipset. To maintain orthogonality throughout the signaling period, the last 128 samples of the frame are copied and placed before the actual frame. This arrangement addresses issues related to interference between symbols caused by time dispersion.

It is important that the part of the signaling period sampled only on the receiving side overlaps a signaling period in the other direction, along the entire copper conductor. TA is used to optimize this overlap period. The maximum cable length is limited by TA = 128 samples = 6.4 ps propagation delay. This corresponds to 1280 meters (if the propagation delay is 5 ns / m).

The analog interface connects the received and transmitted digital data stream at the Cl chip to the telephone line. There are also connections to the Tl chipset and the system controller for control end cases.

The analog interface is shown in Figure 8. The cable is connected to a hybrid transformer which is also linked to POTS. On the receiving side of the hybrid, the incoming signal passes through a low-pass filter and a programmable gain attenuator to an analog-to-digital converter, ADC, and from there to the C1 chipset. On the transmitter side of the hybrid, the output digital signal is converted to analog by a digital / analog converter, DAC, and goes from there via a low-pass filter LP to the hybrid transformer 506 634 Un 20 30. A voltage controlled crystal oscillator, which drives both the ADC and the DAC, is connected to the sync block of the T1 chip.

An OFDM frame is a sum of sinusoidal carriers modulated in phase and amplitude and spaced in the frequency domain with a minimum of separation distance between carriers. The assumption that the symbols within the frame are evenly distributed and uncorrelated in relation to each other gives a signal in the time plane with an approximately normally distributed instantaneous amplitude. Thus, there is a small possibility that input data can interact with each other to create pulses with very high peak levels.

However, the maximum amplitude must be limited to a lower amplitude than this so that there are a sufficient number of quantization levels in the DAC to handle average signals. Although the DAC has sufficient resolution to accommodate a high peak level in the transmitter, there are limitations on the receiver side (ADC). However, the consequences on the recipient side do not have to be as serious as they may seem.

A short cable has lower attenuation in the high frequency range than a long cable, see Figure 9. This means that a temporary pulse can occur in the receiver almost unaffected by the cable characteristics. Therefore, a relatively large dynamic range is required in the receiver. However, this can be easily achieved because almost equal attenuations do not require a large dynamic range. The ADC needs to accommodate the area indicated in Figure 9 by the solid, rough, arrow-marked line.

However, the greater high frequency attenuation of long cables requires a large dynamic range.

The high frequency attenuation also means that several large peaks would be required from the transmitter to build up high amplitudes in the receiver; a case that is even less likely to occur at the ADC input (input) than single peaks. The “free height” (headroom) can therefore be reduced and the ADC should accommodate the area marked by the rough, dashed arrow line in Figure 9.

In summary, performance can be optimized by carefully setting the signal level at the ADC receiver depending on the cable length.

The line splitter / hybrid has two main tasks, namely to: - divide and combine telephony signal (POTS) and VDSL signal frequency bands; and - prevent the transmitted signal from appearing at the receiver on the same device by balancing the cable.

Since each transmission direction has its own frequency band, it is possible to optimize both sides in terms of their respective frequency bands to increase the overall performance.

The purpose of the low-pass filter on the input signal is to reduce aliasing effects on interference above the frequency band used.

The low-pass filter on the output side reduces the transmitted power on the "stop band". These filters can form part of the division / hybrid module_ The best commercially available ADC today is the "Analog Devices AD9042" which has a signal / noise ratio of approximately 66 dB. It is recommended that either this ADC, or one with equivalent performance, be used.

For this description, it is assumed that a DAC with 14 bit resolution is used. 506 634 20 IJ Un 38 The FFT and IFFT algorithms are made up of 1024-point complex FFTs with data reorganization to allow the calculation of two real sequences at the same time.

Consequently, each of FFT and IFFT are effective 2048 points. The hardware realization is based on a radix-32 core that calculates the result in three “transformations” (passes), see Figure 10.

The relationship between the signal-to-noise ratio and the resolution in the algorithm can be expressed as: SNR = 22b-v-1 where b = number of bits, and v = ll (number of effective radix-2 "transformations"). The b solution provides 17 bit resolution (based on ADC SNR), but since ADC is not the only source of analog signal degradation, 16 bit resolution in the algorithm should be sufficient to maintain the resolution throughout the system.

The VCXO generates the sampling frequency used in the NT part of the system. The control voltage is based on data from the synchronization unit. The clock frequency must be very stable and phase locked to the NU reference clock to maintain orthogonality between symbols.

To take full advantage of the dynamic range of the ADC, a programmable attenuator must be inserted before the ADC.

The attenuation level is mainly a function of the cable length and can be determined by the value for "timing advance synchronization" by the system controller.

Attenuation resolution and range, and the relationship between the value for timing advance and the attenuation level, must be determined. Equalization and variance values can also be used in the calculations for improved results.

In a DMT system, a very precise synchronization between the transmitter and the receiver, IQ Uu 30 506 634 39, is necessary especially when carriers are modulated with large constellations.

In the embodiment described here, a new frame synchronization method is used which is based on correlation properties built into the structure of the received signal.

On the NU side, a crystal frequency oscillator with a fixed frequency is used as a reference for generating the sampling clock. On the NT side, a sampling clock is generated by a VCXO (Voltage Controlled Crystal Oscillator) which is locked in phase with the oscillator on the NU side. The VCXO is initially controlled by the frame timing estimate.

However, the resolution of the frame synchronization value calculation is not sufficient in the present application. Therefore, a dedicated pilot carrier, after a lock-in sequence, is used to achieve a very high accuracy of the sampling clock synchronization. Due to the long symbol duration in a DMT system, interference between symbols caused by channel time dispersion can be eliminated by means of a protection interval. (guard interval) as a prefix to each frame in the time domain. To maintain the orthogonality of the frames, the contents of each prefix are a copy of the last part of the following frame, making the frames appear to be partially cyclic.

The synchronization method used to estimate the frame synchronization uses the high correlation between a prefix and the corresponding part of a frame. By continuously correlating samples of the received signal, separated in time by the (known) frame length, the passage of a protection interval will cause a peak in the correlation value calculation (correlation estimate). Therefore 506 634 k) Un 30 40 these peaks will have a known synchronization relationship to the frames and can be used to create a frame start signal. The principle is shown in Figure ll.

The correlator and peak time estimator use a system clock generated by a VCXO. This clock is divided by (divided by) the total number of samples in a signal range (a cyclic prefix and a frame), to create a signal with the same period as the correlation peaks.

The frame time deviation between these two signals is used as input to a feed-back controller that adjusts the VCXO frequency to the correct sampling frequency, however, the phase of this sampling clock is not accurate enough to be used in a DMT system. the frame synchronization value calculation is mainly used for a lock-in operation, it is also used to monitor the frame synchronization to detect major deviations that will make a resynchronization necessary.

The correlation of the received data is calculated continuously. The time difference between the two signals is achieved by using a digital delay line on a frame length. The output of the delay line is multiplied by the non-delayed signal and integrated (accumulated) over an interval corresponding to the length of the cyclic prefix. The output from the integrator is the value calculation (estimate) of the correlation function.

Since only the synchronization information of the correlation value calculation is used, a simplified estimator is implemented which uses only the symbol of the entered data. This hardware implementation has a greatly reduced complexity compared to using the full sample word length. Computer simulations have shown that the use of synchronous averaging of a plurality of signal intervals reduces the variance of the frame synchronization value calculation. Depending on the reduced data word length used in the multiplier portion of the correlator, it is possible to implement such a multiplication ratio. .

A block diagram showing the implementation of the correlator is shown in Figure 12. The incoming signal X (k) 1024, to a conjugator. The output of the delay passes through a delay of N = ie a frame, and the conjugator is then multiplied to produce a signal Y (k) the averifier, which Z (k) signal W (k) C (k). which goes to an average value generator. The output of Z (k) goes to a subtractor from 128 subtracted. delayed by L = This gives one that goes to an accumulator that gives an output signal. The details of the averaging part of the correlator are shown in Figure 13. The averaging comprises a series of delay elements combined with adders, as shown. The output signal can be expressed as ïl fl m Z (k) = Y (k-iM) 0 where Y (k) is the input signal and Z (k) is the output signal.

To make the averaging synchronous with the frame structure of the signal, the delays are equal to the signal interval.

A detector for finding the position of the maximum size of the correlation function value calculation is shown in Figure 14. It is implemented using a register (# 1) for the latest max. Value and a comparator. 506 634 UI 25 42 The register contents and the correlation size are compared, and each time a value greater than the register contents is found, the new value is stored in the register. The current value of a counter that counts sampling intervals (modulo signal intervals) is also passed to a second register (# 2). this second register to contain an index to it When an entire signal interval has passed, the max. value found during this interval. This index is stored in a third register (# 3), once per signal interval, and the contents of the first register (1 #) are divided by two (using shift). (using The index stored in register # 3 is interpreted as the deviation between the counter value and the current synchronization of the input signal frames. The feedback controller will cause the mean value of this deviation to converge to zero. The counter value can then be used as a pointer to the signal interval. Frame synchronization generating clock using this counter value to indicate the frame start.

The value calculation of the complex representation of the pilot carrier in the frequency plane is performed using the FFT unit available in the system. The advantage of using this method is that the value calculation will be independent of the varying modulation of other carriers. This is due to the inherent orthogonality between the carriers. In order to achieve a value calculation with acceptably low variance, a certain average value formation is necessary. This is done using the first-order digital IIR filter.

Unfortunately, the value calculation is represented as a complex number in rectangular coordinates, so the argument is not directly available. In the feedback loop, it is (detect) necessary to detect very small UI k) lJl 30 506 634 43 argument deviations. Therefore, the resolution of the argument must be high. The feedback controller will cause the pilot carrier argument to converge to zero. An approximation of the argument, which is linear only in a small area around zero, is then sufficient to achieve acceptable performance. A useful approximation that is "monotonic" in almost all four quadrants, and also easy to implement in digital logic, is described by the expression: A = M. [3 {c} - <1-sgn9¶ {C}) .K. 9ï {c} .sgn.3 {c}] where C is the complex pilot carrier value calculation, M is a positive scaling constant, and K is a positive constant that affects the design of the function (here K = 2 is used).

The channel introduces phase shifts on the pilot carrier which can cause “misalignment” between the frame synchronization of the input signal and the pilot argument zero.

To eliminate this problem, the pilot carrier estimator also passes through the frequency domain equalizer. The smoothing parameter for this carrier is set during the start sequence, when the frame timing estimate has converged to its final value.

The choice of pilot carrier will be fixed, but logic for choosing other carriers as a pilot can also be provided. The feedback loop actually has two "controllers", each with its own input signal. The two controller outputs are added and fed via a D / A converter to the VCXO which generates the sampling clock. Both "controllers" are of the PI type (Proportional and Integrating). 506 654 Un h) Uu 30 44 Figure 15 gives an overview of the signal paths. The received data in the schedule passes through the correlator and the peak position estimator to result in the frame clock. The complex pilot carrier in the frequency plane derived from the equalizer is fed to a pilot argument estimator, the output of which is fed to "feedback controllers" which also receive output from the peak estimator. The output of the "feedback controllers" is then passed to a D / A converter to provide a signal used to control the VCXO.

During the startup sequence, only the frame synchronization controller is active. Once the frame synchronization has stabilized, the equalization parameter for the pilot carrier is calculated and set (by the SC). updating this parameter is suppressed. After this This is done only once, and further change of equalization parameters, the averaging for the argument estimator is given sufficient setting time.

Finally, the frame synchronization controller is stopped and the pilot argument controller is activated. When the frame synchronization controller is stopped, its last value is locked so that the VCXO frequency remains close to its final value.

The pilot carrier is also used for transmitting synchronization information for the Base Synchronization Interval (ESI). the path argument is normally assumed to be constant.

A short pattern is BPSK modulated on the carrier using phases O and n and leaving the carrier on phase O for the remainder of the BCI interval. If this pattern is only a fraction (pilot carrier argument value calculation negligible. A correlator is used to detect the pattern and provide the synchronization signal for BSI. Lll 10 20 Ix) lJl 30 506 634 45 The "System Controller" (SC) must have read access, to detect synchronization locking and for monitoring reasons, to registers that keep the estimator for frame time deviation and the pilot argument approximation.

In order to handle the initial equalization of the pilot carrier, it is necessary for the SC to read the averaged complex representation of the carrier and write to the equalization parameter memory.

An offset register to determine the relative synchronization between the input frames and the frame start signal is necessary and must be writable from the SC. This is used on the NT page.

The detected BSI event signals, for both reception and transmission, must be connected to the SC as interrupt inputs.

Alternatively, the pilot carrier can be recovered from the signal in the timing plane, using a bandpass filter, and used directly to phase a sampling clock oscillator. The frequency plan method described here has the advantage that the pilot carrier estimator is independent of the modulation of the other carriers. Another frame synchronization method would depend on introducing a known pattern into certain frames.

This would reduce system capacity.

The frame length and the length of the cyclic prefixes are fixed in the embodiment described here. The method, described above, is designed to work in a feedback loop with a VCXO. In a device using a specific sampling clock oscillator, the design of the frame synchronization estimator needs to be slightly modified. It is important that the VCXO has a very low phase fault, as the feedback loop is too slow to compensate for such a fault.

N U 20 IQ UI E 506 634 46 A discrete multitone system (DMT) modulates N complex data symbols on N carriers (here we use N = 1024 carriers). This mapping is calculated as a reverse (inverse) discrete Fourir transform using Inverse (IFFT).

N st carriers of an FFT.

Fast Fourier Transform “In the receiver they are demodulated in the modem, FFT and IFFT are performed by (radix) 16, in different phases. This process is shown as described here, the same unit, using the same base or 32 "cores", schematically in Figure 16.

The main operation is divided into frames with lengths of 2048 real, this unit performs an FFT, or 1024 complex values.

IFFT, and addition of cyclic prefix.

For each frame scaling, descaling, the FFT and the IFFT calculate 2048 points real FFTs and work with a minimum of 16 bit arithmetic.

(NT), synchronization between the input frame start and IFFT- For the night terminal side, there is a requirement for the output start. (A synchronization between the upstream and downstream carriers). The transmitter must be able to start transmitting a frame before it starts receiving a frame, so-called "timing advance". should be provided before IFFT.

This scaling is a multiplication between the real A scaling coefficients stored in this unit, and the input values from the symbol mapper (SM). The coefficients are 16 bits each.

The coefficient memory consists of two banks of the same size (l6x1024 bit). One bank is used while the other is updated. Switchingf is enabled by a PCI command and executed at the next BSI.

(J: 20 h.) UI 506 634 47 After the FFT, a rescaling must be performed before the data is transferred for smoothing and symbol detection.

This rescaling is a multiplication by the inverted value of the scaling values. The coefficients are represented by 16 bits.

An exponent (resulting in a 4-bit post shift) may also be needed to maintain precision.

The coefficient memory consists of two banks of the same size ((l6 + 4) x1024 bit). others are updated. Switching is made possible by a PCI- One bank is used while the command and executed at the next BSI.

At the beginning of each frame, a cyclic prefix is added.

This process is shown schematically in Figure 17. The insertion of a cyclic prefix eliminates interference between symbols (ISI), and preserves the orthogonality between the tones, resulting in a simple input / output ratio that allows each carrier to be considered as a separate channel. .

This cyclic prefix consists of a repetition of the last part of the frame.

Provided that “timing advance” is used and the maximum cable length is 1300 m, a cyclic prefix of 128 samples will be required. Thus, the output for each frame will be a sample: 1920, l92l, ..., 2046, 2047, 0, l, 2, 2046, 2047 For each of the above components there is a FIFO as an interface to the external world with FFT / IFFT input and output memories. Thus, there are a total of 4 FIFOs.

It is recommended that the FIFOs with interfaces to the analog side have a size of 384 words (16 bits) and the FIFOs that interfaces with T1 chips have a size of 448 words (32 bits). 506 634 h) Un 48 Another DMT technology that does not use “Fourir transformation” is “Discrete Wavelet Multi-tone Transform” (DWMT). This method has been submitted to the ADSL Standardization Committee, which rejected it.

The precision required in this technology depends on the required dynamic range, which in turn is determined by the analog components (especially DAC). The FIFO size will depend on clock speed differences and the amount of timing advance used.The use of clipping is a compromise between dynamic range (quantization disturbances) and clipping disturbances.

Channel value calculation is performed using a "decision directed" method, as all data frames are then used to update the channel model.Known data frames are necessary only at start-up.In certain circumstances, interference on the channel can be calculated using all data frames.This is important too early detection of changes in channel transmission quality.

The basic principle for “decision directed” value calculation is that differences between received data and known, transmitted data are used to update a channel model. At some stage of this process, the channel model is accurate enough to be used to smooth the received data, and the detector will produce correct data. This output can then be used in the same way as the known data for further updating of the channel model. Therefore, the predefined data frames are no longer necessary and random data transmitted through the channel is used instead.

By using data taken after the equalizer as input data, and data after the detector as the second input data, an adaptive update algorithm can be designed. It modifies the equalization parameters in small steps in such a way that the equalizer converges towards a model of the "reverse" Un 20 IQ lJl 506 634 49 (inverse) channel. Figure 18 shows a block diagram of such a system. Input in the frequency plane enters the equalizer and is multiplied by the output of an equalizer parameter update unit, EQ. The resulting signal, U, then goes to a detector (quantizer) whose output is Y. Y then goes to a symbol decoder that produces a decoded data bitstream. U and Y also go to an input (input) on the equalizer parameter update unit and to a variance estimator.

The output of the variance estimator is W.

An adaptive algorithm for calculating the value of the smoothing parameters (EQ), which uses the smoothed data (U) is described by the following equation: and the quantized data (Y) as input data, as = so, + ”.EQwUkÛ (Yk- Uk) | Uk | 2 where p is a positive constant (u << 1), which affects the adaptation dynamics. A smaller value gives a slower adjustment than a larger value, but it also gives a greater insensitivity when there are disturbances on the input signals.

For implementation reasons, the division shown in the equation should be avoided. The expression u / | UkP has too large a dynamic range to be replaced by a constant. However, it is possible to quantify this expression in a logarithmic way as shown below: u / 'Uk 2 z 2-i :: teger (2.log2 fUk | J + intege fi logzp) The exponent in the above expression can be produced using the absolute value of Uk as input data in a binary priority encoder and change the sign (negating) of the output data. 506 654 10 20 I Q Un 30 50 Since the expression is an integer power of two, the multiplication is implemented in the algorithm using a "barrel shifter".

The interference variance of each of the carriers is value calculated using the standard method to integrate the squared deviations from a mean value. In this case, each quantized value, Y, is used as the mean of the range of data values, U, which is quantized to this Y. This method assumes that the symbol error rate is low enough for each data value to be associated with the correct mean. However, if suitable constellations are selected for the different carriers, this condition is met.

Figure 18 shows the variance estimator as part of the system. The algorithm used for the value calculation is described by the following equation: wm = (i-s) .wk + s. lybuklz The integration is here replaced by an exponentially weighted average filter. The parameter s is a small, positive constant (e << 1) that affects the dynamic properties of the filter. This is not a critical parameter, and selecting e from integer powers of two will suffice.

If a value of S is selected that provides a good variance value calculator (estimator), the algorithm will not be able to detect sudden changes in the interference level.

Therefore, a separate algorithm, working in parallel with the variance estimator, may be necessary for this task.

The "System Controller" must have both read and write access to the memory that holds the smoothing parameters.

Initialization of the parameters is necessary at start-up. Monitoring (parameters) of the parameters is also necessary UI N 506 634 51 to detect when they have leveled sufficiently close to their final values.

The channel variance memory must be available for the System Controller's read operations. Initialization of this memory to all zeros can be connected to a system reset.

The parameters that affect the dynamics of the estimators must be available for writing from the System Controller.

The method described here assumes a specific start-up sequence, both for the channel and interference value calculation_ During normal execution, it depends on a suitable choice of bit charge that gives a sufficiently low symbol error rate.

It is important that the equalization parameters are initialized to unit value at the beginning of the start sequence, as the input to the update algorithm passes through the equalizer.

The update algorithm is sensitive to scaling changes in the data path.

Any change in scaling in the transmitter must be compensated in the receiver. This also requires special care when using the analog gain control on the input side of the receiver. (encoder) maps a number of bits to the Symbol Map a complex number (I, Q) which indirectly determines the phase and amplitude of a carrier. The mapping of all values of a certain bit length is called a constellation, and is shown in Figure 19. The detection is the inverse function, ie from a complex value the value of the bits sent on the carrier is determined. The number of bits transmitted on a particular carrier is determined by the bit charge factor thereof. 506 634 10 20 30 bl Un 52 The construction of a specific constellation is aimed at allowing each point to be moved as far as possible from all other points. At the same time, the average energy should be as low as possible. Another restriction is that the mapping and detection units should be as simple as possible. However, the decision as to which constellation to use will affect not only the symbol mapping and detection units, but also the bit charge and possibly the adaptive equalizer.

For a given carrier, the encoder selects an odd integer point (I, Q) from the square-grid constellation based on the b-bits (vbllvbz, _, vLv¿). For simplicity of description, these b-bits are identified by an integer label whose binary representation is (vb-i, Vn-z, lvhvz). For example, for b = 2, the four constellation points 0, 1, 2, 3 are "labeled" corresponding to (vLv¿) = (0,0), (0,1), (1,0), (1,1), respective.

For even values of b, the integer values of I and Q of the constellation point (I, Q) are determined from the b-bits (vbl'vb 2, ___, vLv2) as follows. Divide V by VI = (vb1, v¿4, _H 'vl) and VQ = (vb2, vb4' ___, v0). Then apply the reverse Gray code to VI and VQ. This gives I and Q as I = 2Gra¶ (VI) + 1, and Q = 2Gray (VQ) + 1.

Figure 19 shows how the binary pattern for V folders on I and Q when b = 6.

Before these values are sent to the IFFT, they are normalized by shifting so that “msb” of these numbers becomes “msb” on the output (16 - [b / 2] steps left).

For a given carrier, the decoder uses a constellation point (I, Q) to determine the b-bits (vbl, (Jc 25 506 634 53 vbQ, ____ vLv2). For simplicity of description, these b-bits are identified by an integer label whose binary representation is (vbl vbz _H, vLv2).

It is assumed that the values of I and Q are limited by saturation to the range (X, Y). To determine V, Gray encodes the values- I = (iisÄ-n,, i1, io) f and Q = (q1s, q14,, q1, qo) f and then combines to V as V = (gin gqu | giN , gqn '.....), where the upper b-bits are valid.

The number of bits each carrier transmits depends on their (SNR).

The signal-to-noise ratio is calculated for each carrier in the respective signal-to-noise ratio receiver. Based on the signal-to-noise ratios, bit charge factors are calculated for each carrier. Thus, the number of bits each carrier must transmit per transmitted symbol is determined.

These bit load factors are calculated in an initial training session and can be updated if required.

The MUSIC system uses 2-dimensional Quadrature Amplitude Modulation (QAM) on each carrier, with bit charge factors ranging from 0-12 bits.

The number of bits transmitted on each carrier can be expressed by: SNRi) ßi = b¿ + log2 (L) = log2 (l + (1) T where F, the SNR gap, depends on modulation, possible coding and a system margin, and L the constellation expansion is dependent on the extra bits needed for coding.

Use of QAM constellations and some form of coding gives: 506 634 30 35 54 [Q fl (Ps / mf r = ______________ - CEO + Ymargin (dB) (2) 3 where Psär the desired symbol error rate, 'h is the "coding gain" ( gain of coding) in the system, fl Subject, is the system margin.The system margin is a factor used to compensate for unmodeled losses, impulse disturbances, etc. Equation (1) gives a bit charge factor with infinite granularity.

The bit load factors are rounded to give the supported factors (0 - 12 bits).

The rounding procedure will reduce the performance of the DMT system. If the energy distribution was allowed to vary, energy charge factors can be calculated for each carrier. This provides the ability to tune the energy so that (1) results in a bit charge factor supported by the system. Reconciliation gives: E._ 2 i (3) However, this can result in very large differences between carrier energies. In an environment with several different DMT systems, strange effects can occur if the different energies are allowed to vary too much.

The remote crosstalk (FEXT) will vary considerably in such an environment, and some DMT systems may have the full capacity of the cable. To prevent these effects, only small changes in the carrier energies can be allowed. Another limiting factor is the maximum energy allowed on each road.

The input data to the bit load algorithm will depend on the selected frequency domain equalizer. If an adaptive DFE is used, the SNR is obtained by: Wi (4) where Wi is the value-calculated interference variance described above.

For each carrier, a bit charge factor and an energy charge factor are calculated. The bit load factors can be represented by 3 bits, but to prepare the system even for odd bit load factors, 4 bits are recommended. For energy charging, n bit is used to give 2 ”- 1 possible factors.

The implementation of the calculations of bit charge and energy charge factors can be done in four steps shown in Figure 20. To achieve a given bit rate, a required SNR can be calculated and the system margin adjusted so that: the desired bit rate is achieved. The process, illustrated in Figure 20, includes the following steps: - First, the SNR is calculated using (4).

In the second step, four comparisons are performed, ie one for each of the four bits representing the bit load factor.

The thresholds depend on L and F, and can be pre-calculated. The first comparison determines if the bit charge factor is greater than 7, and the result of this comparison controls the first of the four bits representing the bit charge factor; it also controls the threshold for the next comparison. Similarly, this comparison controls the second bit and the threshold for the next comparison. After the four comparisons, the bit charge factor is determined.

The third step is to value the scaling factor for the transmitted energy so that the channel is used more efficiently. The energy is scaled according to equation (3).

Finally, the scaling factor is quantized to n bits.

It should be noted that in order to implement a system with constant energy charging, only the first two steps are necessary.

The energy charge and shift performed for normalization in the symbol mapping determines the scaling and rescaling factors sent to the IFFT / FFT processor.

The purpose of channel coding is to reduce bit error rates. The type of coding that should be used depends on the error pattern characteristics. Expected sources of error include random noise (which induces random bit errors), impulse disturbances (which induce error bursts) and clipping (which induces error bursts).

Faults caused by impulse disturbances mainly affect one or two bits per carrier. The probability of a single bit error on a carrier is always higher than the probability of 2 bit errors, which in turn is higher than the probability of 3 bit errors, and so on. This depends on the way in which the bits in the symbol are coded (ie Gray coding).

All coding depends on a synchronization to determine the start bit for the codewords and / or the "interleaving" blocks. "Simple dead reckoning" should be sufficient, since an error in data flow loss of frame synchronization, or error setting in In a system such as the MUSIC modem will (data flow slip) can never occur without bit charge. These errors necessitate a partial, or complete, system startup. 20 IQ Un 30 506 654 57 The channel coding will also include interleaving to increase the possibility of correcting burst errors.

"Interleaving" should be as deep as possible to obtain optimal function.The limiting factor in depth is the time delay introduced into the system.

The difference between time and frequency interleaving is of little importance because the coding and interleaving function is not sensitive to frame boundaries.

Reed-Solomon codes have the disadvantage that they are mainly burst error correction over a small number of bits (usually eight), a so-called symbol. Impulse bias errors generally introduce a "single-bit error" in some of the symbols. To take advantage of Reed Solomon codes, the most "error prone" bits must be concentrated in one, or a few , of the Reed-Solomon symbols.

The system margin as such (in itself) is a kind of coding that uses the margin of each carrier as the redundancy of the symbol. This redundancy per symbol must be converted to a "shared" larger number of symbols to handle burst errors. The higher redundancy that can be used by a coding rate that this introduces, can be used by certain types of convolutional codes.

The use of a convolutional code combined with "soft" information is therefore the optimal solution for a system with MUSIC channel characteristics. The convulsion code must be combined with interleaving.

It is possible to use a "top-level" Reed-Solomon code, or any other burst error correction code, such as Fire codes, to detect / correct the remaining bit errors 506 634 (J: 20 IJ LI: 30 58 This is especially useful because these errors occur in bursts as a result of the decoding of the convolutional code.

The "System Controller" is based on a "micro controller", or signal processor, depending on capacity requirements, for the MUSIC system the processor can be placed externally.A PCI bus interface is used to connect the System Controller and the various ASICs that make up the modem.

The function of the System Controller is shown schematically in Figure 21, which shows the paths of interaction over a PCI bus, between the System Controller and the FFT chip, the data mapping and detection chip, and the coding and decoding chip. Functions performed by the system controller are: - control of "Channel control signaling"; - calculation of bit charge and energy charge factors; - updating of system parameters in real time; and - system monitoring.

The System Controller, which is used for the modem described here, is programmable and accessible through a JTAG interface on the motherboard (on-board).

As shown in Figure 22, in a modem context with modem described here, the two data paths operate independently on the same physical copper cable, (NOW) the network termination (NT) on the user side. Both the transmitter Tx terminating in the network (work) unit on the network side, and and the receiver Rx are controlled by the System Controller.

The System Controller calculates and updates, after start-up, the bit charge and energy charge factors.

This update must be done at the same time starting from the same frame, on both the transmitter and receiver side. 506 634 59 The calculations are made and the update is initiated on the receiving page. The control channel, combined with the BSI clock, is used to ensure the synchronization of the update.

System Controller also monitors the system. Indications of system errors include the control channel starting to indicate errors, or receiving too many errors from the decoding channel unit.

The System Controller can initiate reboot at different levels; for example, go back to "idle mode", or do a full boot.

The control channel is a selected carrier that is only used for signaling between the two modems. The constellation on the carrier is initially 4 QAM and the data rate is approximately 16 kbit / s. The bit load can be changed to another constellation to increase the data rate.

The protocol on the control channel is partly based on HDLC for the physical layer. This means that the messages are packaged as a number of octets using "flag sequence" and "bit-stuffing". A 16-bit "frame check sequence" guarantees that each message is received correctly.

"Flag-sequence", "bit-stuffing" and "frame check sequence" are handled in the hardware on the mapping and detection chip. The contents of the messages are handled by the System Controller.

The maximum message length is limited to 64 octets depending on the size of the buffers on the mapping and detection chip.

Higher level protocols can be based in part on CCITT Q.92l recommendations.

In MUSIC modem SC several different vectors are handled; these are shown schematically in Figure 23. 506 634 10 20 IJ Un 60 For the transmitter part there is the bit charge and energy scaling vector. Corresponding on the receiver side is the bit charge, rescaling and equalization vector.

As previously described, the pilot carrier delivers a transmitter / receiver synchronization by transmitting and detecting a specific pattern. This clock is used by the system to synchronize changes in the transmitter and receiver vectors.

The time between the pilot synchronization patterns is called the Base Synchronization Interval (BSI) and is determined by the system response time, as shown in Figure 24.

This BSI is hardware dependent. Its length will not change, as the response time always remains the same.

When the system is running, there will be synchronization between the uplink transmitter and the receiver, through "base (BSI-U) see Figure 25. These BSIs are of exact sync interval uplink" (BSI-D), the same length but are shifted half a BSI interval and the base sync interval downlink SC at the NOW, interruptions for both BSI-U and BSI-D or NT, will receive For the NOW there will be a transmission BSI -D- interruption and a receive BSI-U interruption By switching BSI-U with BSI / 2, the SC charge will be better distributed over the BSI period.

The bit charge vector provides the system with the modulation pattern for each carrier. This is a vector that needs to be maintained and updated at exactly the same time on the transmitter and receiver side to provide a faultless connection. By using the BSI, the vector changes synchronously on the receiver and transmitter side. 20 lx) V: 30 506 634 61 The bit charge factors, constellations used on each carrier, are handled by two memories for reception and two memories for transmission on the mapping and detection chip. Each of the four memories contains a 4-bit word for each carrier (l024x4).

The System Controller points out which of the memories to use to send and which to use after receiving from the next BSI interval.

The bit charge factor can have values between 0 and 12, where 0 indicates an unused carrier; l-12 indicates the number of bits in 2 for 4QAM, 4 for 16QAM, 10 for the 1024 constellation (e.g.

QAM).

The energy vector holds information on how the carriers are scaled / rescaled for energy. This is a vector that needs to be updated synchronously, otherwise it will generate a distorted channel value calculation and bit error. The scaling vector will also be used as a pattern (mask) for canceled carriers.

Scaling of the various carriers on the transmitter side is handled by a memory area on the FFT chipset. The memory consists of a 16-bit word for each carrier (1024 x 16). These values are multiplied by the vector for each carrier in the frequency domain (I and Q are multiplied by the value separately).

The memory is doubled to ensure a synchronous update. The System Controller points out which of the two memories will be used from the start of the next BSI interval.

A corresponding memory (doubled) is implemented on the receiver side to rescale the carrier paths before symbol detection. If these memories contain a complex 506 634 20 k) (J: 62 value for each carrier (32 bits / carrier), only the I value will be used for rescaling.

The scaling and rescaling factors have values between 0.5 and 2.0. The value 0 is used for carrier cancellation.

The smoothing vector is used to smooth the received frame according to the channel characteristics. This vector is updated periodically, independently of the other side, when the channel value calculation is calculated by the receiver.

Depending on the specific transmission characteristics of the carrier, it will be assigned one of the following modes: - standard carrier - this carrier transmits data according to the calculated bit charge value and is "transmitter scaled" and "receiver scaled", - canceled carrier - no energy is transmitted at this frequency the scaling vector is therefore set to zero; or - poor carrier; SNR is too low to transmit any data and the bit charge is therefore set to zero.

In carrier mode 1 (CMI), the system operates normally.

The receiver continuously equalizes the channel.

Equalization changes are made for each new value calculation. Using the characteristic, the SC calculates the optimal bit charge factor. This value is transmitted to the transmitter using CCH, and a synchronous change is made.

(CM2) / rescaling value to 0 to disable In carrier mode 2, energy scaling is set to all out / in energy. The value of the bit charge vector is also set to zero to indicate that the carrier path is set to 20 lx) Un 506 634 63 stand. For this carrier path, no channel value calculation can be made.

In carrier mode 3 (CM3), the receiver has calculated a zero for the bit charge factor. On the transmitter side, this means that no data can be transmitted, and therefore no channel value calculation can be made at the receiver. To avoid this, the corresponding carrier value is transmitted from the synchronization frame and makes it possible to perform a channel value calculation at the receiver. The scaling / rescaling value can be used to lower the output power.

The carrier modes are presented briefly in Table 4.

The basic functionality of the "startup" sequence in the system, ie "cold" and "warm" boot, will now be treated.

Initially, the power supply in the system is considered to be switched off at one or both ends, NU and NT. This occurs if the power supply is lost due to a power failure, or by the user disconnecting (unplugging) the NT equipment. The most important thing to consider when starting up is, in addition to the connection function, to minimize the level of interference for other modems that use adjacent cables.

The different frame types used by the system are discussed below. 1. The synchronization frame is used for channel value calculation. This frame pours a specific modulation pattern for each carrier and thus enables easy channel value calculation. By letting the modulation pattern be described by a random sequence, the cross-correlation within the frame is kept low, so that the frame correlation used for synchronization is improved. 506 634 10 IJ V1 64 2. Data frame 1, (DF1), transmits "random data" on all carriers, except for four predefined carriers which transmit the control channel (CCH) in parallel. It is used at start-up when the CCH carrier is indeterminate and enables the receiver to select the least disturbed carrier, thereby guaranteeing the CCH connection. Data frame 2 (DF2) transmits "random data" on all carriers except one, which carries the control channel (CCH), it is used when the CCH carrier has been determined, and the bit charge factors have not yet been set 4. Data frame 3 (DF3) transmits data and uses the bit load function to maximize bandwidth.

A carrier is always dedicated to the control channel (CCH).

The system uses a special frame sequence, shown in Figure 26, at start-up and in idle mode (fidle mode), called the Start-Up Sequence (SUS).

SUS can be composed by using the different ones which are consequently called SUS1 and SUS2. The SUS frame sequence uses the synchronization frames for the data frames, DF1 and DF2, channel value calculation.

After start-up, the synchronization frames are replaced with data frames, as shown in Figure 27, and the channel value calculation process shifts from using synchronization frames to using the data frame. The type of data frame for this sequence is DF3.

At system startup, neither side of the modem, NOW and NT, sends any energy across the copper pair.

The default setting for each side is at this stage to drive the receiver, leaving the transmitter "dead".

The receiver tries, on each side, to perform a frame correlation to detect a frame start. This correlation is run through a threshold function that gives IQ U | 506 634 65 the receiver a distinct indication of when the other side starts transmitting. It is this indication that serves as a "wake-up" signal.

The “wake-up” signal is used only by the NT side. If the start-up decision is made on the NU page, the system goes directly to the set-up sequence described below.

This part of the start-up procedure is subjected to "time out" if a transition to the set-up sequence is not detected.

The basic wake-up signaling for the modem is shown in Figure 28. Initially, both modems search for frame correlation. One of the modems, on the right in Figure 28, sends a “wake-up” signal in the form of a SUS1. The second modem detects frame correlation and starts the set sequence described below.

When the wake-up state has passed, the web page (NOW) initiates the set-up sequence.

The set-up sequence will now be processed. This set-up sequence starts after the web page has detected a wake-up signal, or the network initiates the set-up.

The first step in the set-up sequence is shown in Figure 29. In this phase, NOW starts to send the SUS1 pattern. NOW repeatedly sends a timing advance (TA) setting, with TA = 0, on the CCH. The master clock in the system is now the NOW transmitter frame and the sample clock in NOW.

The pilot is sent continuously.

The NT receiver side, which looks for frame correlation, detects frames and can retrieve the frame and sample clock. It now starts the channel value calculation which at the current speed of synchronization frames makes an accurate value calculation within 300 ms. Using 506 634 20 30 66 this value calculation, the receiver starts polling the predefined CCH carriers and, at "message receive", selects this carrier for the CCH. The NT transmitter now starts with TA = the CCH carrier for each received TA selection message, O for local synchronization and sends receipt (acc.) on repeating the received TA value.It also shifts the outgoing pilot with BSI / 2 from the incoming pilot, so that the SC charge is distributed over time.When NOW detects the frame correlation, the transition to step 2 of the set sequence is made.

Thus, step 1 of the set-up sequence begins with the transmitter, in the network modem, transmitting a SUS1 and a TA message with TA = 0 at periodic intervals. Upon receipt of this, the receiver in the terminal modem will: - perform frame correlation and retrieve the frame clock; - start FFT treatment; enable pilot decoding; - recover the BSI; enable channel value calculation; - select a CCH; and - decoding the TA selection message.

The transmitter in the terminal unit then sends a receipt (acc.), SUS1, a TA = O message and a pilot shifted by BSI / 2. The receiver in the network unit is waiting for frame correlation.

Step 2 in the set-up sequence, see Figure 30, begins with the NU page now calculating a “timing advance” value (TA). The CCH message changes to the new, corrected TA value.

Un 20 506 634 67 When the NT page receives the new TA value, it changes the local synchronization and continues to send the acknowledgment message, with a new TA value, for each TA selection message.

In the NOW receiver, the frame clock is lost, due to the NT transmitter changing (changing) frame clock, and the unit needs to correlate. After the frame clock has been retrieved, the CCH is decoded and, upon acknowledgment detection, which contains the new TA value, the system terminates the TA message and goes to the third step of the set sequence. Thus, step 2 of the set sequence starts , NOW, sends a TA message that contains the correct TA, say X, together with a SUS1, is sent from the transmitting terminal. in response to SUS1 and the TA = 0 message as the Terminal Unit, NT: - receives the new TA message; - corrects the outgoing frame clock; and - sends a receipt SUS1 and TA = X.

The network unit, NOW: - performs frame correlation; - retrieves the frame clock; - starts FFT data processing; - enables pilot decoding; - recovers BSI n; - enables channel value calculation; 506 634 20 68 - selects a CCH; and - decodes the message.

The last set-up sequence, step 3, see Figure 31, handles the uplink and downlink CCH selection. For the uplink, the NU receiver has selected the most suitable carrier and sends a CCH message containing this selection to the NT page. The message is sent repeatedly until it receives a receipt (acc.).

On the NT side, the receiver decodes the CCH message and terminates SUS1 and transmits a SUS2, ie terminates parallel CCH transmission by transmitting only the CCH on the selected carrier.

The uplink CCH carrier has now been configured. For the downlink, the same step is performed in parallel, initiated by the NT ~ page after receiving the first CCH selection message from NOW.

Thus, in step 3, the network unit will: - send the selected CCH for the uplink; - wait for a receipt; and - exit the CCH message.

The terminal unit: receives the CCH selection for the uplink; terminates SUSI; starts SUS2; and acknowledges each CCH selection.

Network unit: 20 30 506 634 69 - receives the CCH selection for the downlink; - terminates SUS1; and starts SUS2; acknowledges each CCH selection.

The terminal unit: - sends the selected CCH for the downlink; - waiting for a receipt; - ends the CCH message.

Once these steps have been taken, the modem has idle mode, transmitting SUS2. Using CCH, the bit charge factors can now be changed according to channel characteristics and DAS transmission can be started.

The present invention relates to the synchronous updating of bit charge factors in multicarrier transmission systems. The exact way in which this is achieved will therefore now be discussed in more detail. It should be emphasized that the present invention can be used not only in MUSIC systems described herein, but also in other multi-carrier systems using dynamic bit charging.

At system startup, the control channel is configured and established, according to a predetermined sequence, to ensure that a connection is established. The start-up procedure can be described in three steps. These steps assume that the receiver is synchronized with the transmitter, as described above.

The uplink transceiver is the unit responsible for the system's "decision feedback". 506 634 70 The task for the downlink transceiver therefore consists of executing system changes according to the decisions made in the uplink transceiver, calculating the value of the channel and forwarding this information to the uplink transceiver.

This configuration is chosen to facilitate central system operation in which many duplex connections can emanate from the same point (uplink). The channel connection architecture is shown in Figure 33, in which the control channel links between receiver and transmitter within a transceiver are shown, together with the control channel links between transceivers. As is clear, the architecture is symmetrical between uplink and downlink transceivers, therefore these cannot be distinguished in the figure.

The three steps through which a control channel is established will now be described with particular reference to Figures 34 to 36.

Step 1: Establishment of a secure control channel.

After the receiver has been synchronized with the transmitter, it is necessary to establish a control channel.

The control channel is, in this case, a connection from the transmitter to the receiver. In a duplex system, this connection will be a two-way connection because both the uplink transceiver and the downlink transceiver contain a transmitter and a receiver, see Figure 33.

The establishment of this channel is an absolute requirement as further configuration is impossible without a connection between the transmitter and the receiver.

U: k) lJu E b: V: 506 634- 71 In the multi-carrier technology, the dispersal of the connection over many carriers makes it natural to assign a separate carrier for the control channel.

In ADSL / VDSL applications, before establishing a control channel, there is a perception of channel characteristics, see above. It is known, for example, that some carriers will give much higher SNRs than others. By using this information and selecting one of these carriers for the control channel, the probability of being able to establish a connection is improved.

Figure 34 shows the establishment of an initial, or primary, control channel on a high capacity carrier. The selected carrier for this is a preset system parameter.

During step 1, the following data / information is, or will be, available to both the transmitter and receiver: - Synchronization frame appearance; Carrier path for the control channel (initial); and - SNR value calculation (estimation) for the channel (rough).

The transmitters in both the uplink and downlink transceivers undergo / perform the following events / processes: - booting; - continuous transmission of frames with random data (random data), except for the carrier of the control channel; and - transmitting a system heartbeat on the control channel. 506 634 Ul l ~) LI: 30 72 The receivers in both the uplink and downlink transceivers undergo / perform the following events / processes: - booting; - initiation of channel equalization / equalization for direct equalization / adjustment; - synchronization; - after synchronization, establishment of the control channel. - when receiving "heartbeat", the channel is considered established.

After the channel has been established on a carrier, determined in advance, the system proceeds to step 2. At the start of step 2, none of the other carriers have been configured, or decoded. During step 2, the control channel is reallocated.

Step 2 assumes that the control channel has been established according to step 1. This means that the transmitter and receiver can exchange information about the control channel based on the value determinations made by the receivers in the downlink and uplink transceivers. This means that the system can move the control channel to a carrier with an SNR that is better suited for the function of this channel, ie a channel that has a smaller SNR margin.

This rearrangement provides a larger total bandwidth for user data because a "narrowband" channel can be selected as the control channel. The system margin for the SNR level on this carrier is selected slightly higher than for the other carriers with the intention of achieving a more stable channel, ie it is operated below (below) its full data carrying capacity. The selection of a new control channel is illustrated in Figure 35.

Information about the new control channel is sent via the control channel established in step 1, and the control channel connection from step 1 is disconnected. The system is now trying to establish the control channel on the new carrier. If this has not happened within a predetermined time period, the system will return to step 1.

During step 2, the following data / information is, or will be, available to both the transmitter and receiver: Synchronization frame appearance; Carrier weight for the control channel (primary); - SNR value calculation (estimation) for the channel from uplink and downlink (measured); and - reallocation of carrier for the control channel.

The transmitter in the uplink transceiver undergoes / performs the following events / processes: - receives information about the measured channel from the uplink and downlink transceivers. - decides on reallocation of the carrier path for the control channel; - sends information about the new control channel carrier to the downlink; 506 654 UI 30 35 74 - terminates the control channel upon confirmation from the downlink via the receiver uplink; and - starts "system heartbeat" on the new carrier.

The receiver in the uplink transceiver undergoes / performs the following events / processes: - measures channel characteristics and sends the information to the uplink transmitter: - equalizes the channel according to measured channel data; - receives channel value calculation from the downlink transceiver and sends the information to the uplink transmitter; - receives a: decision on a new control channel carrier for the uplink transmitter; - receives confirmation from the downlink transmitter; - terminates the control channel, and - tries to establish the control channel on a new carrier; if this has not occurred within a time period, tl, the system restarts step 1.

Once the control channel has been established on the new carrier, the system is ready to proceed to the last step, step 3, which is the configuration of the overall connection.

Step 3 assumes that the control channel has been reallocated ~ according to step 4. Since the transmitter and receiver can now exchange information, the rest of the carriers can now be configured and activated. This is illustrated in Figure 36.

(Ju 10 25 35 506 634 75 During szeg 3, the following data / information is, or will be, available to both the transmitter and the receiver: - synchronization frame appearance; - channel value calculations from uplink and downlink (*; measured); - carrier weight for the control channel; undergoes / performs continuously: the following events / processes: - receives information about measured channels from the uplink and downlink receivers; - decides on the bit charge for each carrier;

The receiver in the uplink transceiver undergoes / performs continuously: the following events / processes: - measures the channel and sends information to the uplink receiver; - equalizes / adjusts the channel according to measured kazel data; 506 634 UI 30 76 - receives channel value calculations from the downlink transceiver and sends the information to the uplink receiver; - receives decisions on new bit charge diagrams; - receives confirmation from the downlink; and - updates the bit load chart.

The multicarrier transmission system of the present invention uses a special reference frame to value the characteristics of the channel, herein referred to as the synchronization frame.

By transmitting a frame with predetermined content, which the receiver can compare, upon detection, with a reference frame, the receiver can value the characteristics of the channel, over which the frame is transmitted, in terms of attenuation, phase shift and variance.

Depending on the speed required for the channel value determination, these frames are transmitted more or less often.

Figure 37 shows an example in which a synchronization frame is transmitted after every sixth user data frame.

This base distance can vary from system to system.

The concept of Base Synchronization Interval (BSI) will now be considered.

This is defined as the distance between the synchronization frames during system startup (step 2 above).

U | Using simple logic in the receiver, the BSI can be calculated and locked, so that the receiver and the transmitter hold a local reference indicating the base synchronization frames.

The distance between these frames can be shortened by (additional) synchronization frames between the base synchronization frames. introduction of one, or more, extra These are introduced in multiples of the distance for the base interval, see Table 5. the base synchronization distance is a power of 2.

The requirement for this is that A simple diagram illustrating this update process from a base synchronization frame to 7 additional synchronization frames per base frame is shown in Figure 38 for a system: ed BSI = 16.

The base synchronization interval is not changed by the introduction of additional synchronization frames.

Update frequency: the channel value calculation is doubled for each step as the number of synchronization frames is increased, see column 1 in Table 5.

The BSI provides a reference clock that can be used to initiate system configuration changes.

One such: command regarding system changes is transmitted through the system, from the receiver to the transmitter, via the control channel. Such a command is generated by means of a "decision feedback" based on channel information in the receiver.An important factor in the command signaling chain is the different execution times for different system components in the signal path.

An overview of the signal flow, from the receiver to the transmitter, is shown in Figure 39. 506 634 UA 10 h) U | 78 78 When the receiver has received a reconfiguration message at time t7, see Figure 39, a confirmation is sent. This acknowledgment has the same, or shorter, signal transit time because it follows the same path through the system as the initiating signal, but contains less data.

Reconfiguration signaling is selected to start at the beginning of a new BSI interval to execute reconfiguration changes at the start of the next BSI.

By selecting BSI> 2 * Ts1, the system will execute the change synchronously.

If confirmation is not received before the next BSI interval, the change will not be performed, which, if the confirmation is destroyed, will lead to disconnection of the connection. By sending multiple confirmations, the probability of this happening is reduced.

The method described here for updating bit load factors can be used in different types of DMT systems.

The present invention provides a simple and reliable way of meeting synchronous update requirements. With the help of the dynamic configuration, greater opportunities are provided to adapt the implementation to several multi-carrier systems.

The VDSL modem can have interfaces to different network elements, depending on the physical location of the modem, ie in the space for access nodes or in customer premises. In the customer premises, the VDSL modem can interface with an active night termination equipment. At the access node, the VDSL modem will interface with an access-specific (J.

(Ju 506 634 79 interface, see Figure 32, which shows a logical view of the network elements that have an interface to the VDSL modem.

The VDSL modem can be physically integrated with the network termination equipment, and the VDSL modem at the access node can be physically located in the cabinet in which the access node is located.

NT (interface A1) and the access node (interface A2) require a layer 1 frame format of the VDSL modem. Integrated in the layer 1 frame, apart from the frame head and the payload, there are a number of information fields for handling and control information. These handling and control fields include various alarm indicators, such as SDH alarms, e.g. AIS (valid only if SDH is taken all the way to customer premises) measurements of bit error rate for performance monitoring, indications of whether synchronization is poor, or lost, equipment management alarm for loss of power supply and too high temperature, etc. Management fields also include activation of various loop tests on the modem, for operation and maintenance purposes. 506 654 80 TABLE 1 System parameters for the overall system Orthogonality between modems No Duplex method Separate bands Frequency intervals between up- Depending on duplex filter / down data flow characteristics Net bit rate, - upstream 2 Mbit / s - downstream 13 or 26 Mbit / s, Brut upstream / s Coding dependency - downstream Coding dependence Cable length <1300 meters Cable bandwidth 10 MHz Modulation, single carrier - upstream 0-4096 QAM - downstream O-4096 QAM Number of carriers, total 1024 Bandwidth for each carrier 9, 77 kHz Cyclic prefix DMes Modul VDSL Signal power -60 dBm / Hz 506 634 81 Bit error rate 104 Interleaving delay 0.5 ms (Interleaving delay) System margin 6 dB CCH - bandwidth} carrier wave, minimum 16 kbit / s - protocol HDLC Sample clk 20 MHz ilOppm Frame clk 20 MHZ / (2Û + ll2) = 9.19 kHz 506 634 82 TABLE 2 System parameters for the Transmitter Interleaving - depth 2 x frames - delay 0.5 ms DAC resolution 84 dB Cutting gs-algorithm No (Clipping algorithm) IPFT - type Real - points 2048 - resolution 16 bit LP filter LP 10 MHZ Bit charge Yes, 0, 2, 4, 6, 8, 10, 12 bit Energy charge Yes, 4 bit BSI distance 1 s TABLE 3 506 634 83 System parameters for the Receiver ADC resolution 66 dB FFT - type Real - points 2048 - resolution 16 bit LP filter LP 10 MHZ Synchronization - jitter <0.5 ns VCXO i25 ppm, 10ppm / V sensitivity - DAC 18 bit, range 0-5 V - resolution 1/100 of a sample 506 634 84 TABLE 4 Carrier mode Mode Transmit Bit charge Smoothing Scaling CMl Data 2 - 12 Yes Yes cMz No o No 0 CM3 Sync info O Yes, sync Yes, low 506 634 85 TABLE 5 Addition of extra synchronization frames Step Distance Distance Number of extra between between sync frames base frames sync frames between base frames l BSI BSI O 2 BSI BSI / 2 1 3 BSI BSI / 4 3 4 BSI BSI / 8 7

Claims (35)

506 634 86 PATENT REQUIREMENTS A multi-carrier transmission system having a first and a second transceiver, each of said transceivers having a receiver and a transmitter, the data being transmitted between said transceivers by modulating said data on a plurality of carriers in the form of multibit symbols, each carrier path constitutes a channel, and where the number of bits per symbol (bit charge) varies between channels and, within a channel, in time, so that each channel has an associated bit charge parameter, characterized in that, in operation, said multi-carrier transmission system is arranged synchronously updating, at said first and second transceivers, the bit charge parameters associated with each channel by transmitting data over a control channel, of said control channel being established at system start on a channel predetermined in said plurality of carrier paths whose identity is known by said first and second transceivers, and in that said control channel, after starting, changes from said predetermined channel to an additional one re channel, selected by said first transceiver on the basis of channel characteristics. A multi-carrier transmission system according to claim 1, characterized in that decisions regarding changes in bit charge and selection of control channel are initiated by said first transceiver transmitting command signals over said control channel, in that said second transceiver effects changes in bit charge and selection of control channel carrier, that said second transceiver measures changes in channel characteristics and forwards data relating thereto over said control channel to said first transceiver. A multi-carrier transmission system according to claim 1, or 2, characterized in that said multi-carrier transmission system is a DMT transmission system. A multi-carrier transmission system according to either claim 1, or 2, characterized in that said multi-carrier transmission system is a DMT-based VDSL system. A multi-carrier transmission system according to either claim 1, or 2, characterized in that said multi-carrier transmission system is a DMT-based ADSL system. A multi-carrier transmission system according to any one of claims 3 to 5, characterized in that said predetermined carrier is selected from said plurality of carriers on the basis of the channel SNR characteristics so that said control channel is subject to minimal interference from interference. A multi-carrier transmission system according to any one of the preceding claims, characterized in that, upon activation of said multi-carrier system, said control channel is established by means of a process comprising the following three steps: ~ establishing said control channel on a predetermined carrier; transferring said control channel to a carrier selected by said multi-carrier system and "enabling" of bit charge control; and - "enabling" of all carriers. 506 634 88 A multi-carrier transmission system according to claim 7, characterized in that said step of establishing said control channel includes, in each of said first and second transceivers: UI "booting" of said transmitter; said transmitter continuously transmits frames in which all carriers, except said predetermined wave, are modulated with random data; said transmitter transmits a system "heartbeat"; "Booting" of said receiver; said receiver initiates channel equalization / adjustment; synchronizing clocks in said first and azira transceivers; and establishing said control channel on said predetermined carrier path upon receipt of a "heartbeat". A multi-carrier transmission system according to claim 7, or 8, characterized in that said step of transmitting said control channel includes, in said first transceiver: receiving data, from the transmitter, regarding measured channel characteristics from receivers in both said first and second transceives; selecting a carrier path to which said control channel is to be reallocated by said transmitter; Transmitting, by said transmitter, a signal identifying said carrier path, to which said control channel is to be reallocated, to said second transceiver; upon receiving an acknowledgment signal from said second transceiver, said transmitter terminates said control channel on said predetermined carrier path; said transmitter starts said control channel on the unallocated carrier at a "heartbeat"; said receiver measures channel characteristics and sends data relating thereto to said transmitter in said first transceiver; said receiver equalizes / adjusts said measured channel; said receiver receives a channel value calculation from the second transceiver and transmitting data thereon to said transmitter in said first transceiver; said receiver receiving data identifying the carrier for reallocation of said control channel; said receiver receiving an acknowledgment signal from said second transceiver; said receiver terminating the control channel on said predetermined carrier; Uu 90 said receiver establishes the control channel on the unallocated carrier, and if said control channel cannot be established, return to said step, according to claim 8, to establish said control channel. A multi-carrier transmission system according to any one of claims 7 to 9, characterized in that said steps and "enabling" all carriers include, on a continuous basis, in said first transceiver that: said transmitter receives data regarding measured channels from receivers in both said transceivers; said transmitter determines the bit charge parameter for each carrier; said transmitter transmits data regarding the bit charge parameter to said second transceiver; said transmitter changes the bit charge parameter upon confirmation from said second transceiver; the receiver measures channel characteristics on said plurality of channels and transmits data regarding said measurements to said transmitter; the receiver equalizes / adjusts said plurality of channels according to: said measured channel characteristics; The receiver receives a channel value calculation from said second transceiver for each of said plurality of channels; the receiver receives a new bit charge parameter for each of said plurality of channels; - the receiver receives a confirmation signal from said second transceiver; - the receiver updates the bit load parameters for each of the plurality of channels. 11. ll. A multi-carrier transmission system according to any one of the preceding claims, characterized in that channel characteristics are valued by periodic transmission, of one of said transceivers, of a base synchronization frame having a predetermined content and comparison, in the other of said transceivers, of the received sync with the received receiver: a frame of reference. A multi-carrier transmission system according to claim ll, characterized in that said channel characteristics include attenuation, phase shift and variance. A multi-carrier transmission system according to either claim ll, or 12, characterized in that said base synchronization frames are transmitted at intervals, BSI, and said BSI is locked in said transceivers, thereby enabling said transceivers to identify a frame as a synchronizer. A multi-carrier transmission system according to claim 13, characterized in that additional 506 634 Uu 10 30 92 synchronization frames are transmitted at intervals between said base synchronization frames. A multi-carrier transmission system according to any one of claims 13 or 14, characterized in that said first transceiver sends system reconfiguration commands at the start of a BSI, and in that system reconfiguration is performed at the start of the next BSI. A multi-carrier transmission system according to any one of claims 13 to 15, characterized in that said BSI is greater than twice the signal transmission time of the system. In a multi-carrier transmission system having a first and a second transceiver, each of said transceivers having a transmitter and a receiver, the data being transmitted between said transceivers by modulating said data on a plurality of carriers in the form of multibit symbols, wherein each of said carriers constitutes a channel, and wherein the number of bits per symbol (bit charge) varies between channels and, within a channel, in time, so that each channel has an associated bit charge parameter, a method of controlling said control channel, characterized by: - synchronously updating, at said first and second transceivers, the bit charge parameters associated with each channel by transmitting data over the control channel; establishing said control channel, at system start-up, on a carrier scale predetermined in said plurality of carriers whose identity is known by the first and second transceivers; and - after starting, changing said control channel from W 506 93 654 said predetermined channel to a further channel selected by said first transceiver on the basis of channel characteristics, such as SNR. A method according to claim 17, characterized in that: - decisions are initiated, regarding changes in bit charge and selection of control channel, in said first transceiver, and transmission of command signals over said control channel; - said second transceiver effecting changes in bit charge and selection of control channel carrier; and - said second transceiver measures changes in channel characteristics and forwards data relating thereto over said control channel to said first transceiver. 19. characterized in that said A method according to claim 17, or 18, multi-carrier transmission system is a DMT transmission system. A method according to either claim 17, or characterized in that said multi-carrier transmission system is a DMT-based system. A method according to either claim 17, or characterized in that said multi-carrier transmission system is a DMT-based system. A method according to any one of claims 19 to 18, VDSL-18, ADSL-21, 506 634 94 characterized in that said predetermined carrier is selected from said plurality of carriers on the basis of SNR characteristics of the channel so that said control channel is exposed for minimal interference from noise. A method according to any one of claims 17 to 22, characterized in that said control channel is established, by activating said multi-carrier system, by means of a process comprising the following three steps: 24. establishing said control channel on a predetermined carrier path; transmitting said control channel to a carrier selected by said multi-carrier system and enabling bit charge control; and enabling of all carriageways. A method according to claim 23, characterized by said step of establishing said control channel including, in each of said first and second transceivers: "booting" of said transmitter; said transmitter continuously transmits frames in which all carriers, except said predetermined wave, are modulated with random data; said transmitter transmits a system "heartbeat"; "bocting" of said receiver; said receiver initiates channel equalization / adjustment; synchronization of clocks in said first and second transceivers; and establishment of said control channel on said predetermined carrier when receiving heartbeat. A method according to any one of claims 23, or 24, characterized by said step of transmitting said control channel including, in said first transceiver: receiving data, by the transmitter, regarding measured channel characteristics from receivers in both said first and second transceivers; selecting a carrier to which said control channel is to be reallocated by said transmitter; transmitting, by said transmitter, a signal identifying said carrier, to which said control channel is to be reallocated, to said second transceiver; upon receiving acknowledgment signal from said second transceiver, said transmitter terminates said control channel on said predetermined carrier path; said transmitter starts said control channel on the unallocated carrier path at a "heartbeat"; said receiver measures channel characteristics and sends data relating thereto to said transmitter in said first transceiver; 506 634 UI 10 k) UA 96 said receiver equalizes / adjusts said measured channel; said receiver receives a channel value calculation from the second transceiver and sends data relating thereto to said transmitter in said first transceiver; said receiver receives data identifying the carrier for reallocating said control channel; said receiver receives an acknowledgment signal from said second transceiver; said receiver terminates the control channel on said predetermined carrier; said receiver establishes the control channel on the unallocated carrier; and if said control channel cannot be established, returning to said step, according to claim 25, to establish said control channel. A method according to any one of claims 7 to 9, characterized by said step of "enabling" all carriers including, on a continuous basis, in said first transceiver: - said transmitter receives data regarding measured channels from receivers in both said transceivers; said transmitter determines the bit charge parameter for each carrier path; Un 10 30 Q.) Lil 506 634 97 - said transmitter transmits data regarding the bit charge parameter to said second transceiver; - said transmitter changes the bit charge parameter upon confirmation from said second transceiver; the receiver measures channel characteristics on said plurality of channels and transmits data regarding said measurements to said transmitter; the receiver equalizes / adjusts said plurality of channels according to said measured channel characteristics; the receiver receives a channel value calculation from said second transceiver for each of said plurality of channels; the receiver receives a new bit charge parameter for each of said plurality of channels; - the receiver receives a confirmation signal from said second transceiver; - the receiver updates the bit load parameters for each of the plurality of channels. A method according to any one of claims 17 to 26, characterized in that channel characteristics are calculated by periodic transmission, of one of said transceivers, of a base synchronization frame having a predetermined content and comparison, in the other of said transceivers, of the received the synchronization frame with a reference frame. 506 634 98 A method according to claim 27, characterized in that said channel characteristics include attenuation, phase shift and variance. 5 A method according to either claim 27, or 28, characterized in that said base synchronization frames are transmitted at intervals, BSI, and read said BSI in said transceivers, thereby enabling said transceivers to identify a frame as a synchronization frame. A method according to claim 29, characterized in that additional synchronization frames are transmitted at intervals between said base synchronization frames. A method according to either claim 29, or 30, characterized in that said first transceiver issues a system reconfiguration command at the start of one BSI, and performs system reconfiguration at the start of the next BSI. A method according to any one of claims 29 to 30, characterized in that said BSI is greater than twice the transmission time of the system for signals. A receiver, characterized in that it is adapted to be used in a multi-carrier transmission system according to any one of claims 1 to 17, or adapted to implement the method according to any one of claims 17 to 30 32. A transmitter, characterized in that it is adapted to be used in a multi-carrier transmission system according to any one of claims 1 to 17, or adapted to b: KJ: implement the method according to any one of claims 17 to 32. 506 634 99 A transceiver, characterized in that it includes a receiver according to claim 33 and a transmitter according to claim 34.