SE506641C2 - Multicarrier transmission system with channel data sent between two transceivers - Google Patents

Abstract

The multicarrier transmission system transmits channel information between two transceivers using several subcarriers. Each subcarrier or symbol has a parameter associated with it. The transceivers transmit the channel information as a sequence of a number of groups. Each group contains information concerning the number of adjacent subcarriers with the same value as the parameter, together with the actual value of the parameter. The parameter has several discrete values, and is a bit loading value and a QAM constellation identifier.

Description

5Û6 641 15 25 30 the use of asymmetric solutions in which high data rates are transmitted in only one direction. Such solutions meet many of the requirements for high-bandwidth services, such as video-on-demand, but in the long term, symmetric duplex systems will be required.

VDSL technology is largely similar to ADSL, although ADSL must provide much larger dynamic ranges and as a result is significantly more complex. VDSL is lower in cost and lower in power, and VDSL devices in premises need to implement media access control at the physical layer for multiplexing upstream data.

Four line codes have been proposed for VDSL: - CAP; "Carrierless" AM/PM, a version of QAM with suppressed carrier, for passive NT configurations, CAP would use QPSK upstream and a type of TDMA for multiplexing (although CAP does not exclude a solution with FDM for upstream multiplexing); - DMT; Discrete Multi-Tone, a multicarrier system that uses Discrete Fourier Transforms to create and demodulate individual carriers, for passive NT configurations; DMT would use FDM for upstream multiplexing (although DMT does not exclude a strategy with TDMA multiplexing); - DWMT; Discrete Wavelet Multi-Tone, a multicarrier system that uses "Wavelet transforms" to create and demodulate individual carriers; 10 25 506 641 DWMT also uses FDM for upstream multiplexing, but also allows TDMA; and - SLC; Simple Line Code, a four-level version of baseband signaling that filters the baseband and restores it at the receiver, for passive NT configurations; it is most likely that SLC will use TDMA for upstream multiplexing, although FDM is possible.

Early versions of VDSL will use frequency division multiplexing to separate downstream from upstream channels, and both of these from POTS and ISDN. Echo cancellation may be required for later generations of systems with symmetrical data rates. A fairly large separation, in frequency, will be maintained between the lowest data channel and POTS to allow very simple and cost-effective POTS splitters to place the downstream channel above the upstream channel. DAVIC splitters). However, in normal use the specification would reverse this order to allow distribution of VDSL signals over coaxial cable systems in buildings.

Currently, bit loading is used to vary the number of bits per subcarrier, in so-called discrete multitone, and OFDM transmission systems. Information regarding channel characteristics, such as bit loading and energy loading information, is transmitted as a sequence of N numbers, where N is the number of subcarriers.

It is necessary, when using discrete multitone (DMT) systems, to transmit information regarding how the channel characteristics affect the transmission, for example the number of bits to be transmitted per symbol. When using a large number of subcarriers, a relatively large amount of information regarding channel characteristics must be transmitted. It is therefore a requirement in such systems to provide an efficient method for transmitting such information.

An object of the present invention is to provide a method for the efficient transmission of information in a multicarrier transmission system, such as bit-loading information, i.e. a method in which the number of information bits that need to be transmitted is reduced in comparison with known systems, thereby achieving a saving in transmission capacity.

Another object of the present invention is to provide a multi-carrier transmission system in which information, such as bit loading information, can be transmitted efficiently, i.e. by reducing the number of information bits that need to be transmitted and thereby achieving a saving in transmission capacity.

According to a first aspect of the present invention, there is provided a multicarrier transmission system in which channel information is transmitted between two transceivers using a plurality of subcarriers, characterized in that each subcarrier, or symbol, has a parameter associated therewith, and in that said transceivers are adapted to transmit said channel information as a sequence of a number of groups, each of said groups containing information regarding the number of adjacent subcarriers having the same value as said parameter, together with the actual value of the parameter.

Said parameter may have a plurality of discrete values and may be a bit loading value, or a QAM constellation identifier. According to the invention, the number of information bits that need to be transmitted is significantly reduced in comparison with known systems, thereby achieving a saving in transmission capacity.

In a preferred arrangement for the multicarrier transmission system, said parameter may have a plurality of discrete values, and the number of information bits transmitted will be reduced if: P (m + n) < N x n where P is the number of groups, the number of discrete values of said parameter is > 2", but S 2n¿, and the number of subcarriers N is -1 > 2m, but S 2m .

According to the preferred system arrangement set forth in the preceding paragraph, the value of N may be equal to 1324, n may be equal to é, and m may be equal to 10. Thus, if P is equal to 50 groups, the number of bits to be transmitted will be reduced by 83%. However, if P is less than 200 groups, the number of bits to be transmitted will be reduced by at least 66%, if P is less than 100 groups. The number of bits to be transmitted will be reduced by at least 32%.

According to a second aspect of the present invention, there is provided a transmitter for a multicarrier transmission system in which channel information is transmitted between two transceivers using a plurality of subcarriers, characterized in that each subcarrier, or symbol, has a parameter associated therewith, and in that said transmitter is adapted to transmit said channel information as a sequence of n groups, in which each of said n groups contains information regarding the number of adjacent subcarriers having the same value as said parameter, together with the current value of the parameter.

In a preferred arrangement for the transmitter, said parameter may have a plurality of discrete values and be one or more QAM constellation identifier_bit load values. According to a third aspect of the present invention, there is provided a transceiver for a multicarrier transmission system characterized in that said transceiver includes a receiver and a transmitter as outlined in the preceding paragraph.

According to a fourth aspect of the present invention, there is provided a multicarrier transmission system including two transceivers as outlined in the preceding paragraph.

According to a fifth aspect of the present invention, in a multi-carrier transmission system in which channel information is transmitted between two transceivers using a plurality of subcarriers, there is provided a method of transmitting channel information, characterized in that each subcarrier, or symbol, has a parameter associated therewith, said method being characterized by the step of transmitting said channel information as a sequence of n groups, each of said 2 groups containing information regarding the number of adjacent subcarriers having the same value as said parameter, together with the current value of the parameter.

In a preferred method of the present invention, said parameter may have a plurality of Un W N u; Un 506 641 discrete values and may be a bit-charge value, or a QAM constellation identifier.

With the method of the present invention, the number of information bits that need to be transmitted can be significantly reduced in comparison to known systems, thereby effecting a saving in transmission capacity.

According to the method of the present invention, said parameter may have a plurality of discrete values, and the number of information bits transmitted will be reduced if: P (m+ n) < N X n where P is the number of groups, the number of discrete values of said parameter is > 2", but S Znfl, and the number of subcarriers N is > 2m, but S Zmd.

According to the method described in the previous paragraph, the value of N can be equal to 1024, n can be equal to 4, and m can be equal to 10. Thus, if P is equal to 50 groups, the number of bits to be transmitted will be reduced by 83%. However, if P is less than 200 groups, the number of bits to be transmitted will be reduced by at least 66%, if P is less than 100 groups. The number of bits to be transmitted will be reduced by at least 32%.

According to the invention, a multi-carrier transmission system, a transmitter, a transceiver or a method, outlined in the preceding paragraphs, may be characterized in that said transmission system is a DMT system. 506 641 Alternatively, according to the invention, a multi-carrier transmission system, a transmitter, a transceiver or a method, outlined in the preceding paragraphs, may be characterized in that said transmission system is a DMT-based VDSL system.

The foregoing and other features of the present invention will be better understood from the following description with reference to the accompanying figures in which: Figure 1 shows, in schematic form, an asymmetric communication system.

Figure 2 shows, in schematic form, a DMT system.

Figure 3 shows, graphically, the channel separations used in an asymmetric DMT transmission system.

Figure 4 shows, in schematic form, the building blocks of a multitone carrier system modem contemplated by the present invention.

Figure 5 shows, in schematic form, a partitioning of the multitone carrier system modem shown in Figure 4, which is used to facilitate implementation.

Figure 6 shows, in graphical form, spectral allocation for copper pairs.

Figure 7 shows, in schematic form, the frame structure used in the multi-ton carrier system described herein.

Figure 8 shows, in schematic form, the analog interface for the multitone carrier system modem shown in Figure 4.

Figure 9 shows, in graphical form, the dependence of the signal-to-noise ratio (SNR ratio) on frequency in the multi-tone carrier system described here.

Un 506 641 Figure 10 shows, in schematic form, the FFT algorithm used in the multitone carrier system modem shown in Figure 4.

Figure 11 shows, in schematic form, the frame correlation principle used in the multitone carrier system modem shown in Figure 4.

Figure 12 shows, in schematic form, implementation of a correlator used in the multi-tone carrier wave system modem shown in Figure 4.

Figure 13 shows, in schematic form, the averager used in the correlator in Figure 12.

Figure 14 shows, in schematic form, a correlation position detector used for the multitone carrier system modem shown in Figure 4.

Figure 15 shows, in schematic form, an overview of the synchronization unit used in the multitone carrier system modem shown in Figure 4.

Figure 16 shows, in schematic form, an overview of the FFT/IFFT unit used in the multitone carrier system modem shown in Figure 4.

Figure 17 shows, in schematic form, the use of a cyclic prefix.

Figure 18 shows, in schematic form, a "decision directed" channel value calculation and equalization system for use in the multitone carrier system modem shown in Figure 4.

Figure 19 shows QAM encoding for b = 6. 506 641 LI! 10 20 10 Figure 20 shows, in schematic form, the implementation of the calculation of bit loading and energy loading factors used in the multitone carrier system modem shown in Figure 4.

Figure 21 shows, in schematic form, an overview of the system controller interface used in the multitone carrier system modem shown in Figure 4.

Figure 22 shows, in schematic form, the manner in which two of the multitone carrier system modems shown in Figure 4 are interconnected to create a multitone carrier transmission system. Figure 23 shows, in schematic form, the vector management system used in the multitone carrier system modem shown in Figure 4.

Figure 24 shows BSI length.

Figure 25 shows, in schematic form, the NU SC load distribution for BSI interrupts for the multitone carrier system modem shown in Figure 4.

Figure 26 shows the SUS pattern for the multitone carrier system modem shown in Figure 4.

Figure 27 shows the DAS pattern in schematic form, for the multi-tone carrier system modem shown in Figure 4.

Figure 28 shows, in schematic form, "wake-up" signaling for the multitone carrier modem shown in Figure 4.

Figures 29 to 31 show the setup sequence for the multitone carrier system modem shown in Figure 4. Figure 32 shows, in schematic form, a network overview for a network interface for a VDSL modem application.

Figure 33 shows, in graphical form, the manner in which channel information is transmitted according to the present invention, in a sequence of a number of groups.

To facilitate understanding of the present invention, a list of abbreviations used in this patent application is presented below.

ADC: AIS: ASIC: BPSK: BSI: BSI-D: BSI-U: CCH: CMI: CM2: CM3: Analog-to-Digital Converter (A/D) "Alarm In Signal" Application Specific Integrated Circuit (Application Specific Integrated Circuit) Binary Phase Shift Keying (Binary Phase Shift Keying) Base Synch Interval (Base Synch Interval) BSI for downlink connection (BSI for downlink connection) BSI for uplink connection (BSI for uplink connection) Control channel (Control channel) Carrier type (mode) 1; bit-loaded and used carrier (Carrier mode 1, bit-loaded and used carrier) Carrier mode 2, masked out or disabled carrier (Carrier mode 2, masked out or disabled carrier) Carrier mode 3, zero bit-loading enabled carrier (Carrier mode 3, zero bit-loading enabled carrier) 506 641 IJ: 20 CP: DAC: DAS: DFl: DF2: DF3: DMT: DWMT: EMC: FEC: FEXT: FFT: FTTN: Gl MUSIC: G2 MUSIC: G3 MUSIC: IFFT: 12 Cyclic Prefix (Cyclic Prefix) Digital-to-Analog converter (Digital-to-Analog converter) DF3 frame sequence (DF3 frame sequence) Data frame, random data parallel CCH, (Data frame, random data parallel CCH) Data frame, random data one CCH (Data frame, random data one CCH) Data frame, fully bit loaded one CCH) Discrete Multi Tone Discrete Wavelet Multi-Tone Electromagnetic Compatibility Forward Error Correction Far End Cross Talk Fast Fourier Transform Fiber To The Node Generation one, prototype system VME-based Three + two ASIC implementation Two chips silicon implementation Inverse Fast Fourier Transformation 20 k) Un IIR: ISDN: ISI: JTAG: LEX: LP: NT: OFDM: ONU: PGA: POTS: QAM: SC: SDH: SF: SNR: STB: SUS: 506 641 13 Infinite Impulse Response International Standard for Digital Networks Inter-Symbol Interference Joint Test Action Group Local Exchange Low Pass Network Termination Network Unit Orthogonal Frequency Division Multiplexing Optical Network Unit Programmable Gain Attenuator Plain Old Telephony Service Quadrature Amplitude Modulation System Controller Synchronous Digital Hierarchy Synch Frame Signal-to-Noise Ratio Set Top Box Synch Frame Sequence 506 641 U: 20 25 30 14 SUS1: SF and DFl frame sequence (SF and DFl frame sequence) SUS2: SF and DF2 frame sequence (SF and DF2 frame sequence) TA: "Time Advance" TDMA: Time Division Multiple Access (Time Division Multiple Access) UTP: Unshielded Twisted Pair (Unshielded Twisted Pair) VCXO: Voltage Controlled Crystal Oscillator (Voltage Controlled Crystal Oscillator) VDSL: Very high bit-rate Digital Subscriber Lines (Very high bit-rate Digital Subscriber Lines) The system to which the present invention relates is referred to for simplicity as "MUSIC" (MUlti-carrier System for the Installed Copper Network). MUSIC is intended to provide high-speed communication on copper pair cable for telephony in support of broadband multimedia services.

(SE 9603194-3) and the cross-referenced patent specifications SE 9603187-7, SE 9603188-5, SE 9603189-3, SE 9603190-1, SE 9603191-9, SE 9603192-7, SE 9603193-5, SE 9603195-0, SE 9603196-8, SE 9603197-6 and SE 9603198-4, cost-effective and robust customer implementation with silicon, the MUSIC system described herein offers a that provides 26:2 or 13:2 Mbit/s asymmetric transmission over copper cable (local telephone networks.

The MUSIC system can be accessed using the network concept known as Fiber To The Node (FTTN), serving many users using optical fiber, each reaching a switch cabinet in the vicinity of the users' homes. Thus, the cable length specification for MUSIC can be successfully limited to 1300 meters.

The MUSIC system is mainly intended for the transmission of a signal with a high bit rate (26 Mbit/s) downstream to the subscriber, and a signal with a low bit rate (2 Mbit/s) from the subscriber. upstream, Figure 1 shows the MUSIC system. A network unit, NU, is connected to the fixed network through an optical fiber link, (FTTN). A network termination, NT, connected to a multimedia application, e.g. video-on-demand, is linked to the NU via copper cable. The MUSIC system supports a high data rate downstream and a much lower data rate upstream.

In the MUSIC system described here, two fixed bit rates (13:2 and 26:2 Mbit/s) are supported, where the (I) 13 lower bit rate 13:2 Mbit/s can be implemented as an additional option for use with poor, or extremely poor, copper cables.

For the network termination (NT), the connection consists of POTS, ISDN, ATM25 and Ethernet. All transmission protocols are supported by a set of standardized interfaces, (carried by) the data flow in the modem, except the POTS service which is filtered out passively, so that it is independent of (NU) modem status. The network unit terminates in the fixed network.

MUSIC separates the uplink and downlink spectra through passive filtering in the analog parts.

The version of MUSIC described here is intended to allow for future functional upgrades. For this reason, the FFT/IFFT block is designed to support full 506 641 20 IQ Un 16 functionality so that it can be reused in future system upgrades.

The MUSIC system is a DMT-based, multi-carrier VDSL system that uses discrete Fourier transform to create and demodulate individual carriers. This is illustrated in Figure 2, which shows two transceivers, each with a receiver, Rx, and a transmitter, Tx, connected to a twisted copper pair. Data is transmitted between the two transceivers using a plurality of carriers, some of which may not be used, e.g. when the channel quality is extremely poor. The number of bits transmitted on each of the carriers may also vary, depending on the channel quality.

A multicarrier modulation technique such as DMT effectively handles frequency-dependent losses and interference on twisted pair cable. In the MUSIC system, the available bandwidth of 10 MHz is divided into 1024 carriers, each 9.77 kHz wide. The assigned transmission power of the individual carriers depends on the interference power and transmission losses on each of the bands. Each carrier carries multilevel pulses that can represent up to 12 bits of data (4096 QAM). The signal-to-noise ratio (SNR) of the individual carrier is calculated at the receiver. If a carrier has a high SNR, up to 12 bits are placed on this carrier. For carriers with lower SNR values, fewer bits are placed on the carrier. Carriers affected by narrowband interference sources are switched off. Forward error correction and data interleaving are used to mitigate the effects of temporary bursts of impulse interference.

Asymmetric VDSL is implemented in this version of the MUSIC system, which means that the downstream speed is much higher than the upstream speed. Two fixed UI 20 30 506 641 17 downstream speeds (26/13 Mbit/s) are supported by the system; the selected speed depends on the current cable length (<1300 m) and/or the quality of the channel. The upstream speed is fixed at 2 Mbit/s. Different frequency bands can be used in the MUSIC system to separate the downstream channel from the upstream channel and both from POTS, see Figure 3.

Alternatively, other duplex methods can be used, e.g.

TDMA and/or a method where every other carrier path is dedicated to the downstream and upstream channel.

Figure 4 shows an overview of a MUSIC modem to which the present invention relates. The main hardware blocks are ADC and DAC, synchronization, Fourier transform processing, channel value calculation/equalization, symbol mapping and detection, interleaving encoding and decoding, network interface and system monitor.

The modem can be considered in the form of four principal functional blocks, namely: - the digital receiver unit; - the digital transmitter unit; - the analog input (front end); and - the system controller/PCI.

The analog input includes a hybrid transformer connected to an unshielded twisted pair and POTS. On the receiver side, the hybrid is connected, via a low-pass filter, LP, a programmable gain attenuator, PGA, to an analog-to-digital (A/D) converter. A voltage-controlled crystal oscillator, VCXO, is used to drive the analog-to-digital converter. On the transmitter side, the hybrid is connected to a digital-to-analog (D/A) converter via a low-pass filter. 506 641 20 h) Un 18 The digital receiver unit includes a fast Fourier transform and rescaling unit, FFT, connected, as shown in Figure 4, to a synchronization unit and a channel estimator. The channel estimator is connected via a symbol detection unit and a de-interleaving and decoding unit, to a bit management unit and from there to a network application interface.

The digital transmitter unit includes a bit handling unit connected to an inverse "fast Fourier" transform and scaling unit, IFFT, via a coding and interleaving unit and a symbol mapping unit.

The system control is connected to various functional units in the digital receiver and digital transmitter, and to the network application interface and a computer interface, as shown in Figure 4.

The network interface connects the higher protocol level to the modem's layer one functionality.

This block is responsible for providing the system with data at the configured bit rate, and adding "dummy frames" if required.

The data is then channel coded and interleaved. The MUSIC system described here uses a convolutional code combined with interleaving. Using a depth of multiple frames, a combined frequency/time interleaving is obtained (see later in this specification).

The symbol mapping block receives input data as an integer vector. This vector is mapped into the configured constellation depending on the current bit load value. The mapping unit uses a Gray coding scheme to reduce the probability of bit errors.

A real vector multiplication is the first step in the IFFT block. This causes the system to scale the output power level on each carrier. The IFFT block then performs a real 2048-point inverse FFT on the input data, which modulates each carrier. As a final step, an address "wrap around" is performed on the output data, where a copy of the first 128 samples is added to the end of the frame. This is called the cyclic prefix (CP).

The modulated signal goes to a DAC that converts the signal with a minimum true dynamic range of 84 dB. The DAC is clocked by the system sample clock at 20 MHz. To get rid of Nyquist "ghosts", the signal is LP filtered. The hybrid provides a balanced interface to the copper cable.

An overview of the signal path of the MUSIC transmitter and receiver is shown in Figure 4. The transmitter part uses the same hybrid design as the receiver.

At the receiving end, the splitter/hybrid transceiver separates the frequencies used by POTS, from 0 to 4 kHz, from the frequencies used by the system. It also extracts the low-level receive signal from the combined high-level transmit signal and the low-level receive signal.

To reduce Nyquist effects on the signal, the received analog signal is low-pass filtered before it is fed into the PGA (Programmable Gain Amplifier).

The PGA is necessary to get the best use of the dynamic range in the ADC. In this system, the dynamic range should be at least 66 dB. 506 641 (J: 20 30 20 After the signal is converted to digital format, the synchronization and FFT block receives the data.

In the synchronization block, a frame clock (for controlling the FFT buffers) and a control signal for the VCXO are generated.

Initially, the synchronization block retrieves the frame clock from the sampled signal. The frame clock is then used to calculate the frame synchronization value calculation and is passed to the VCXO feed back controller. The VCXO generates the sampling clock (20 MHz). (frame timing estimate) A sampling clock that is only controlled by the frame time estimate is not accurate enough in a DMT system.

Therefore, after the locking sequence, a dedicated pilot carrier is used to achieve high synchronization precision on the sampling clock.

A BSI signal is also extracted from the pilot carrier.

BSI is the Base Synchronization Interval timing signal used to synchronize the transmitter and receiver CCH communication.

One of the new aspects of the MUSIC system is the algorithm used by the synchronization block, which is discussed in more detail later in this specification.

A 2048-point real FFT is performed on the input frames in the FFT block. After this, rescaling is performed, based on the energy loading parameters, before the data is transferred to the next block.

The channel estimation and smoothing is performed on the output data from the FFT block. All data frames are used to estimate the channel characteristics. These are then used to compute a bit loading vector that determines the number of bits to be transmitted on each of the carriers. This information is then sent to the transmitter through the upstream control channel (CCH). 20 k) UI 506 641 21 In the symbol detection block, a "demapping" is performed for each carrier according to the bit loading mask.

After demapping, "de-interleaving" and "forward error correction" (FEC) are performed on the detected bit stream.

The data is then ready for the network/application interface block after bit manipulation. The dummy frames are removed in this block.

At the heart of the system, as shown in Figure 4, is the System Controller (SC). The SC is a general purpose processor that interfaces with and controls the various sub-blocks using a local PCI bus. The controller CPU is programmable. An external port is provided, through a JTAG interface on the motherboard (o:-board), to facilitate programming.

The main tasks of the SC are to control system startup and runtime behavior and to perform bit charge and energy charge calculations. It communicates with the remote side of the modem through a dedicated (CSE). changes in bit/energy charge and other control channel This channel carries data related to system signaling.

To obtain a cost-effective product for high volume use, the digital parts of the system must be based on at least two ASICs. Figure 5 shows how the system can be partitioned for chip design purposes.

One chip contains the FT/IFFT core. A second chip contains resynchronization, channel value calculation and equalization, symbol detection, and symbol mapping. The analog block and network interface block may be implemented on third and fourth chips, respectively. 506 641 30 22 The system parameters used by the MUSIC system described herein are shown in Tables 1 to 3 attached hereto.

VDSL systems operate in the spectrum from 0 to 40 MHz.

In this band, the MUSIC system described here occupies the lower 10 MHz, see Figure 6. A number of traditional bands exist in this spectrum, including POTS and some amateur radio bands. Different frequency bands are used in the MUSIC system described here to separate downstream from upstream channels. Since the MUSIC system described here uses 1024 carriers over 10 MHz, each carrier has a bandwidth of allocated by the DC level and the POTS service. The last 9.77 kHz, where the first two carriers are the carrier, is disabled because it is the Nyquist point.

This is primarily a question of immunity and radiation on the balanced copper pair. Other carrier waves (on radio bands) may need to be cancelled.

By passively filtering the POTS spectrum, this service can be made independent of the MUSIC system described here, runtime status, or power supply.

There are two ways to provide ISDN services for a MUSIC modem connection. One way is to allow the POTS (below) MUSIC frequency bands. This can be achieved by using a and the ISDN systems exist under a similar filtering process for ISDN band spectrum as for POTS. This filtering allows the service to be provided regardless of configuration.

The second way to provide ISDN is to let ISDN be a bearer service in the MUSIC system. This solution has the advantage in terms of spectrum efficiency. Using 1024 carriers over 10 MHz gives each carrier a bandwidth of 9.77 kHz. (150- 4)/9.77 = 5, the ISDN spectrum requires the allocation of these carriers. Depending on the channel characteristics, these five carriers must be chosen to have the best SNR in the system. For a standard connection, this gives 5*l00=500 kbit/s bandwidth.

The optimal solution is therefore to use the modem as a bearer, allocating only 64 kbit/s, compared to 500 kbit/s for the total bandwidth of the 64 kbit/s ISDN service.

The results of the attenuation and FEXT (Far End Cross Talk) measurements performed on a telecommunications operator's site showed that it is possible to achieve bit rates higher than 100 Mbit/s if the cable is shorter than 200-300 meters. For longer cables, the attenuation at higher frequencies limits the maximum bit rate.

For cables of around 500 meters, 40 Mbit/s can be achieved, and for a 1 km cable, 15-20 Mbit/s is realistic.

Another factor that reduces performance is EMC, which limits the power used. Some parts of the frequency domain may also need to be excluded.

A typical PSTN can be expected to have the following characteristics regarding impulse noise: - maximum duration 250 ps - median interval 67 ms - maximum peak amplitude 20 mV - most of the energy below 200 kHz - background noise -107 dBm/Hz The main source of synchronization in the system is the sampling clock. The reference for the sampling clock is located on the NU side and is common to all twisted copper pairs in a secondary cable.

The sampling clock frequency is 20 MHz at 10 ppm, with a phase jitter of less than 0.5 ns. 506 641 10 20 30 24 The sampling clock on the NT side is phase locked to the NU side. The read logic uses the frame timing estimation in a first stage, and then uses the pilot carrier to produce a fine adjustment of the read. The lock logic controls the frequency of a VCXO via an 18 bit digital to analog converter. The requirements for the VCXO are 20 MHz at 25 ppm range and 10 ppm/volt sensitivity. The final read shall have a precision of 1/100 sample, with a phase jitter of less than 0.5 ns.

The frame clock is 1/(2048 + 128) of the sampling clock and the frame clock, which is used for both transmission and reception, deviates in phase on both the NU and NT sides.

The frame clock for transmission on the NT side is the master and controls the start of the signal intervals, see Figure 7.

The receive frame clock on the NT side is obtained from the hardware function for the frame synchronization value calculation and controls the start of the frame sampling period, see Figure 7.

The frame clock for transmission on the NT side is the same as the frame clock for reception, but is one TA sample earlier in phase. TA is a parameter measured during system start-up on the NU side and is used to compensate for propagation delay on the copper conductor. This must be done to maintain orthogonality, over the copper conductor, of the sampled periods, both on the uplink and downlink. The frame clock for transmission on the NT side controls the start of the signal intervals, see Figure 7.

The frame clock for reception on the NU side is delayed by a number of sample clock cycles (TA) relative to the frame clock for transmission, after the TA calculation has been performed. The delay before the calculation of TA in the 20 IJ UI m -::> m fl3\ 4> _) 25 start-up sequence is determined by the frame timing estimation hardware function and the value is accessible to the controller.

The receive frame clock on the NOW side controls the start of the frame sampling period, see Figure 7.

The BSI clock is used to synchronize parameter changes between the sending and receiving sides. The parameters can be, for example, bit charge, energy charge or control channel frequency. The parameters are updated by the system controller, on both sides, before the BSI clock initiates the switch for the new set-up.

The BSI clock is 1/8192 of the frame clock. The uplink BSI clock is delayed by half a BSI clock cycle relative to the downlink BSI clock.

A short pseudo-random sequence on the pilot channel is used for BSI synchronization between the transmitting and receiving sides.

The cyclic prefix is an extension of the frames added by the FFT chip. To maintain orthogonality throughout the signaling period, the last 128 samples of the frame are copied and placed before the actual frame. This arrangement addresses problems associated with intersymbol interference caused by time dispersion.

It is important that the part of the signaling period that is sampled only on the receiving side overlaps a signaling period in the other direction, along the entire copper conductor. TA is used to optimize this overlap period. The maximum cable length is limited by TA = corresponding to 1280 meters (if the propagation delay is 5 ns/m). 128 samples = 6.4 us propagation delay. This 506 641 UI 26 The analog interface connects the received and transmitted digital data stream at the Cl chipset to the telephone line. There are also connections to the Tl chipset and the system controller for control purposes.

The analog interface is shown in Figure 8. The line is connected to a hybrid transformer that is also linked to the POTS. On the receiving side of the hybrid, the incoming signal goes through a low-pass filter and a programmable gain attenuator to an analog-to-digital converter, ADC, and from there to the Cl chipset. On the transmitting side of the hybrid, the outgoing digital signal is converted to analog by a digital-to-analog converter, DAC, and from there goes through a low-pass filter LP to the hybrid transformer. A voltage-controlled crystal oscillator, which drives both the ADC and DAC, synchronization block. is connected to the Tl chipset. An OFDM frame is a sum of sinusoidal carriers modulated in phase and amplitude and spaced in the frequency domain with a minimum separation distance between carriers. The assumption that the symbols within the frame are evenly distributed and uncorrelated with each other gives a signal in the time domain with an approximately normally distributed instantaneous amplitude. Thus, there is a small possibility that the input data may interact with each other to create pulses with very high peak levels.

However, the maximum amplitude must be limited to a lower amplitude than this so that there is a sufficient number of quantization levels in the DAC to handle (average) average signals. Even if the DAC has sufficient resolution to accommodate a high peak level in the transmitter, there are limitations on the receiver side (ADC). However, the consequences on the receiver side need not be as serious as they may seem. 20 25 30 506 641. 27 A short cable has lower attenuation in the high frequency range than a long cable, see Figure 9. This means that a temporary pulse can appear in the receiver almost unaffected by the cable characteristics. Therefore, a relatively large dynamic range is required in the receiver. However, this can be easily achieved because almost equal attenuations do not require a large dynamic range. The ADC needs to accommodate the range indicated in Figure 9 by the solid, thick, arrow-marked line.

However, the greater high-frequency attenuation of long cables requires a large dynamic range.

The high-frequency attenuation also means that it would take several large peaks from the transmitter to build up high amplitudes in the receiver; a case that is even less likely to occur at the ADC input than single peaks. The "headroom" can therefore be reduced and the ADC should accommodate the area marked by the thick, dashed arrow line in Figure 9.

In summary, performance can be optimized by carefully tuning the signal level at the receiver ADC depending on the cable length.

The splitter/hybrid has two main tasks, namely: - to split and combine the telephony signal (POTS) and VDSL signal frequency bands; and - to prevent the transmitted signal from appearing at the receiver on the same device by balancing the cable.

Since each transmission direction has its own frequency band, it is possible to optimize both sides in terms of their respective frequency bands to increase the overall performance. 506 641 UI 20 28 The purpose of the low-pass filter on the input signal is to reduce "aliasing" effects on interference above the frequency range used.

The low-pass filter on the output side reduces the transmitted power in the "stopband". These filters can be part of the splitter/hybrid module.

The best commercially available ADC today is the "Analog Devices AD9042" which has a signal-to-noise ratio of approximately 66 dB. It is recommended that either this ADC, or one with equivalent performance, be used.

For this description it is assumed that a DAC with 14 bit resolution is used.

The FFT and IFFT algorithms are built from 1024-point complex FFTs with data reorganization to allow the calculation of two real sequences on the same thread.

Consequently, each of the FFT and IFFT is effectively 2048 points. The hardware implementation is based on a radix-32 core that computes the result in three "transformations" (passes), see Figure 10.

The relationship between signal-to-noise ratio and resolution in the algorithm can be expressed as: sNR-22b'"'1 where b = number of bits, and v = 11 (number of effective radix-2 "transforms"). The solution for b gives 17 bits of resolution (based on ADC SNR), but since the ADC is not the only source of analog signal degradation, 16 bits of resolution in the algorithm should be sufficient to maintain resolution throughout the system.

VCXO:: generates the sampling frequency used in the NT part of the system. The control voltage is based on data from the synchronization unit. The clock frequency must be very LI: N lx) VI N 506 641 29 stable and phase locked to the NU reference clock to maintain orthogonality between symbols. (phase locked) To fully utilize the dynamic range of the ADC, a programmable attenuator must be inserted before the ADC.

The attenuation level is mainly a function of the cable length and can be determined by the "timing advance" value through the system controller.

Damping resolution and range, and the relationship between the timing advance value and the damping level, must be determined. Smoothing and variance values can also be used in the calculations for improved results.

In a DMT system, very precise synchronization between the transmitter and receiver is necessary, especially when carriers are modulated with large constellations.

In the embodiment described here, a new frame synchronization method is used that relies on correlation properties built into the structure of the received signal.

On the NU side, a fixed frequency crystal oscillator is used as a reference for generating the sampling clock. On the NT side, a sampling clock is generated by a VCXO (Voltage Controlled Crystal Oscillator) that is phase locked to the oscillator on the NU side. The VCXO is initially controlled by the frame timing estimate.

However, the resolution of the frame synchronization value calculation is not sufficient in the present application. Therefore, a dedicated pilot carrier is used, after a lock-in sequence, to achieve a very high accuracy of the sampling clock synchronization.

Due to the long symbol duration in a DMT system, intersymbol interference caused by channel time dispersion can be eliminated by using a guard interval as a prefix to each frame in the time domain. To maintain the orthogonality of the frames, the content of each prefix is a copy of the last part of the following frame, making the frames appear to be partially cyclic.

The synchronization method used to estimate frame synchronization exploits the high correlation that exists between a prefix and the corresponding part of a frame. By continuously correlating samples of the received signal, separated in time by the (known) frame length, the passage of a guard interval will cause a spike in the correlation estimate. Therefore, these spikes will have a known synchronization relationship to the frames and can be used to create a frame start signal. The principle is shown in Figure ll.

The correlator and peak time estimator use a system clock generated by a VCXO. This clock is divided by the total number of samples in a signal interval (a cyclic prefix and a frame), to create a signal with the same period as the correlation peaks. The phase deviation: (frame time deviation) signals between these two are used as input to a "feed-back controller" that adjusts the TCXO frequency to the correct sampling rate. However, the phase of this sampling clock is not accurate enough to be used in a DMT system. Therefore, the frame synchronization value calculation is mainly used for a lock-in operation. It is also used to monitor the frame synchronization to detect major deviations that will make resynchronization necessary.

W N 506 641 31 The correlation of the received data is calculated continuously. The time difference between the two signals is achieved by using a digital delay line of one frame length. The output of the delay line is multiplied by the undelayed signal and integrated (accumulated) over an interval corresponding to the length of the cyclic prefix. The output from the integrator is the estimate of the correlation function.

Since only the synchronization information of the correlation value calculation is used, a simplified estimator that uses only the symbol of the input data is implemented, reducing complexity compared to using the (sign). This hardware implementation has a strongly complete sample word length.

Computer simulations have shown that using synchronous averaging of several signal intervals reduces the variance of the frame synchronization value calculation. Due to the reduced data word length used in the multiplier part of the correlator, it is possible to implement such an averaging function immediately after the multiplier.

A block diagram showing the implementation of the correlator is shown in Figure 12. The incoming signal X(k) passes through a delay of N = 1024, i.e. one frame, and to a conjugator. The output from the delay and conjugator is then multiplied to produce a signal Y(k) which is fed to an accumulator which produces an output signal C(k). which is fed to an averager. The output from Z(kl delayed by L = 128 is subtracted. goes to a subtracter from This gives a The details of the averaging part of the correlator are shown in Figure 13. The averaging part comprises a series of delay elements combined with adders, as shown. The output signal can be expressed as 6 Z(k) = Z Y(k-iM) i=0 where Y(k) is the input signal and Z(k) is the output signal.

To make the averaging synchronous with the frame structure of the signal, the delays are equal to the signal interval.

A detector for finding the position of the maximum magnitude of the correlation function value calculation is shown in Figure 14. It is implemented using a register (#1) for the latest maximum value and a comparator.

The register contents and the correlation magnitude are compared, and each time a value greater than the register contents is encountered, the new value is stored in the register. The current value of a counter that counts sampling intervals (modulo signal interval) is also transferred to a second register (#2). This second register will contain an index to the maximum value encountered during this interval. This index (#3), and the contents of the first register are stored in a third register once per signal interval, (l#) divided by two (shift). (using shift). The index stored in register #3 is interpreted as the deviation between the counter value and the current synchronization of the input signal frames. The feedback controller will cause the average of this deviation to converge to zero. The counter value can then be used as a pointer to the signal interval. The frame synchronization clock is generated using this counter value to indicate the start of the frame.

Un 20 30 506 641 33 The value calculation of the complex representation of the pilot carrier in the frequency domain is performed using the FFT unit available in the system. The advantage of using this method is that the value calculation will be independent of the varying modulation of other carriers. This is due to the inherent orthogonality between the carriers. In order to achieve a value calculation with acceptably low variance, some averaging is necessary. This is performed using first order digital IIR filters.

Unfortunately, the value calculation is represented as a complex number in rectangular coordinates, so the argument is not directly available. In the feedback loop, it is necessary to detect very small argument deviations. Therefore, the resolution of the argument must be high. The feedback controller will cause the pilot carrier argument to converge towards zero. An approximation of the argument, which is linear only in a small region around zero, is then sufficient to achieve acceptable performance. A useful approximation that is "monotonic" in almost all four quadrants, and also easy to implement in digital logic, is described by the expression: A;NL[3{C}-(l-sgn¶{C}).K. ¶{C}.sgn.S{CH where C is the complex pilot carrier value calculation, M is a positive scaling constant, and K is a positive constant that affects the shape of the function (here K=2 is used).

The channel introduces phase shifts on the pilot carrier which can cause "misalignment" between the frame synchronization on the input signal and the zero pilot argument.

To eliminate this problem, the pilot carrier estimator also passes through the frequency domain equalizer (J: 20 IQ (JA 34 equalizer). The equalization parameter for this carrier is set during the start-up sequence, when the frame timing estimate has converged to its final value.

The selection of the pilot carrier will be fixed, but logic for selecting other carriers as pilot can also be provided. The feedback loop actually has two "controllers", each with its own input signal. The two controller outputs are added and fed via a D/A converter to the VCXO which generates the sampling clock. Both "controllers" are of the PI (Proportional and Integrating) type.

Figure 15 provides an overview of the signal paths. The received data in the time domain passes through the correlator and the peak position estimator to result in the frame clock. The complex pilot carrier in the frequency domain derived from the equalizer is fed to a pilot argument estimator, the output of which is fed to "feedback controllers" which also receive the output of the peak estimator. The output of the "feedback controllers" is then fed to a D/A converter to provide a signal used to control the VCXO.

During the start sequence, only the frame synchronization controller is active. When the frame synchronization has stabilized, the pilot carrier smoothing parameter is calculated and set (by the SC). Updating of this parameter is suppressed. After this, the averager of the argument estimator is given sufficient settling time. This is done only once, and further changes to the smoothing parameter are made.

Finally, the frame synchronization controller is stopped and the pilot argument controller is activated. When the frame synchronization controller is stopped, its last output value is locked so that the VCXO frequency remains close to its final value.

The pilot carrier is also used for the transmission of synchronization information for the Base Synchronization Interval (BSI). The carrier argument is normally assumed to be constant.

A short pattern is BPSK modulated onto the carrier using phases 0 and n, leaving the carrier at phase 0 for the remainder of the BSI interval. If this pattern is only a fraction ( the pilot carrier argument value calculation is negligible. A correlator is used to detect the pattern and provide the synchronization signal for the BSI.

The "System Controller" (SC) must have read access, for synchronization lock detection and for monitoring purposes, to registers holding the frame time deviation estimator and the pilot argument approximation.

To handle the initial smoothing of the pilot carrier, it is necessary for the SC to read the averaged complex representation of the carrier and write to the smoothing parameter memory.

An offset register to determine the relative synchronization between the input frames and the frame start signal is necessary and must be writable from the SC. This is used on the NT side.

The detected BSI event signals, for both reception and transmission, shall be connected to the SC as interrupt inputs.

Alternatively, the pilot carrier can be recovered from the signal in the time domain, using a bandpass filter, and used directly for phase locking of a sampling clock oscillator as described here. The frequency plane method, 506 641 .- Un 20 36 described, has the advantage that the pilot carrier estimator is independent of the modulation of the other carriers, depending on the orthogonality. Another frame synchronization method would depend on introducing a known pattern into certain frames.

This would reduce system capacity.

The frame length and the length of the cyclic prefixes are fixed in the embodiment described here. The method, as described above, is designed to operate in a feedback loop with a VCXO. In a device using a fixed sampling clock oscillator, the implementation of the frame synchronization estimator needs to be modified slightly. It is important that the VCXO has very low phase noise, since the feedback loop is too slow to compensate for such noise.

A discrete multitone (DMT) system modulates N complex data symbols onto N carriers (here we use N=1024 carriers). This mapping is calculated as an inverse discrete Fourier transform using the Inverse Fourier Transform (IFFT).

The Nth carrier paths of an FFT.

Fast Fourier Transform" In the receiver, the demodulation described here, FFT and IFFT are performed by 16, or (cores), in different phases. This process is shown In the modem, the same device, using the same base (radix) 32 "cores" schematically in Figure 16.

The main operation is divided into frames with lengths of 2048 real, this unit performs an FFT, or 1024 complex values.

IFFT, (descaling), and addition of cyclic prefix.

For each frame scaling, rescaling FFT and IFFT calculate 2048 point real FFTs and work with a minimum of 16 bit arithmetic.

For the network terminal side, (NT), there is a requirement for synchronization between the input frame start and the IFFT output start. (A synchronization between the upstream and downstream carriers). The transmitter must be able to start transmitting a frame before it starts receiving a frame, so-called "timing advance".

A scaling should be provided before IFFT.

This scaling is a multiplication between the real q-coefficients stored in this unit, and the input values from the symbol mapper (SM). The coefficients are 16 bits each.

The coefficient memory consists of two banks of the same (16X1024 bit). Switching is enabled by the size of the second bank being updated. One bank is used while the other is updated. One bank is used while the other is updated. Switching is enabled by the size of the second bank being updated. One bank is used while the other is updated. One bank is used while the other is updated. Switching is enabled by the size of the second bank being updated. One bank is used while the other is updated. One bank is used while the other is updated. One bank is used while the other is updated. The second bank

After the FFT, rescaling must be performed before the data is transferred for smoothing and symbol detection.

This rescaling is a multiplication by the inverse value of the squint values. The coefficients are represented by 16 bits.

An exponent (resulting in a "post shift") of 4 bits may also be needed to maintain precision.

The coefficient memory consists of two banks of the same ((1e_4)x1o24 bit). The other is updated. Switching is enabled by a PCI- size One bank is used while the command is executed at the next BSI.

At the beginning of each frame, a cyclic prefix is added.

This process is shown schematically in Figure 17. The insertion of a cyclic prefix eliminates intersymbol interference (ISI), and preserves orthogonality between the tones, resulting in a simple input/output relationship that allows each carrier to be considered a separate channel.

This cyclic prefix consists of a repetition of the last part of the frame. 506 Un 20 30 641 38 Assuming that timing advance is used and the maximum cable length is 1300 m, a cyclic prefix of 128 samples will be needed. Thus, the output data for each frame will be samples: l920, l92l,...,2046, 2047, 0,l,2, 2046, 2047 For each of the above components there is a FIFO as an interface to the external world with FFT/IFFT input and output memories. Thus there are 4 FIFOs in total.

It is recommended that the FIFOs that interface to the analog side have a size of 384 words (16 bits) and the FIFOs that interface to Tl chips have a size of 448 words (32 bits).

Another DMT technique that does not use Fourier transform is the Discrete Wavelet Multi-tone Transform (DWMT). This method has been submitted to the ADSL transformation standardization committee, which rejected it.

The precision needed in this technique depends on the required dynamic range, which in turn is determined by the analog components (especially the DAC). The FIFO size will depend on clock speed differences and the amount of "timing advance" used. The use of clipping is a compromise between dynamic range (quantization noise) and clipping noise.

Channel estimation is performed using a "decision directed" method, since all data frames are then used to update the channel model. Known data frames are only necessary at startup. Under certain circumstances, interference on the channel can be estimated using all data frames. This is important for early detection of changes in channel transmission quality. The basic principle of "decision directed" estimation is that differences between received data and known transmitted data are used to update a channel model. At a certain stage of this process, the channel model is accurate enough to be used for smoothing the received data, and the detector will produce correct data. This output data can then be used in the same way as the known data for further updating the channel model. Therefore, the predefined data frames are no longer necessary and random data transmitted through the channel is used instead.

By using the data taken after the equalizer as input, and the data after the detector as the second input, an adaptive update algorithm can be designed. It modifies the equalizer parameters in small steps in such a direction that the equalizer converges to a model of the "inverse" channel. (inverse) Figure 18 shows a block diagram of such a system. The frequency-domain input data enters the equalizer and is multiplied by the output of an equalizer parameter update unit, EQ. The resulting signal, U, then goes to a detector (vantizer), whose output is Y. Y then goes to a U and Y also goes to an input of the symbol decoder update unit which produces a decoded data bit stream. for equalizer parameters and to a variance estimator.

The output of the variance estimator is W.

An adaptive algorithm for calculating the values of the equalization parameters (EQ), which uses the equalized data (U) and the quantized data (Y) as input data, is described by the following equation: P EQk+l = EQk + .EQk.Uk'. (Yk' Uk) Iukiz where u is a positive constant (u << 1), which affects the adaptation dynamics. A smaller value 506 641 Un 20 fx) LI: 40 gives a slower adaptation than a larger value, but it also gives a greater insensitivity when there are disturbances in the input signals.

For implementation reasons, the division shown in the equation should be avoided. The expression p/IUJZ has too large a dynamic range to be replaced by a constant. However, it is possible to quantize this expression in a logarithmic manner as shown below: Iz 2-incege:<2.1og2|uxIJ+ 1n:eger<1°g2p> of P/'Uk The exponent in the above expression can be produced by using the absolute value of Uk as input to a binary priority encoder and changing the sign (negating) on the output.

Since the expression is an integer power of two, the multiplication in the algorithm is implemented using a "barrel shifter".

The interference variance on each of the carriers is calculated using the standard method of integrating the squared deviations from a mean. In this case, each quantized value, Y, is used as the mean of the range of data values, U, that are quantized to that Y. This method assumes that the symbol error rate is low enough for each data value to be associated with the correct mean. However, if appropriate constellations are chosen for the different carriers, this condition is satisfied.

Figure 18 shows the variance estimator as part of the system. The algorithm used for the value calculation is described by the following equation; WN = (1-s).wk+s.|Yk_Uk|2 The integration is here replaced by an exponentially weighted average filter. The parameter S is a small, positive constant (6 << 1) that affects the dynamic LJ» 20 IJ LJ| 506 641 41 properties of the filter. This is not a critical parameter, and choosing s from integer powers of two will be sufficient.

If a value of s is chosen that provides a good variance estimator, the algorithm will not be able to detect sudden changes in the interference level.

Therefore, a separate algorithm, working in parallel with the variance estimator, may be necessary for this task.

The "System Controller" must have both read and write access to the memory that holds the smoothing parameters.

Initialization of the parameters is necessary at startup. Monitoring of the parameters is also necessary to detect when they have settled sufficiently close to their final values.

The channel variance memory must be available for System Controller read operations. Initializing this memory to all zeros can be coupled with a system reset.

The parameters that affect the dynamics of the estimators must be available for writing from the System Controller.

The method described here assumes a specific start-up sequence, both for the channel and interference value calculations. During normal execution, it is dependent on an appropriate choice of bit loading that provides a sufficiently low symbol error rate.

It is important that the smoothing parameters are initialized to unity at the beginning of the startup sequence, as the input to the update algorithm passes through the smoothing.

The update algorithm is sensitive to scaling changes in the data path. 506 641 42 Any change in scaling in the transmitter must be compensated for in the receiver. This also requires special care when using the analog gain control on the input side of the receiver.

The symbol mapper (encoder) maps a number of bits to a complex number (I, Q) that indirectly determines the phase and amplitude of a carrier. The mapping of all values of a certain bit length is called a constellation, and is shown in Figure 19. The detection is the inverse function, i.e. from a complex value the value of the bits transmitted on the carrier is determined. The number of bits transmitted on a certain carrier is determined by the bit loading factor for this.

The design of a specific constellation is aimed at moving each point as far as possible from all other points. At the same time, the average energy should be as low as possible. Another restriction is that the mapping and detection units should be as simple as possible. However, the decision regarding which constellation to use will affect not only the symbol mapping and detection units, but also the bit loading and possibly the adaptive equalizer.

For a given carrier, the encoder selects an odd integer point (I, Q) (square-grid constellation) based on the b-bits (vbllväq, from the square-grid constellation _'vLv2). For the sake of simplicity in the description, these b-bits are identified by an integer label whose binary representation for b=2 3 correspondingly is (vb1'vbQ,___,vLv2). For example, the four constellation points O, 1, 2, (v.v2) are "labeled" = (0,0), (0,1), (l,O). (1,1), respectively.

LI: 20 30 506 641 43 For even values of b, the integer values of I and Q for the constellation point (I, Q) are determined from the b bits (vbl vb L U_,v1j@) as follows. Divide V into VI = (vbl|vb3V_H lvl) and VQ = (vb2,v¿4,___,vo). Then apply the inverse Gray code to VI and VQ. This gives I and Q as I = 2GraW(VI) + 1, and Q=2Graw(VQ) + 1.

- Figure L: shows how the binary pattern for V maps onto I and Q when b = 6.

Before these values are sent to the IFFT, they are normalized by shifting so that the "msb" of these numbers becomes the "msb" of the output (16 - [b/2] steps left).

For a given carrier, the decoder uses a constellation point (I, Q) to determine the b-bits (vbfli Vb-z, _'vLv¿ For the sake of simplicity in the description, these b-bits are identified by an integer label whose binary representation is (vbllvbq, lr-llvz).

It is assumed that the values of I and Q are limited by saturation to the range (X, Y). To determine V, the values I = Ti1s,i14, ,i1,io)f and Q = (qiaqn, ,q1,qo)f are Gray-encoded and then combined into V as V = (gißlgqß gin gqM,.....), where the upper b-bits are valid.

The number of bits each carrier conveys depends on their (SNR).

The signal-to-noise ratio is calculated for each carrier in the respective receiver. Based on the signal-to-noise ratios, bit loading factors are calculated for each carrier. Thus, the number of bits each carrier should transmit per transmitted symbol is determined.

These bit loading factors are calculated in an initial training session and can be updated if required.

The MUSIC system uses 2-dimensional "Quadrature 506 Un 20 25 30 35 641 44 Amplitude Modulation" (QAM) on each carrier, with bit loading factors varying from 0-12 bits.

The number of bits transmitted on each carrier can be expressed by: SNRi ) Bi = bi + logz (L)= logz (1 + (1) l' where F, the SNR gap, depends on modulation, possible coding and a system margin, and L is the constellation expansion depending on the extra bits needed for coding.

Using QAM constellations and some form of coding gives: [QflPs/MJZ |- = ___:_____ - yd + ymargin 3 (dB) (2) where Ps is the desired symbol error rate, yd is the "gain of coding" in the system, nßmnï is the system margin. The system margin is a factor used to compensate for non-modeled losses, impulse disturbances, etc. Equation (1) gives a bit loading factor with infinite granularity.

The bit loading factors are rounded to give the supported factors (0 - 12 bit).

The rounding procedure will reduce the performance of the DMT system. If the energy distribution is allowed to vary, energy loading factors can be calculated for each carrier. This provides the possibility to tune the energy so that (1) results in a bit loading factor supported by the system. Tuning gives; (Qi-l)f SNR.

E-_ 2 1 (3) UI 10 20 |~J Un 506 641 45 However, this can result in very large differences between carrier energies. In an environment with several different DMT systems, strange effects can occur if the different energies are allowed to vary too much.

The far-end crosstalk (FEXT) will vary considerably in such an environment, and some DMT systems may draw the full capacity of the cable. To prevent these effects, only small changes in the carrier energies can be allowed. Another limiting factor is the maximum energy allowed on each carrier.

The input to the bit loading algorithm will depend on the selected frequency domain equalizer. If an adaptive DFE is used, the SNR is obtained by: sNRi=wi (4) where Wi is the estimated interference variance as described above.

For each carrier, a bit loading factor and an energy loading factor are calculated. The bit loading factors can be represented by 3 bits, but to prepare the system also for odd bit loading factors, 4 bits are recommended. For energy loading, n bits are used to give 2" - l possible factors.

The implementation of the calculations of bit loading and energy loading factors can be done in four steps as shown in Figure 20. To achieve a given bit rate, a required SNR can be calculated and the system margin can be adjusted to achieve the desired bit rate. The process, illustrated in Figure 20, includes the following steps: - First, the SNR is calculated using (4).

- In the second step, four comparisons are performed, that is, one for each of the four bits 506 641 10 20 IJ (Ju 30 46 representing the bit loading factor.

The thresholds depend on L and F, and can be pre-calculated. The first comparison determines whether the bit loading factor is greater than 7, and the result of this comparison determines the first of the four bits representing the bit loading factor; it also determines the threshold for the next comparison. In a similar way, this comparison determines the second bit and the threshold for the next comparison. After the four comparisons, the bit loading factor is determined.

- The third step is to calculate the scaling factor for the transmitted energy so that the channel is used more efficiently. The energy is scaled according to equation (3).

- Finally, the scaling factor is quantized to n bits.

It should be noted that to implement a constant energy charging system, only the first two steps are necessary.

The energy loading and shifting performed for normalization in the symbol map determine the scaling and rescaling factors sent to the IFFT/FFT processor.

As previously mentioned, bit loading is currently used in so-called discrete multitone, and OFDM transmission systems. Information regarding channel characteristics, such as bit loading and energy loading information, is transmitted as a sequence of N numbers, where N is the number of subcarriers.

Thus, when using discrete multitone (DMT) systems, it is necessary to transmit information regarding how the channel characteristics affect the transmission, for example the number of bits to be transmitted per symbol. When using a large number of subcarriers, a relatively large amount of information regarding channel characteristics must be transmitted. It is therefore a requirement that such systems provide an efficient method for transmitting such information.

Since a typical subcarrier has characteristics similar to those of the adjacent subcarriers, an efficient method for transmitting channel information is to transmit the channel information as a sequence of a number of groups, each group containing information regarding the number of subcarriers having the same value and the current value of such subcarriers.

Thus, in accordance with the present invention, a multicarrier system, e.g. the MUSIC system in Figure 1 of the accompanying figures, in which channel information is transmitted between two transceivers using a plurality of subcarriers, is arranged in a manner whereby each symbol, subcarrier, has a parameter associated therewith, and the transceivers, or more precisely, the modems associated therewith, are adapted to transmit the channel information as a sequence of a number of groups, each of which contains information regarding the number of adjacent subcarriers having the same value as the parameter, together with the current value of the parameter. The parameter, which may have a plurality of discrete values, may be a bit-load value, or a QAM constellation identifier.

In a DMT system, such as the MUSIC system, the number of subcarriers, N, as shown in Figure 33 of the accompanying figures, may be equal to 1024 and there may be 50 plateaus, i.e. the channel information may be transmitted, according to the present invention, as a sequence of 50 groups. 506 641 U: 10 20 IQ Un 48 if it is assumed that there are 1024 subcarriers, that the number of groups is equal to 50, and that Thus, a modem needs to transmit the number of bits that each channel is to use (0 to 15, i.e. 4 bits), it will be immediately apparent from the following table that, by using the method of the present invention, it will be possible to effect a saving in transmission capacity, since considerably less information needs to be transmitted. âändâ Typical Method 1024 x 4 = 4096 100% Present 50 x (4 + 10) = 700 17% Invention In determining the number of groups, or plateaus, that can be used to achieve the benefits of the present invention, the following analysis should be considered.

If it is assumed that: - the number of discrete values of the parameter referred to above is > 2", but S 2°4, - the number of subcarriers N is > 2m, but S Zmfl, - the number of levels is P, then the transmitted amount of data, according to the method of the present invention, will be reduced if: P (m + n) < N x n Lll 25 30 49 If we consider the case where N = 1024 subcarriers and there are 15 parameter values, i.e. where m = 10, and n = 4, then it follows from the above equation that: P (4 + 10) < 1024 X 4 = 4096 i.e., the number given in the table above for a typical method.

In the above case, which can be considered as the break even point, i.e. no saving in transmission time, the number of levels P will be as follows: P = 4094/14 = 292 levels Obviously, it will be advantageous to use the method of the present invention in cases where P < 200, and especially where P < 100.

For example, where P is equal to 200, the bits to be transmitted will be 2,800, i.e. a saving of approximately 32% compared to a typical method. Regarding the case where 100 levels are used, there will be a saving of approximately 66%.

It will be quite apparent from the foregoing description that the method of the present invention can be used by any modem which is arranged to transmit information regarding how the capacity of a channel is to be used, and which uses OFDM, or similar techniques, for distributing such information on a number of subcarriers. 506 641 (J: 30 50 The purpose of channel coding is to reduce the bit error rate. The type of coding which should be used depends on the error pattern characteristics. Expected sources of error include random noise (which induces random bit errors), impulse noise (which induces burst errors) and clipping (which induces burst errors).

Errors caused by impulse interference mainly affect one or two bits per carrier. The probability of a single bit error on a carrier is always higher than the probability of 2 bit errors, which in turn is higher than the probability of 3 bit errors, and so on. This depends on the way in which the bits in the symbol are encoded (i.e. Gray encoding).

All coding depends on synchronization to determine the start bit of the codewords and/or interleaving blocks. In systems such as the MUSIC modem, simple dead reckoning will suffice, since a data flow slip can never occur without loss of frame synchronization, or misalignment of bit loading. These errors necessitate a partial, or complete, system restart.

The channel coding will also include "interleaving" to increase the ability to correct burst errors.

"InterLeaving" should be as deep as possible to obtain optimal performance. The limiting factor on depth is the time distortion introduced into the system. .4 The distinction between time and frequency interleaving is of little importance since the coding and interleaving function is not sensitive to frame boundaries.

Un 10 20 IQ UI 506 641 51 Reed-Solomon codes have the disadvantage that they are essentially burst error correction over a small number of bits (usually eight), a so-called symbol. Burst errors from impulse noise generally introduce a "single-bit error" in some of the symbols. To exploit the advantages of Reed Solomon codes, the most "error prone" bits must be concentrated in one, or a few, of the Reed-Solomon symbols.

The system margin in itself is a type of coding that uses the margin of each carrier as the symbol redundancy. This redundancy per symbol must be converted into a "shared" larger number of symbols to handle burst errors. The higher redundancy that can be used by a coding rate that this introduces can be used by certain types of convolutional codes.

Use of a convolutional code combined with "soft" information is therefore the optimal solution for a system with MUSIC channel characteristics.

The convolutional code should be combined with interleaving.

It is possible to use a "top-level" Reed-Solomon code, or some other burst error correcting code, e.g. Fire codes, to detect/correct the remaining bit errors.

This is especially useful because these errors occur in bursts as a result of the decoding of the convolutional code.

The "System Controller" is based on a "micro controller", or signal processor, depending on capacity requirements. For the MUSIC system, the processor can be placed externally. A PCI bus interface is used to connect the System Controller and the various ASICS that make up the modem.

The function of the System Controller is shown schematically in Figure 21, which shows the paths of interaction over a PCI bus, between the System Controller and the FFT chipset, the data mapping and detection chipset, and the encoding and decoding chipset. Functions performed by the System Controller are: 506 641 Un 20 52 - handling of "Control Channel Signalling"; - calculation of bit loading and energy loading factors; - updating of system parameters in real time; and - system monitoring.

The System Controller, which is used for the modem described here, is programmable and accessible through a JTAG interface on the motherboard (on-board).

As shown in Figure 22, in a modem context with modems as described here, the two data paths operate independently of each other on the same physical copper cable, (NU) (NT) on the user side. Both the transmitter Tx terminates in the network device on the network side, and the network termination and receiver Rx are controlled by the System Controller.

System: The controller calculates and updates, after startup, the auxiliary charging and energy charging factors.

This update must be done simultaneously starting from the same frame, on both the sender and receiver sides.

The calculations are made and the update is initiated on the receiving side. The control channel, combined with the ESI clock, is used to ensure the synchronization of the update.

The System Controller also supervises the system. Indications of system errors include the control channel starting to indicate errors, or receiving too many errors from the decoding channel unit.

The System Controller can initiate a reboot at various levels; for example, returning to "idle mode", or performing a full reboot. 20 506 641 53 The control channel is a selected carrier that is used only for signaling between the two modems. The constellation on the carrier is initially 4 QAM and the data rate is approximately 16 kbit/s. The bit load can be changed to any other constellation to increase the data rate.

The control channel protocol is partly based on HDLC for the physical layer. This means that messages are packaged as a number of octets using a flag sequence and bit-stuffing. A 16-bit frame check sequence ensures that each message is received correctly.

"Flag-sequence", "bit-stuffing" and "frame check sequence" are handled in hardware on the mapping and detection chipset. The content of the messages is handled by the System Controller.

The maximum message length is limited to 64 octets depending on the size of the buffers on the mapping and detection chipsets.

Higher-level protocols may be based in part on CCITT Q.921 recommendations.

In MUSIC modem SC, several different vectors are handled; these are shown schematically in Figure 23.

For the transmitter part there is the bit loading and energy scaling vector. Correspondingly on the receiver side there is the bit loading, rescaling and smoothing vector.

As previously described, the pilot carrier provides transmitter/receiver synchronization by transmitting and detecting a specific pattern. This clock is used by the system to synchronize changes in the transmitter and receiver vectors.

The time between pilot synchronization patterns is called the Base Synchronization Interval (BSI) and is determined by the system response time, as shown in Figure 24.

This BSI is hardware dependent. Its length will not change, as the response time always remains the same.

When the system is up and running, synchronization will exist between the uplink transmitter and receiver, through the "base (BSI-U) see Figure 25. These BSIs are of exact sync interval uplink" (Bsï-D), the same length but are shifted by half a BSI interval. and the "base sync interval downlink" SC at the NU, or NT, will receive interrupts for both BSI-U and BSI-D.

For the NU, there will be a transmit BSI-D interruption and a receive BSI-U interruption. By shifting BSI-U by BSI/2, over the BSI period, the SC charge will be better distributed. The bit charge vector provides the system with the modulation pattern for each carrier. This is a vector that needs to be held and updated at exactly the same time on the transmitter and receiver sides to provide an error-free connection. By using the BSI, the vector changes synchronously on the receiver and transmitter sides.

The bit loading factors, constellations used on each carrier, are handled by two receive and two transmit memories on the mapping and detection chip. Each of the four memories contains a 4-bit word for each carrier (1024x4).

The System Controller designates which of the memories should be used for transmitting and which should be used for receiving after the start of the next BSI interval.

U: 20 IQ KJ! 01 CD 0\ ~J\ F> ...à 55 The bit loading factor can have values between 0 and 12, where 0 indicates an unused carrier; 1-12 indicates the number of bits in the constellation (e.g. 2 for 4QAM, 4 for 16QAM, 10 for 1024 QAM).

The energy vector holds information about how the carriers are scaled/rescaled in terms of energy. This is a vector that needs to be updated synchronously, otherwise it will generate a distorted channel value calculation and bit errors.

The scaling vector will also be used for canceled (cancelled) as a pattern (mask) carriers.

Scaling of the different carriers on the transmitter side is handled by a memory area on the FFT chipset. The memory consists of a 16-bit word for each carrier (1024 x 16). These values are multiplied by the vector for each carrier in the frequency domain (I and Q are multiplied by the value separately).

The memory is duplicated to guarantee a synchronous update. The System Controller designates which of the two memories will be used from the start of the next BSI interval. (duplicated) at the receiver side to rescale the carriers before A corresponding memory is implemented at symbol detection. If these memories contain a complex value for each carrier (32 bits/carrier), only the I value will be used for rescaling.

The scaling and rescaling factors have values between 0.5 and 2.0. The value 0 is used for carrier weight cancellation.

The smoothing vector is used to smooth the received frame according to the channel characteristics. This vector is updated periodically, independently of the other side, when the channel value calculation is calculated by the receiver. 506 641 56 Depending on the specific transmission characteristics of the carrier, it will be assigned one of the following modes: - normal carrier - this carrier transmits data according to the calculated bit load value and is "transmitter scaled" and "receiver rescaled"; - null carrier - no energy is transmitted on this frequency and the scaling vector is therefore set to zero; or 10 - bad carrier; the SNR is too low to transmit any data and the bit load is therefore set to zero.

In carrier mode (CM1), the system operates normally.

The receiver continuously equalizes the channel.

Smoothing changes are made for each new value calculation. Using the 1> characteristic, the SC calculates the optimal bit loading factor. This value is transmitted to the transmitter using the CCE, and a synchronous change is performed.

In carrier mode 2 (CM2), the energy scaling/rescaling value is set to 0 to disable all output/input energy. The bit load vector value is also set to zero to indicate that the carrier is disabled. No channel value calculation can be done for this carrier.

In carrier mode 3 (CM3), the receiver has calculated a zero for the bit loading factor. On the transmitter side, this means that no data can be transmitted, and therefore no channel value calculation can be made at the receiver. To avoid this, the corresponding carrier value is sent from the synchronization frame and allows a channel value calculation to be made at the receiver. The scaling/rescaling value can be used to lower the output power.

The carrier modems are presented in Table 4. 10 506 641 57 The basic functionality of the "startup" sequence in the system, i.e. "cold" and "warm" (boot), is discussed. start will now be Initially, the power supply in the system is considered to be off at one or both ends, NU and NT. This occurs if power supply is lost through a power failure, or by the user unplugging the NT equipment. The most important thing to consider during "start-up" is, besides the connection function, to minimize the interference level for other modems using neighboring cables.

The different frame types used by the system are discussed below. 1. The synchronization frame is used for channel value calculation. This frame contains a specific modulation pattern for each carrier and thus enables easy channel value calculation. By having the modulation pattern described by a "random sequence", the cross-correlation within the frame is kept low, so that the frame correlation, which is used for synchronization, is improved. 2. Data frame 1, (F1), conveys "random data" on all carriers, except on four predefined carriers that transmit the control channel (CCH) in parallel. It is used at "start-up" when the CCH carrier is undetermined and enables the receiver to select the least disturbed carrier, thereby guaranteeing the CCH connection.

(DF2 carriers except one, 3. Data frame 2 conveys "random data" on all carriers of the control channel (CCH). It is used when the CSE carrier has been determined, and the bit loading factors have not yet been set. 506 641 lJl 20 I~J (Jl 30 58 (DF3) bit loading function to maximize bandwidth. 4. Data frame 3 conveys data and uses One carrier is always dedicated to the control channel (CCH).

The system uses a special frame sequence, shown in Figure 26, at start-up and in idle mode, called the Start-Up Sequence.

The SUS can be composed by using the different data frames, DF1 and DF2, which are consequently called SUS1 and SUS2. channel value calculation.

In the SUS frame sequence, the synchronization frames are used for After startup, the synchronization frames are replaced with data frames, as shown in Figure 27, and the channel value calculation process switches from using synchronization frames to using the data frame. The type of data frame for this sequence is DF3.

At system startup, neither side of the modem, NU and NT, transmits any energy over the copper pair.

The default setting for either side at this stage is to power the receiver, leaving the transmitter "dead".

The receiver, on each side, attempts to perform a frame correlation to detect a frame start. This correlation is run through a threshold function that gives the receiver a distinct indication of when the other side starts transmitting. It is this indication that serves as a "wake-up" signal.

The "Wake-up" signal is used only by the NT side. If the decision to start up is made on the NU side, the system goes directly to the set-up sequence described below.

This part of the startup procedure times out if a transition to the setup sequence is not detected.

From 20 30 506 641. 59 The basic modem wake-up signaling is shown in Figure 28. Initially, both modems search for frame correlation. One of the modems, on the right in Figure 28, sends a wake-up signal in the form of a SUS1. The other modem detects frame correlation and starts the setup sequence described below.

Once the "wake-up" state has been passed, the network side (NU) initiates the setup sequence.

The set-up sequence will now be processed. This set-up sequence starts after the network side has detected a "wake-up" signal, or the network initiates the set-up.

The first step in the setup sequence is shown in starts NU to transmit SUS1- The NU repeatedly transmits a "timing advance" Figure 29. In this phase the pattern.

(TA) setting, with TA = 0, on the CCH. The master clock in the system is now the NU transmitter frame and the sample clock in NU.

The pilot is broadcast continuously.

The NT receiver side, which is looking for frame correlation, detects frames and can retrieve the frame and sample clock. It now starts the channel value calculation which at the current rate of synchronization frames makes an accurate value calculation within 300 ms. Using this value calculation, the receiver starts polling the predefined CCH carriers and, on message receive, selects this carrier for the CCH. The NT transmitter now starts with TA = CCH carrier for each received TA selection message, O for local synchronization and sends acknowledgement (ack.) on repeating the received TA value. It also shifts the outgoing pilot by ESI/2 from the incoming pilot, so When the NU detects the frame correlation, the transition to step 2 is made by distributing the SC load over time. the setup sequence. 506 641 60 Thus, step 1 of the setup sequence begins with the transmitter, in the network unit modem, transmitting a SUS1 and a TA message with TA = 0 at periodic intervals. Upon receipt of this, the receiver in the terminal modem will: UI - perform frame correlation and recover the frame clock; - begin FFT processing; - enable pilot decoding; - recover the BSI; 10 - enable channel value calculation; - select a CCH; and - decode the TA selection message.

The transmitter in the terminal unit then sends an acknowledgement (ack.), SUS1, a TA =0 message and a pilot shifted 1: with BSI/2. The receiver in the network unit waits for frame correlation.

Step 2 of the setup sequence, see Figure 30, begins with the NOW side now calculating a "timing advance" (TA) value. The CCH message is changed to the new, corrected TA value.

When the NT side receives the new TA value, it changes the local synchronization and continues to send the acknowledgement message, with a new TA value, for each TA selection message. k) Un In the NU receiver, the frame clock is lost, due to the NT transmitter changing the frame clock, and the unit needs to re-correlate. After the frame clock is recovered, the CCH is decoded and, upon detection of an acknowledgement containing the new TA value, the system terminates the TA message and goes to the third step of the setup sequence.

Thus, step 2 of the setup sequence starts with the transmitter in the network unit, NU, sending a TA message containing the correct TA, say X, together with a SUS1, sent from the transmitter terminal. In response to the SUSI and TA = 0 message, the Terminal Unit, NT: - receives the new TA message; - corrects the outgoing frame clock; and - sends an acknowledgement SUS1 and TA = X.

The network unit, NOW: - performs frame correlation; - recovers the frame clock; - starts FFT data processing; - enables pilot decoding; - recovers the BSI; - enables channel value calculation; - selects a CCH; and decodes the message.

The last setup sequence, step 3, see Figure 31, handles the CCH selection for uplink and downlink. For the uplink, the NU receiver has selected the most suitable carrier and sends a CCH message containing this selection to the NT side. The message is sent repeatedly until it receives an acknowledgment (ack.). 506 641 62 On the NT side, the receiver decodes the CCH message and terminates SUS1 and transmits a SUS2, i.e. terminates _ parallel CCH transmission by only transmitting the CCH on the selected carrier.

The uplink CCH bearer has now been configured. For the Un downlink, the same steps are performed in parallel, initiated by the NT side after receiving the first CCH selection message from the NU.

Thus, in step 3, the network unit will: - transmit the selected CCH for the uplink; - wait for an acknowledgement; and - terminate the CCH message.

The terminal unit: - receives the CCH selection for the uplink; - terminates SUS1; - starts SUS2; and - acknowledges each CCH selection.

The network unit: receives the downlink CCH selection; terminates SUS1; IQ O I starts SUS2; and acknowledges each CCE selection.

The terminal device: - transmits the selected CCH for the downlink; Un 20 IQ Un 506 641 63 - waits for an acknowledgement; - terminates the CCH message.

Once these steps have been taken, the modem has reached idle mode, transmitting SUS2. Using the CCH, the bit loading factors can now be changed according to channel characteristics and DAS transmission can begin.

The VDSL modem may interface with different network elements, depending on the physical location of the modem, i.e. in access node space or on customer premises. At customer premises, the VDSL modem may interface with an active network termination device. At the access node, the VDSL modem will interface with an access-specific interface, see Figure 32, which shows a logical view of the network elements that interface with the VDSL modem.

The VDSL modem can be physically integrated with and the VDSL modem at the access node can be physically located in the cabinet in which the night termination equipment, the access node, is located.

The NT (interface A1) and the access node (interface A2) require a layer 1 frame format from the VDSL modem. Integrated into the layer 1 frame are, apart from the frame header and the payload, a number of information fields for management and control information. These management and control fields include e.g. AIS- only if SDH is taken all the way to the customer premises) measurements various alarm indicators, such as SDH alarms, e.g. (valid of bit error rate for performance monitoring, indications of whether synchronization is bad, or lost, equipment management alarms for loss of power supply and too high temperature etc. The management fields also include activation of various loop tests on the modem, for operation and maintenance purposes. 506 641 64 TABLE 1 System parameters of the overall system Orthogonality between modems No Duplex method Separate bands Frequency spacing between up- Depending on duplex filter/down-data flow characteristic Net bit rate, - upstream 2 Mbit/s - downstream 13 or 26 Mbit/s Gross bit rate, - upstream Coding dependent - downstream Coding dependent Cable length < 1300 meters Cable bandwidth 10 MHz Modulation, single carrier - upstream O-4096 QAM - downstream O-4096 QAM Number of carriers, total 1024 Bandwidth for each carrier 9.77 kHz Cyclic prefix 128 samples (carrier) Modulation DMT Access technology VDSL Signal power -60 dBm/Hz U1 CD 0\ Ö\ ß- "A 65 Bit error rate 104 Interleaving delay 0.5 ms (Interleaving delay) System margin 6 dB CCH - bandwidth 1 carrier, minimum 16 kbi:/s - protocol HDLC Sample clk 20 MHz i10ppm Frame clk 20 MHZ/(2048+ll2) = 9.19 kHz 506 641 66 TABLE 2 System parameters for the Transmitter Interleaving - depth 2 x frames - delay 0.5 ms DAC resolution 84 dB Clipping algorithm No (Clipping algorithm) IFFT - type Real - points 2048 - resolution 16 bit LP filter LP lO MHz Bit charge Yes, O, 2, 4, 6, 8, lO, 12 bit Energy charge Yes, 4 bit BSI interval 1 s TABLE 3 506 641. 67 System parameters for the Receiver ADC resolution 66 dB FFT - type Real - points 2048 - resolution 16 bit LP filter LP 10 MHZ Synchronization - jitter < 0.5 ns VCXO i25 ppm, lOppm/V sensitivity - DAC 18 bit, Range O-5 V - resolution l/100 of a sample 506 641 6 8 TABLE 4 Carrier modes Mode Transmit Bit charge Equalize Scaling CMl Data 2 - 12 Yes Yes cM2 No o No o CM3 Sync info O Yes, sync Yes, low

Claims (28)

UI IJ Un ga V; 506 641 69 PATENT CLAIMS A multi-carrier transmission system in which channel information is transmitted between two transceivers using a plurality of carrier paths, characterized in that each subcarrier, or symbol, has a parameter associated therewith, and in that said transceivers are adapted to transmit said channel information as a sequence of a number of groups, in which each of said groups contains information regarding the number of adjacent subcarriers having the same value as said parameter, together with the current value of the parameter. A multi-carrier transmission system according to claim 1, characterized in that said parameter has a plurality of discrete values. A mule: carrier transmission system according to claim 1 or 2, characterized in that said parameter is a bit charge value. A multi-carrier transmission system according to claim 1 or 2, characterized in that said parameter is a QAM constellation identifier. A mulch transmission system according to any one of the preceding claims, characterized in that the number of bits of information that need to be transmitted is significantly reduced compared to known systems, thereby effecting a saving in transmission capacity. A carrier transmission system according to claim 5, characterized in that said parameter has a plurality of discrete values, in that the number of transmitted bits of information will be reduced if: 506 641 Un W fi 30 70 P (m + n) <N xn where P is the number of groups, the number of discrete values of 2n ~ 1 mentioned parameter is> 2 ", but 5, and the number of subcarriers N is> 2", but S Zm fl. A multi-carrier transmission system according to claim 6, characterized in that N is equal to 1024, n is equal to 4, and m is equal to 10. A multicarrier transmission system according to claim 7, characterized in that P is equal to 50 groups and in that the number of bits to be transmitted is reduced by 83%. A multi-carrier transmission system according to claim 7, characterized in that P is less than 200 groups, by at least 32%. and that the number of bits to be transmitted is reduced A multi-carrier transmission system according to claim 7, characterized in that P is less than 100 groups, is reduced by at least 66%. and by the number of bits to be transmitted 11. ll. A transmitter for a multi-carrier transmission system in which channel information is transmitted between two transceivers using a plurality of subcarriers, characterized in that each subcarrier, or symbol, said transmitter is adapted to transmit said having a parameter associated therewith, and that channel information as a sequence of n groups, each of said n groups containing information regarding the number of adjacent subcarriers having the same value of said parameter, together with the current value of the parameter. (J: 10 b: (Ju _ 506 641 71 A transmitter according to claim 11, characterized in that said parameter has a plurality of discrete values. A transmitter according to claim 11 or claim 12, characterized in that said parameter is a bit charge value. A transmitter according to claim 11 or claim 13, characterized in that said parameter is a QAM constellation identifier. A transceiver for a multicarrier transmission system, characterized in that said transceiver includes a receiver and a transmitter according to any one of claims 11 to 14. A multicarrier transmission system that includes two transceivers according to claim 15. In a multi-carrier transmission system, in which channel information is transmitted between two transceivers using a plurality of subcarriers, a method of transmitting channel information, characterized in that each subcarrier, or symbol, has a parameter associated therewith, said method being characterized by the step transmitting said channel information as a sequence of n groups, each of said n groups containing information regarding the number of adjacent subcarriers having the same value on said parameter, together with the current value of the parameter. A method according to claim 17, characterized in that said parameter has a plurality of discrete values. 506 641 IQ Un 30 bl L / l 72 A method according to claim 17 or claim 18, characterized in that said parameter is a bit charge value. A method according to claim 17 or claim 18, characterized in that said parameter is a QAM constellation identifier. A method according to any one of claims 17 to 19, characterized in that the number of pieces of information that need to be transmitted is significantly reduced compared to known systems, whereby a saving in transmission capacity is achieved. A method according to claim 21, characterized in that: said parameter has a plurality of discrete values, in that the number of information bits transmitted will be reduced by: P (m + n) <N xn where P is the number of groups, the number discrete values for said parameter are> 2 “, but S Zml, and the number of subcarriers N is> 2m, but S 2m4. A method according to claim 22, characterized in that N is equal to 1024, n is equal to 4, and m is equal to 10. A method according to claim 23, characterized in that P is equal to 50 groups and in that the number of bits to be transmitted is reduced by 83%. A method according to claim 23, characterized in that P is less than 200 groups and in that the number of bits to be transmitted is reduced by at least 32%. A method according to claim 23, characterized in that P is less than 100 groups and in that the number of bits to be transmitted is reduced by at least 66%. A multicarrier transmission system, a transmitter, a transceiver, or a method according to any one of the preceding claims, characterized in that said system is a DMT system. A multi-carrier system, a transmitter, a transceiver, or a method according to any one of the preceding claims, characterized in that said system is a DMT-based VDSL system.