SE506510C2 - Semiconductors including inclined base emitter and collector base transitions and method for producing such - Google Patents

Semiconductors including inclined base emitter and collector base transitions and method for producing such

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Publication number
SE506510C2
SE506510C2 SE9600898A SE9600898A SE506510C2 SE 506510 C2 SE506510 C2 SE 506510C2 SE 9600898 A SE9600898 A SE 9600898A SE 9600898 A SE9600898 A SE 9600898A SE 506510 C2 SE506510 C2 SE 506510C2
Authority
SE
Sweden
Prior art keywords
base
insulator
emitter
collector
region
Prior art date
Application number
SE9600898A
Other languages
Swedish (sv)
Other versions
SE9600898L (en
SE9600898D0 (en
Inventor
Andrej Litwin
Torkel Arnborg
Original Assignee
Ericsson Telefon Ab L M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Telefon Ab L M filed Critical Ericsson Telefon Ab L M
Priority to SE9600898A priority Critical patent/SE506510C2/en
Publication of SE9600898D0 publication Critical patent/SE9600898D0/en
Priority to AU20493/97A priority patent/AU2049397A/en
Priority to PCT/SE1997/000377 priority patent/WO1997033319A1/en
Priority to CN97192844A priority patent/CN1212787A/en
Priority to EP97908624A priority patent/EP0963610A1/en
Priority to JP9531710A priority patent/JP2000506311A/en
Priority to CA002243998A priority patent/CA2243998A1/en
Priority to KR1019980706992A priority patent/KR19990087554A/en
Publication of SE9600898L publication Critical patent/SE9600898L/en
Publication of SE506510C2 publication Critical patent/SE506510C2/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66265—Thin film bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/7317—Bipolar thin film transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Transistors (AREA)

Abstract

In a bipolar semiconductor-on-insulator transistor device (1) comprising an emitter region (4), a base region (5), a collector region (2) and a collector contacting region (6) in a semiconductor wafer, e.g. a monocrystalline silicon wafer (2), on top of an insulator (3), the base-emitter and collector-base junctions are tilted relative to the interface between the semiconductor wafer (2) and the insulator (3). The device can be made by anisotropic etching in order to produce a tilted surface (7) at an edge of the device or equivalently a V-groove having tilted sidewalls. The base and emitter regions (5, 4) are then produced by diffusing suitable donor and acceptor atoms into the material inside the tilted surface. Such a bipolar semiconductor-on-insulator transistor combines the high speed features of a lateral semiconductor device and the high voltage features of a vertical semiconductor device.

Description

sne 510 2 Collector" som presenteras i 1994 IEDM Conference Digest.) KORTFATTAD BESKRIVNING AV UPPFINNINGEN Syftet med uppfinningen är att åstadkomma en bipolär halvledar- på-isolator-anordning som kombinerar höghastighetsegenskaperna hos en lateral halvledaranordning och högspänningsegenskaperna hos en vertikal halvledaranordning. BRIEF DESCRIPTION OF THE INVENTION The object of the invention is to provide a bipolar semiconductor-on-insulator device which combines the high speed properties of a lateral semiconductor device and the high voltage semiconductor properties of a semiconductor device.

Detta uppnås genom den bipolära halvledar-på-isolator anordningen enligt uppfinningen genom att bas-emitter- och kollektor-bas-övergångarna är lutade.This is achieved by the bipolar semiconductor-on-insulator device according to the invention in that the base-emitter and collector-base junctions are inclined.

Detta syfte uppnås också genom förfarandet enligt uppfinningen att framställa en bipolär halvledar-på-isolator anordning genom att göra basområdet och emitterområdet lutade.This object is also achieved by the method according to the invention to produce a bipolar semiconductor-on-insulator device by tilting the base region and the emitter region.

KORTFATTAD BESKRIVNING AV RITNINGEN Uppfinningen kommer att beskrivas mer i detalj nedan med hänvisning till den bilagda ritningen i vilken den enda figuren är en schematisk genomskärningsvy av en utföringsform av en bipolär halvledar-på-isolator-anordning enligt uppfinningen.BRIEF DESCRIPTION OF THE DRAWING The invention will be described in more detail below with reference to the accompanying drawing in which the single figure is a schematic sectional view of an embodiment of a bipolar semiconductor-on-insulator device according to the invention.

BESKRIVNING AV FÖREDRAGNA UTFÖRINGSFORMER På ritningen visar den enda figuren schematisk en utföringsform av en bipolär halvledar-på-isolator-anordning 1 enligt uppfinningen.DESCRIPTION OF PREFERRED EMBODIMENTS In the drawing, the single figure schematically shows an embodiment of a bipolar semiconductor-on-insulator device 1 according to the invention.

I den visade utföringsformen av halvledar-på-isolator- anordningen 1 är halvledaren en kiselskiva. Den visade anordningen 1 är således en kisel-på-isolator-(SOI) halvledaranordning. Kiselskivan betecknas 2 medan isolatorn, t ex ett kiseloxidlager, betecknas 3.In the illustrated embodiment of the semiconductor-on-insulator device 1, the semiconductor is a silicon wafer. The device 1 shown is thus a silicon-on-insulator (SOI) semiconductor device. The silicon wafer is designated 2 while the insulator, for example a silicon oxide layer, is designated 3.

Kiselskivan 2 innefattar ett emitterområde 4, ett basområde 5 och ett kollektorområde 6.The silicon wafer 2 comprises an emitter area 4, a base area 5 and a collector area 6.

I enlighet med uppfinningen är bas-emitterövergången och kollektor-basövergången i kiselskivan 2 parallella och lutade relativt gränsytan mellan kiselskivan 2 och isolatorn 3. 596 510 3 Detta åstadkoms genom att emitterområdet 4 och basområdet 5 är lutade relativt nämnda gränsyta mellan kiselskivan 2 och isolatorn 3.According to the invention, the base-emitter junction and the collector-base junction in the silicon wafer 2 are parallel and inclined relative to the interface between the silicon wafer 2 and the insulator 3. This is achieved by the emitter region 4 and the base region 5 being inclined relative to said interface between the silicon wafer 2 and the insulator 3 .

Lutningsvinkeln för bas-emitter- och kollektor-basövergångarna relativt gränsytan mellan kiselskivan 2 och isolatorn 3 är typiskt 4s° i 2o°.The angle of inclination of the base-emitter and collector-base transitions relative to the interface between the silicon wafer 2 and the insulator 3 is typically 4 ° to 20 °.

Ett föredraget förfarande för att framställa den visade halvledaranordningen 1 är genom anisotrop ets av en SOI-film med (100) kiselkristallriktning, med KOH för att exponera kiselskivans (111) kristallyta vid en av dess laterala kanter, varvid ett basområde och ett emitterområde dopas parallellt för att bli exponerad (111) kristallyta i kiselskivan, vilken normalt redan innefattar ett kollektorområde.A preferred method of manufacturing the semiconductor device 1 shown is by anisotropically etching an SOI film having (100) silicon crystal direction, with KOH to expose the crystal surface of the silicon wafer (111) at one of its lateral edges, a base region and an emitter region being doped to be exposed (111) to a crystal surface in the silicon wafer, which normally already includes a collector area.

I detta fall kommer lutningsvinkeln för de parallella bas- emitter- och kollektor-basövergångarna att motsvara lutningsvinkeln hos (111) kristallytan i kiselskivan.In this case, the angle of inclination of the parallel base-emitter and collector-base transitions will correspond to the angle of inclination of the (111) crystal surface in the silicon wafer.

Det torde emellertid inses att andra förfaranden än etsning kan användas för att framställa lutade parallella bas-emitter- och kollektor-basövergångar. Vidare kan andra kristallytor än kiselskivans (111) kristallyta exponeras för att dopa ett basområde och ett emitterområde parallellt för att bli exponerad kristallyta.It will be appreciated, however, that methods other than etching can be used to produce inclined parallel base-emitter and collector-base transitions. Furthermore, crystal surfaces other than the crystal surface of the silicon wafer (111) can be exposed to dope a base region and an emitter region in parallel to be exposed crystal surface.

SOI-filmens dimensioner väljs på ett sådant sätt att det elektriska fältet vinkelrätt mot emitter-basövergången minskas.The dimensions of the SOI film are selected in such a way that the electric field perpendicular to the emitter-base junction is reduced.

Detta kommer att öka halvledaranordningens genombrottsspänning.This will increase the breakdown voltage of the semiconductor device.

Tack vare sin geometri emitteras laddningen in i kollektorområdesladdningsområdet i det elektriska fältets riktning. Eftersom ingen potentiallåsning finns och det laterala fältet således aldrig är noll kommer transporten att ske genom drift och inte genom diffusion som i fallet med en halvledaranordning med helt utarmad kollektor. Denna egenskap kommer att göra halvledaranordningen enligt uppfinningen snabbare och med prestanda jämförbar med en lateral halvledaranordning. 506 510 4 Dessutom torde det inses att uppfinningen inte är begränsad till användning av kisel som halvledare i halvledar-på-isolator- anordningen enligt uppfinningen. I stället för kisel kan GaAS eller SiC lika väl användas.Due to its geometry, the charge is emitted into the collector area charge area in the direction of the electric field. Since there is no potential locking and the lateral field is thus never zero, the transport will take place by operation and not by diffusion as in the case of a semiconductor device with a completely depleted collector. This feature will make the semiconductor device according to the invention faster and with performance comparable to a lateral semiconductor device. In addition, it should be understood that the invention is not limited to the use of silicon as a semiconductor in the semiconductor-on-insulator device according to the invention. Instead of silicon, GaAS or SiC can just as well be used.

Claims (5)

506 510 PATENTKRAV506 510 PATENT CLAIMS 1. Bipolär halvledar-på-isolator-anordning (1) innefattande ett emitterområde (4), ett basomrâde (5) och ett kollektorområde (6) i en halvledarskiva (2) på en isolator (3), kännetecknad av att bas-emitter- och kollektor-basövergångarna är lutade relativt gränsytan mellan halvledarskivan (2) och isolatorn (3).Bipolar semiconductor-on-insulator device (1) comprising an emitter region (4), a base region (5) and a collector region (6) in a semiconductor wafer (2) on an insulator (3), characterized in that the base emitter and the collector-base junctions are inclined relative to the interface between the semiconductor wafer (2) and the insulator (3). 2. Anordning enligt krav 1, kännatecknad av att lutningsvinkeln för bas-emitter- och kollektor-basövergângarna är 45° i 20°.Device according to claim 1, characterized in that the inclination angle of the base-emitter and collector-base transitions is 45 ° in 20 °. 3. Anordning enligt krav 1 eller 2, kännetecknad av att lutningsvinkeln för bas-emitter- och kollektor-basövergångarna motsvarar (111) kristallytan på halvledarskivan (2).Device according to Claim 1 or 2, characterized in that the angle of inclination of the base-emitter and collector-base junctions corresponds to (111) the crystal surface of the semiconductor wafer (2). 4. Förfarande för att framställa en bipolär halvledar-på- isolator-anordning från en halvledarskiva (2) på en isolator (3), kännetecknad av att ett basomrâde (5) dopas och ett emitterområde (4) lutat relativt gränsytan mellan halvledarskivan (2) och isolatorn (3).Method for manufacturing a bipolar semiconductor-on-insulator device from a semiconductor wafer (2) on an insulator (3), characterized in that a base region (5) is doped and an emitter region (4) inclined relative to the interface between the semiconductor wafer (2) ) and the insulator (3). 5. Förfarande enligt krav 4, kännetecknat av att halvledarskivan (2) etsas anisotropt för att exponera dess (111) kristallyta vid en av dess laterala kanter innan basområdet (5) och emitterområdet (4) parallella med den exponerade (111) kristallytan hos halvledarskivan (2) dopas.Method according to claim 4, characterized in that the semiconductor wafer (2) is etched anisotropically to expose its (111) crystal surface at one of its lateral edges before the base region (5) and the emitter region (4) parallel to the exposed (111) crystal surface of the semiconductor wafer. (2) dopas.
SE9600898A 1996-03-07 1996-03-07 Semiconductors including inclined base emitter and collector base transitions and method for producing such SE506510C2 (en)

Priority Applications (8)

Application Number Priority Date Filing Date Title
SE9600898A SE506510C2 (en) 1996-03-07 1996-03-07 Semiconductors including inclined base emitter and collector base transitions and method for producing such
AU20493/97A AU2049397A (en) 1996-03-07 1997-03-05 Bipolar soi device having a tilted pn-junction, and a method for producing such a device
PCT/SE1997/000377 WO1997033319A1 (en) 1996-03-07 1997-03-05 Bipolar soi device having a tilted pn-junction, and a method for producing such a device
CN97192844A CN1212787A (en) 1996-03-07 1997-03-05 Bipolar SOI device having tilted PN-junction, and method for producing such device
EP97908624A EP0963610A1 (en) 1996-03-07 1997-03-05 Bipolar soi device having a tilted pn-junction, and a method for producing such a device
JP9531710A JP2000506311A (en) 1996-03-07 1997-03-05 Bipolar SOI device with graded PN junction and method of manufacturing such device
CA002243998A CA2243998A1 (en) 1996-03-07 1997-03-05 Bipolar soi device having a tilted pn-junction, and a method for producing such a device
KR1019980706992A KR19990087554A (en) 1996-03-07 1997-03-05 Bipolar Silicon-on-Insulator Devices and Manufacturing Method Thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE9600898A SE506510C2 (en) 1996-03-07 1996-03-07 Semiconductors including inclined base emitter and collector base transitions and method for producing such

Publications (3)

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SE9600898D0 SE9600898D0 (en) 1996-03-07
SE9600898L SE9600898L (en) 1997-09-08
SE506510C2 true SE506510C2 (en) 1997-12-22

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SE9600898A SE506510C2 (en) 1996-03-07 1996-03-07 Semiconductors including inclined base emitter and collector base transitions and method for producing such

Country Status (8)

Country Link
EP (1) EP0963610A1 (en)
JP (1) JP2000506311A (en)
KR (1) KR19990087554A (en)
CN (1) CN1212787A (en)
AU (1) AU2049397A (en)
CA (1) CA2243998A1 (en)
SE (1) SE506510C2 (en)
WO (1) WO1997033319A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100197001B1 (en) * 1996-05-02 1999-07-01 구본준 Bipolar device and manufacturing method thereof

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1589453A1 (en) * 1966-06-28 1970-04-02 Asea Ab Semiconductor device
US5040034A (en) * 1989-01-18 1991-08-13 Nissan Motor Co., Ltd. Semiconductor device

Also Published As

Publication number Publication date
CA2243998A1 (en) 1997-09-12
SE9600898L (en) 1997-09-08
JP2000506311A (en) 2000-05-23
CN1212787A (en) 1999-03-31
WO1997033319A1 (en) 1997-09-12
AU2049397A (en) 1997-09-22
SE9600898D0 (en) 1996-03-07
KR19990087554A (en) 1999-12-27
EP0963610A1 (en) 1999-12-15

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