JP2933050B2 - Semiconductor substrate and method of manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for smoothing a surface of a semiconductor substrate, and a method for manufacturing a wafer-like semiconductor substrate having a high impurity concentration region and a low impurity concentration region, and a semiconductor device.

[0002]

2. Description of the Related Art A semiconductor wafer having a high impurity concentration region and a low impurity concentration region (a thin semiconductor substrate or substrate)
First, a first semiconductor wafer 1a having a relatively low impurity concentration (first impurity concentration) of, for example, N type as shown in FIG. 1A is cut out from the ingot.

Next, an N-type impurity is introduced by thermal diffusion from both main surfaces of the first semiconductor wafer 1a, and the first impurity concentration is located at the center in the thickness direction of the semiconductor wafer as shown in FIG. Region 2 and N ⁺ -type first and second diffusion regions 3a and 3b having a second impurity concentration higher than the first impurity concentration are formed on both sides of the second semiconductor wafer 1b. Get.

Next, a second semiconductor wafer 1 shown in FIG.
b so that the thickness of the second semiconductor wafer 1b becomes approximately 1/2.
Is ground from one main surface side to remove all of the first diffusion region 3a and a part of the region 2 with the first impurity concentration, and the second diffusion region 3a having the second impurity concentration shown in FIG. A third semiconductor wafer 1c comprising two diffusion regions 3b and a first impurity concentration region 2a is obtained. Since the grinding for obtaining the third semiconductor wafer 1c shown in FIG. 1C is performed by a well-known surface grinding machine (plane grinding machine), the grinding of the surface of the semiconductor wafer is simultaneously achieved, and the semiconductor wafer is cut out from the ingot. A surface having better smoothness than the surface of the first semiconductor wafer 1a is obtained. Therefore, the step of grinding the second semiconductor wafer 1b in FIG. 1B into the third semiconductor wafer 1c in FIG. 1C can be referred to as a first polishing step. However, it does not have sufficient smoothness while being ground by a surface grinder. Therefore, the upper surface of the third semiconductor wafer 1c in FIG. 1C is secondly polished with a cloth or the like impregnated with a sharpening material and mirror-polished (mirror polished). As a result, the semiconductor wafer 1c that could not be removed by the first polishing
To remove irregularities and damage on the main surface.

In manufacturing a semiconductor device, FIG.
For example, a P-type base region and an N-type emitter region are formed in the first impurity concentration region 2a to obtain a bipolar transistor, or a P-type channel region, an N-type source region, a gate insulating film, etc. Is obtained.

[0006]

In the second polishing (mirror polishing step), it is necessary to use a fine polishing material to prevent damage to the surface of the semiconductor wafer and perform polishing. Not only for a long time,
It took time and increased production costs. Therefore, if the second polishing can be omitted, the production process of the semiconductor wafer and the production process of the semiconductor device can be simplified, and the productivity can be improved. However, since the surface of the wafer subjected to only the first polishing has relatively large irregularities, a semiconductor wafer subjected to only the first polishing is used, for example, an oxide film is formed on the surface of the wafer, and the oxide film is formed by known photolithography. When patterning is performed in the (light etching) step, unevenness may be disturbed, and the relative alignment between the photomask and the wafer may not be properly performed. That is, such a relative alignment between the photomask and the wafer is generally performed using a well-known mask alignment apparatus. At this time, a part of the oxide film formed on the upper surface of the wafer may be removed into a predetermined shape to form a concave portion, and this may be used as a mark for relative alignment of the wafer with respect to the photomask. The position of the marker is detected by a method of scanning the marker and an oxide film around the marker with a laser beam, and identifying the marker based on a difference in the angle of reflection of the laser beam from the wafer. That is, the portion where the sign is formed is recessed at a predetermined inclination from the surface of the oxide film where the sign is not formed. Therefore, if a laser beam is projected from the direction substantially perpendicular to the surface of the oxide film and optical scanning is performed, the laser beam is reflected from the surface of the oxide film in a direction substantially perpendicular to the portion where no mark is formed. Since the oxide film is inclined in the peripheral portion, the laser beam hitting this portion is reflected at a predetermined angle with respect to the oxide film surface. Therefore, the position of the marker can be detected by measuring the amount of reflected laser light reflected at the predetermined angle. However, if the surface of the wafer is not sufficiently smooth, the surface of the oxide film formed on the surface of the wafer also has irregularities, and when scanning with a laser beam, the surface of the oxide film other than the peripheral portion of the sign is exposed. The irregular reflection of the laser beam makes accurate detection of the sign impossible. In addition, since a damaged layer having microcracks is formed on the surface of the wafer subjected to only the first polishing, when a semiconductor element is formed on this layer, good electrical characteristics of the element cannot be obtained. Therefore,
It was impossible to omit the second polishing.

It is an object of the present invention to provide a method for smoothing a semiconductor substrate without including a mechanical mirror finishing step, and a method for manufacturing a semiconductor substrate and a semiconductor device.

[0008]

In order to achieve the above object, the present invention has a first impurity concentration with a smooth surface.
A first semiconductor region to be formed and a first impurity concentration higher than the first impurity concentration.
A second semiconductor region having a second impurity concentration.
A method of manufacturing a wafer-shaped semiconductor substrate, comprising:
From the semiconductor region where the region has the first impurity concentration
Providing a first semiconductor wafer comprising:
The first semiconductor from one and the other main surface of the semiconductor wafer;
Impurities to obtain the same conductivity type as the body wafer
Both sides of the region having the first impurity concentration by thermal diffusion
First and second impurities having the second impurity concentration
Obtaining a second semiconductor wafer having a configuration in which diffusion regions are arranged
And the first semiconductor wafer in the second semiconductor wafer.
A pure diffusion region and a region having the first impurity concentration
Grind a part, and at the same time as this grinding or in another process,
Fine irregularities remain on the surface of the region having the impurity concentration of
Polishing to obtain a third semiconductor wafer,
The polished surface of the third semiconductor wafer is thermally oxidized.
Forming a semiconductor oxide film by etching, and etching the oxide film.
The first surface, the surface of which is smoothed by removing
And a step of obtaining a semiconductor region . Further, as described in claims 2 and 3 , the technology of claim 1 can be applied to the manufacture of a semiconductor device.

[0009]

According to the present invention, fine irregularities on the surface of a semiconductor substrate or a semiconductor wafer can be removed and smoothed without a polishing step by polishing. Is improved. Further, according to the first aspect of the present invention, the first and second impurity concentration regions are provided.
It is possible to easily obtain a semiconductor substrate (semiconductor wafer) in which the surface of the region having the impurity concentration is smoothed. Claims
According to the inventions of 2 and 3 , a semiconductor device having regions of the first and second impurity concentrations can be easily obtained.

[0010]

Next, a method of manufacturing a semiconductor wafer and a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. First, as shown in FIG. 2A, a first semiconductor wafer 11 cut into a flat plate shape from a silicon ingot (a mass of single crystal silicon grown from a silicon melt).
Prepare a. Cutting (slicing) of the wafer 11 from the ingot is performed using a known slicing machine. The wafer 11a in FIG. 2A is a non-mirror wafer having a relatively large uneven surface (rough surface) generated by slicing on the surface, and has a thickness of about 500 μm. Note that the wafer 11a of this embodiment has an N-type impurity (for example, phosphorus) having a first impurity concentration (for example, 4 × 10 ^13).
cm ⁻³ ). The depth of the concave portion on the surface of the wafer 11a, that is, the height of the convex portion is about 900.
0 Å (0.9 μm).

Next, for example, phosphorus is introduced as an N-type impurity into both main surfaces of the wafer 11a in FIG. 2A by a well-known thermal diffusion method, and as shown in FIG. The first and second impurity diffusion regions having a second impurity concentration (for example, 3 × 10 ²⁰ cm ⁻³ ) higher than the first impurity concentration on both sides of the N-type semiconductor region 12 having an impurity concentration of 1 are left. A second semiconductor wafer 11b on which N ⁺ type semiconductor regions 13a and 13b are formed. The thickness of the N-type semiconductor region 12 is about 180 μm, and the first and second N
The thickness of each of the ⁺ type semiconductor regions 13a and 13b is about 16
0 μm.

Next, polishing is started from one main surface of the second semiconductor wafer 11b where the first N ⁺ type semiconductor region 13a is formed, and the entire first N ⁺ type semiconductor region 13a is removed. About half of the N-type semiconductor region 12 is removed to obtain a third semiconductor wafer 11c shown in FIG. The third semiconductor wafer 11c shown in FIG. 2C has an N-type semiconductor region 12a having a first impurity concentration and a remaining portion of the N-type semiconductor region 12.
And an N ⁺ type semiconductor region 13b having a second impurity concentration. The thickness of the N-type semiconductor region 12a is about 90 μm,
Since the thickness of the N ⁺ type semiconductor region 13b is about 160 μm, the thickness of the entire third semiconductor wafer 11c is about 250 μm.
m. Polishing for obtaining the third semiconductor wafer 11c is performed by a known surface grinder (a device for rotating a grinding tool to grind the surface of a workpiece). Therefore, the polished N
Although the exposed surface of the mold semiconductor region 12a is a surface having less irregularities than the surfaces of the semiconductor wafers 11a and 11b in FIGS. 2A and 2B, the exposed surface is not a mirror surface or a smooth surface, but a very small surface. It is a rough surface on which irregularities and microcracks remain. The depth of the concave portion, that is, the height of the convex portion on the surface of the wafer 11c after grinding is approximately 1600 angstroms (0.16 μm).

Next, a silicon oxide 14 is formed on the entire upper surface of the N-type semiconductor region 12a of the third semiconductor wafer 11c by a well-known thermal oxidation method as shown in FIG. 2D.
In the thermal oxidation step, silicon on the surface of the semiconductor wafer 11c reacts with oxygen in the air to form a silicon oxide film 14, so that the N-type semiconductor region 12 of the semiconductor wafer 11c is formed.
A part of the surface side of “a” is transformed into the silicon oxide film 14. N-type semiconductor region 12a denatured on silicon oxide film 14
Has a thickness of about 0.35 μm to 0.5 μm, and includes substantially all of the surface side region where the above-mentioned irregularities and microcracks exist. In other words, substantially the entire surface region of the semiconductor wafer 11c where the irregularities and microcracks have occurred is transformed into the silicon oxide film 14. Note that the silicon oxide film 14 is also formed on a portion corresponding to the upper part of the surface of the N-type semiconductor region 12a in FIG. 2C, and thus has a thickness of about 0.7 μm to 1.0 μm.

Next, the silicon oxide film 14 is removed by etching with an etching solution comprising, for example, hydrofluoric acid and water, and an N-type semiconductor region 12a is formed on the main surface of the semiconductor wafer 11c.
Is exposed as shown in FIG. Strictly, the thickness of the N-type semiconductor region 12a is slightly smaller than that in the stage of FIG. On the surface of the N-type semiconductor region 12a exposed on the wafer surface, the above-mentioned uneven surface is removed, and there is substantially no micro-crack or the like (there is no micro-crack that causes a problem in characteristics). It is a surface that can be called a smooth surface. The reason why the surface of the N-type semiconductor region 12a is mirrored and smoothed as described above is considered as follows.

In the thermal oxidation step, as described above, silicon in the silicon semiconductor wafer, that is, in the N-type semiconductor region 12a reacts with oxygen in the air, and this silicon and oxygen combine to form the silicon oxide film 14. . Here, the reaction speed between silicon and oxygen is considered to be fast enough not to be affected by the uneven surface on the upper surface of the N-type semiconductor region 12a.
That is, oxidation of silicon proceeds not only in the vertical direction but also in the horizontal direction with respect to the main surface of the semiconductor wafer 11c. For this reason, the oxidation of the projection on the surface of the N-type semiconductor region 12a proceeds not only in the vertical direction but also in the horizontal direction, and the entire projection is oxidized within a short time. Therefore, the interface between the silicon oxide film 14 formed by thermal oxidation and the silicon semiconductor substrate therebelow, that is, the N-type semiconductor region 12a, is a smooth surface without being affected by the irregularities on the surface side of the semiconductor wafer 11c. . Therefore, when the silicon oxide film 14 is removed, a smoothed surface of the N-type semiconductor region 12a is obtained. FIGS. 3 and 4 schematically show the principle of smoothing, and correspond to enlarged portions of FIGS. 2C and 2D. The uneven surface 15 generated in FIG.
Is in a state as absorbed by the silicon oxide film 14 as shown in FIG.

The semiconductor wafer 11c shown in FIG.
It is used, for example, in the manufacture of field effect transistors (FETs), as schematically shown in FIG. In this case, a P-type impurity is selectively diffused into the N-type semiconductor region 12a to form a P-type channel region 16, and an N-type impurity is further diffused to form an N ⁺ -type source region 17. When the source region 17 is formed, the oxide film 1 is formed on the channel formation region 16.
It is required that the position of the opening 19 of the 8 be determined accurately. For this reason, the position of the photomask is adjusted by the well-known photolithography (light etching) technique as already described in the description of the related art. An optically identifiable marker is used when aligning the photomask. However, in this embodiment, the surface of the selective diffusion oxide film 18 is smooth because the surface of the semiconductor wafer 11c is smooth, and the marker can be accurately identified. And it becomes possible to detect it quickly. In addition, a large number of semiconductor elements are simultaneously formed on the semiconductor wafer 11c,
As shown by broken lines in FIG. 5, the semiconductor wafer 11c is cut to obtain independent semiconductor elements.

[0017]

[Modifications] The present invention is not limited to the above-described embodiment, and for example, the following modifications are possible. (1) As shown in FIG. 6, a P-type semiconductor region 20 is formed on the smoothed N-type semiconductor region 12a of the third semiconductor wafer 11c by an epitaxial growth method, and N ⁺ is formed therein.
The type semiconductor region 21 can also be formed. in this case,
Since the surface of the N-type semiconductor region 12a is smoothed, the surface of the P-type semiconductor region 20 and the surface of the oxide film as a mask formed thereon are also smoothed. In FIG. 6, for example, the N ⁺ type semiconductor region 13b is a collector, the P type semiconductor region 20 is a base, and the N ⁺ type semiconductor region 21 is an emitter. (2) The present invention is applicable not only to FETs and bipolar transistors but also to the manufacture of integrated circuits, diodes, thyristors, and the like. (3) The technique of the present invention is particularly effective in obtaining a semiconductor wafer composed of, for example, an N-type semiconductor region 12a having a low impurity concentration and an N ⁺ -type semiconductor region 13b having a high impurity concentration. As shown, it is also effective for smoothing the surface of the semiconductor wafer 11a cut out from the ingot. In this case, the surface of the semiconductor wafer 11a is polished by a surface grinder, then a silicon oxide film is formed by thermal oxidation, and then removed by etching.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a conventional semiconductor wafer in a manufacturing process order.

FIG. 2 is a cross-sectional view showing a semiconductor wafer according to an embodiment of the present invention in the order of manufacturing steps.

FIG. 3 is a partially enlarged sectional view of FIG. 2 (C).

FIG. 4 is a partially enlarged sectional view of FIG. 2 (D).

FIG. 5 is an enlarged cross-sectional view showing a semiconductor device formed on the semiconductor wafer of FIG. 2 (E).

FIG. 6 is an enlarged cross-sectional view showing a case where semiconductor elements are formed on the semiconductor wafer of FIG. 2E by another method.

[Explanation of symbols]

11c Semiconductor wafer 12a N type semiconductor region 13b N ⁺ type semiconductor region 14 silicon oxide film

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int.Cl. ⁶ , DB name) H01L 21/02 H01L 21/304 321 H01L 21/306

Claims (3)

(57) [Claims] A first impurity concentration having a smooth surface;
The first semiconductor region and the first impurity concentration
A second semiconductor region having a high second impurity concentration;
A method of manufacturing a wafer-like semiconductor substrate , comprising: a semiconductor region having an entire region having the first impurity concentration.
Preparing a first semiconductor wafer made of, from the one and the other main surface of said first semiconductor wafer
To obtain the same conductivity type as that of the first semiconductor wafer
Having the first impurity concentration by thermally diffusing impurities of
First and second regions having the second impurity concentration on both sides of the region.
Second semiconductor wafer having a structure in which two impurity diffusion regions are arranged.
A step of obtaining an electron beam and the first impurity diffusion in the second semiconductor wafer
Polishing the region and a part of the region having the first impurity concentration.
Grinding, and simultaneously with or separately from this grinding, the first impurity
The surface of the region with the concentration is made so that fine irregularities remain.
Polishing to obtain a third semiconductor wafer; and thermally oxidizing the polished surface of the third semiconductor wafer.
Forming an oxide film of the semiconductor by etching, and removing the oxide film by etching to smooth the surface.
Obtaining the formed first semiconductor region.
A method for manufacturing a semiconductor substrate, comprising: 2. The entire region has a first impurity concentration.
Step of preparing a first semiconductor wafer comprising a semiconductor region
And from one and the other main surface of the first semiconductor wafer,
To obtain the same conductivity type as that of the first semiconductor wafer
Having the first impurity concentration by thermally diffusing impurities of
A second impurity higher than the first impurity concentration is provided on both sides of the region.
First and second impurity diffusion regions having a pure concentration are arranged.
Obtaining a second semiconductor wafer having the above-described configuration, and diffusing the first impurity in the second semiconductor wafer.
Polishing the region and a part of the region having the first impurity concentration.
Grinding, and simultaneously with or separately from this grinding, the first impurity
The surface of the region with the concentration is made so that fine irregularities remain.
Polishing to obtain a third semiconductor wafer; and thermally oxidizing the polished surface of the third semiconductor wafer.
Forming a semiconductor oxide film by etching, and removing the oxide film by etching to form the first non-conductive film.
Fourth semiconductor wafer in which the surface of the pure concentration region is smoothed
Obtaining step c, and a region of the fourth semiconductor wafer having the first impurity concentration.
Forming a semiconductor device including at least one PN junction
Manufacturing a semiconductor device, comprising the steps of:
Construction method. 3. The entire region has a first impurity concentration.
Step of preparing a first semiconductor wafer comprising a semiconductor region
And from one and the other main surface of the first semiconductor wafer,
To obtain the same conductivity type as that of the first semiconductor wafer
Having the first impurity concentration by thermally diffusing impurities of
A second impurity higher than the first impurity concentration is provided on both sides of the region.
First and second impurity diffusion regions having a pure concentration are arranged.
Obtaining a second semiconductor wafer having the above-described configuration, and diffusing the first impurity in the second semiconductor wafer.
Polishing the region and a part of the region having the first impurity concentration.
Grinding, and simultaneously with or separately from this grinding, the first impurity
The surface of the region with the concentration is made so that fine irregularities remain.
Polishing to obtain a third semiconductor wafer; and thermally oxidizing the polished surface of the third semiconductor wafer.
Forming a semiconductor oxide film by etching, and removing the oxide film by etching to form the first non-conductive film.
Fourth semiconductor wafer in which the surface of the pure concentration region is smoothed
Obtaining step c, and a region of the fourth semiconductor wafer having the first impurity concentration.
Of the first impurity on the surface of
Form semiconductor region of conductivity type opposite to that of concentration region
Obtaining a fifth semiconductor wafer by using the semiconductor region of the opposite conductivity type of the fifth semiconductor wafer.
Semiconductor device by forming at least one PN junction in the region
A method for manufacturing a semiconductor device.