CN1212787A - Bipolar SOI device having tilted PN-junction, and method for producing such device - Google Patents
Bipolar SOI device having tilted PN-junction, and method for producing such device Download PDFInfo
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- CN1212787A CN1212787A CN97192844A CN97192844A CN1212787A CN 1212787 A CN1212787 A CN 1212787A CN 97192844 A CN97192844 A CN 97192844A CN 97192844 A CN97192844 A CN 97192844A CN 1212787 A CN1212787 A CN 1212787A
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- base
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- 238000004519 manufacturing process Methods 0.000 title description 3
- 239000004065 semiconductor Substances 0.000 claims abstract description 33
- 239000012212 insulator Substances 0.000 claims abstract description 24
- 238000005530 etching Methods 0.000 claims abstract description 7
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 19
- 229910052710 silicon Inorganic materials 0.000 claims description 19
- 239000010703 silicon Substances 0.000 claims description 19
- 239000013078 crystal Substances 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 9
- 238000002360 preparation method Methods 0.000 claims description 6
- 235000012431 wafers Nutrition 0.000 claims 10
- 239000000463 material Substances 0.000 abstract description 2
- 239000002019 doping agent Substances 0.000 description 7
- 229910052785 arsenic Inorganic materials 0.000 description 5
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 239000002210 silicon-based material Substances 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- 238000009826 distribution Methods 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000035755 proliferation Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66265—Thin film bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/7317—Bipolar thin film transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Bipolar Transistors (AREA)
Abstract
In a bipolar semiconductor-on-insulator transistor device (1) comprising an emitter region (4), a base region (5), a collector region (2) and a collector contacting region (6) in a semiconductor wafer, e.g. a monocrystalline silicon wafer (2), on top of an insulator (3), the base-emitter and collector-base junctions are tilted relative to the interface between the semiconductor wafer (2) and the insulator (3). The device can be made by anisotropic etching in order to produce a tilted surface (7) at an edge of the device or equivalently a V-groove having tilted sidewalls. The base and emitter regions (5, 4) are then produced by diffusing suitable donor and acceptor atoms into the material inside the tilted surface. Such a bipolar semiconductor-on-insulator transistor combines the high speed features of a lateral semiconductor device and the high voltage features of a vertical semiconductor device.
Description
The present invention relates to the semiconductor device on the ambipolar insulator and make the method for this device.
The design of now having submitted a plan bipolar semiconductors a large amount of, no heavy doping buried layer on Semiconductor substrate.The bipolar semiconductor that two kinds of fundamental types are arranged, i.e. transversal device and vertically device.
Transversal device is (referring to as Stephen A.Parke, Chenming Hu, Ping K.Ko: " A High-performance Lateral Bipolar Transi stor Fabricated OnSimox ", IEEE Electron Dev.Lett., 14 volumes, the 33-35 page or leaf, in January, 1993, and R.Dekker, W.T.A.v.d.Einden and H.G.R.Mass: " An UltraLow Power Lateral Bipolar Emitter Technology on SOI ", 1993 IEDM proceedings, the 75-77 page or leaf) be suitable for high-speed applications, but can only bear very little voltage.
Vertically device is (referring to as Andrej Litwin and Torkel Arnborg: the bipolar SOI transistor of compact superhigh pressure compatibility " Compact Very High Voltage CompatibleBipolar Silicon-On-Insulator Transistor " ISPSD ' 94, Davos, in June, 1994, with United States Patent (USP) NO.4,868,624) be more suitable for bearing the application of high pressure and moderate switching speed.
Isolate shallow transversal device than isolating the easier realization of vertical device, this is because utilize simple LOCOS or mesa-isolated to replace groove or knot face to isolate.Yet, being difficult to the doping of control base stage and emitter, this is because will utilize horizontal proliferation.The puncture voltage BV of transversal device
CeoLower than vertical device, BV wherein
Ceo=BV
CboOn the other hand, can bear high-tension vertical device and have the low shortcoming of switching speed, this is (to see Torkel Arnborg: the high speed that has the collector electrode that exhausts fully because be subjected to the restriction of the transit time of the semiconductor-insulator interface transmission of horizontal carrier below base stage that the electromotive force locking-up effect causes, transistorized model of high-voltage bipolar SOI and simulation " Modelling and Simulation of High Speed, HighVoltage Bipolar SOI Transistor with fully Depleted Collector " are published in IEDM proceeding in 1994).
An object of the present invention is to provide a kind of high speed characteristics and vertical semiconductor device on the ambipolar insulator that combines of the high pressure characteristics of semiconductor device with horizontal semiconductor device.
The semiconductor device that utilization has on the ambipolar insulator of inclination base-emitter knot face and collector-base junction face can be realized this purpose.
The method that comprises the semiconductor device on the ambipolar insulator of base with inclination configuration and emitter region by manufacturing also can realize this purpose.
At length introduce the present invention below with reference to accompanying drawing in the mode of non-limiting example, wherein:
-Fig. 1 is the generalized section of ambipolar semiconductor on insulator device,
The dopant distribution figure of-Fig. 2 and 3 for calculating at emitter place according to the bipolar device of Fig. 1,
The dopant distribution figure of-Fig. 4 for measuring at emitter place according to the bipolar device of Fig. 1.
Fig. 1 illustrates the embodiment of ambipolar semiconductor on insulator device 1, and wherein semiconductor is a silicon single crystal wafer, and device 1 is silicon-on-insulator (SOI) semiconductor device thus.Silicon wafer represents with 2, and insulator for example silicon oxide layer represent with 3, be positioned under the silicon wafer, as can be seen from the figure.Illustrated device is generally rectangular section.
The inclination angle at the interface between base-emitter knot face and collector-base junction face and silicon wafer 2 and the insulator 3 is usually in 45 ° ± 20 ° scope, promptly between 25 and 65 °.
Emitter and base region 4,5 are positioned at the top edge line place of the chip architecture with inclined surface 7, can obtain this configuration by the folding corner region that cuts away rectangular section.Emitter and base region are positioned at this inclined surface 7, and base region 5 is for being located immediately at the thin layer in the inclined surface, and emitter region 4 is for being located immediately at the thin layer in the emitter region, and therefore, emitter and base region are parallel to inclined surface 7 and extend.Inclined surface 7 only is the surface of silicon layer 2, does not extend to insulating barrier 3.Collector electrode contact zone 6 is positioned at the top edge line of the structure relative with inclined surface 7 residing edges.
The method of semiconductor device shown in the manufacturing 1 comprises the anisotropic etching soi film, is (100) silicon wafer face along the surface of soi film.Carry out etching with KOH solution,, make this total surface along silicon wafer 2 (111) crystal face settings so that make inclined surface 7.Only carry out etching, before etch step, need to apply suitable mask at a transverse edge place of soi film.On base region 5 and emitter 4, mix, so that they are parallel with inclined surface 7, thus parallel with (111) crystal face in the silicon wafer 2, suppose to be included in the collector electrode contact zone 6 that certain is made in the treatment step morning.(111) crystal face with silicon wafer 2 is identical with respect to the inclination angle of the upper surface of silicon wafer 2 thus for the parallel base-emitter knot face and the inclination angle of collector-base junction face.At last prepare emitter, base stage and collector electrode and contact (not shown) with forming alloyings on these regional tops or on suitable contact position, forming polysilicon structure as locating the heavy doping contact zone in place in some conventional modes.This method can be used for preparing transistor on wafer, for example be used for having on same chip the integrated circuit of different assemblies.Carry out the anisotropic etching preparation then and make V-shaped groove with sidewall along (111) crystal face of silicon single crystal material.In V-shaped groove, its suitable diffuse dopants prepares base and emitter region in silicon materials.The difference of this method and the transistorized conventional method of preparation was mainly that before diffusing step V-shaped groove that preparation V-shaped groove or preparation have a skew wall replaces having the rectangle facet groove perpendicular to the sidewall of wafer surface.
Fig. 2 shows for the one dimension simulation curve of the transistorized exemplary embodiments edge of introducing with reference to figure 1 perpendicular to the dopant profiles of inclined surface 7 interceptings of emitter 4.The different curves that draw show the concentration of arsenic, boron and phosphorus and the functional relation of surperficial 7 distances of distance.In addition, show net dopant concentration.In the curve of Fig. 3, show the functional relation of net donor concentration and net acceptor concentration and same distance.Show net dopant concentration at this equally.
In Fig. 4, for the npn transistor that is mixed with arsenic and boron, actual concentrations measured value that shows dopant atom equally and functional relation apart from the same vertical range of the inclined surface of emitter region.
Yet, should be understood that except the etching of above introduction other method also can be used to prepare the parallel base-emitter knot face and the collector-base junction face of inclination.In addition,, be used to prepare the inclined surface that will mix, to obtain to be parallel to the base and the emitter region of the crystal orientation face that exposes except (111) crystal face of silicon wafer can also expose other crystal orientation face.
Select the size of soi film, the electric field perpendicular to the EB junction face is reduced.To increase the puncture voltage of semiconductor device like this.Because its geometric figure, electric charge is injected into the collector electrode space charge region along the direction of electric field.Owing to do not have electromotive force locking, so transverse electric field is definitely non-vanishing, by drift rather than resemble to have and transmit by diffusion the semiconductor device that exhausts collector electrode fully.This characteristic makes the semiconductor device of above introduction compare with horizontal semiconductor device to have faster speed.
In addition, should be understood that the present invention is not limited to use silicon as semi-conducting material in semiconductor on insulator device.Outside the silica removal, also can use for example GaAs or SiC equally.
Claims (6)
1. an ambipolar semiconductor on insulator device (1), the emitter region (4), base (5) and the collector region that comprise the semiconductor wafer (2) that is positioned on the insulator (3) are characterised in that base-emitter knot face and collector-base junction face tilt with respect to the interface between semiconductor wafer (2) and the insulator (3).
2. according to the device of claim 1, the inclination angle that is characterised in that base-emitter knot face and collector-base junction face is in 45 ° ± 20 ° scope.
3. according to the device of claim 1 or 2, when semiconductor wafer when making, is characterised in that the inclination angle of base-emitter knot face and collector-base junction face is corresponding with (111) crystal face of silicon wafer (2) by monocrystalline silicon (Si).
4. the method by the ambipolar semiconductor on insulator device of the preparation of the semiconductor wafer (2) on the insulator (3) is characterised in that base (5) and emitter region (4) that the interface between wafers doped preparation and semiconductor wafer (2) and the insulator (3) tilts.
5. according to the method for claim 4, the inclination angle that is characterised in that base-emitter knot face and collector-base junction face is in 45 ° ± 20 ° scope.
6. according to the device of claim 4 or 5, when semiconductor wafer by monocrystalline silicon (Si) when making, be characterised in that in doping to be parallel to the base (5) of (111) crystal face of the silicon wafer (2) that exposes and emitter region (4) before, it a transverse edge place anisotropically etching semiconductor wafer (2) (111) crystal face is exposed.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| SE9600898A SE506510C2 (en) | 1996-03-07 | 1996-03-07 | Semiconductors including inclined base emitter and collector base transitions and method for producing such |
| SE9600898-2 | 1996-03-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1212787A true CN1212787A (en) | 1999-03-31 |
Family
ID=20401711
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN97192844A Pending CN1212787A (en) | 1996-03-07 | 1997-03-05 | Bipolar SOI device having tilted PN-junction, and method for producing such device |
Country Status (8)
| Country | Link |
|---|---|
| EP (1) | EP0963610A1 (en) |
| JP (1) | JP2000506311A (en) |
| KR (1) | KR19990087554A (en) |
| CN (1) | CN1212787A (en) |
| AU (1) | AU2049397A (en) |
| CA (1) | CA2243998A1 (en) |
| SE (1) | SE506510C2 (en) |
| WO (1) | WO1997033319A1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100197001B1 (en) * | 1996-05-02 | 1999-07-01 | 구본준 | Bipolar device and manufacturing method thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE1589453A1 (en) * | 1966-06-28 | 1970-04-02 | Asea Ab | Semiconductor device |
| DE4001350C2 (en) * | 1989-01-18 | 1993-10-07 | Nissan Motor | Semiconductor device |
-
1996
- 1996-03-07 SE SE9600898A patent/SE506510C2/en not_active IP Right Cessation
-
1997
- 1997-03-05 EP EP97908624A patent/EP0963610A1/en not_active Withdrawn
- 1997-03-05 WO PCT/SE1997/000377 patent/WO1997033319A1/en not_active Application Discontinuation
- 1997-03-05 KR KR1019980706992A patent/KR19990087554A/en active IP Right Grant
- 1997-03-05 CN CN97192844A patent/CN1212787A/en active Pending
- 1997-03-05 JP JP9531710A patent/JP2000506311A/en active Pending
- 1997-03-05 AU AU20493/97A patent/AU2049397A/en not_active Abandoned
- 1997-03-05 CA CA002243998A patent/CA2243998A1/en not_active Abandoned
Also Published As
| Publication number | Publication date |
|---|---|
| JP2000506311A (en) | 2000-05-23 |
| SE9600898L (en) | 1997-09-08 |
| SE9600898D0 (en) | 1996-03-07 |
| CA2243998A1 (en) | 1997-09-12 |
| WO1997033319A1 (en) | 1997-09-12 |
| EP0963610A1 (en) | 1999-12-15 |
| KR19990087554A (en) | 1999-12-27 |
| AU2049397A (en) | 1997-09-22 |
| SE506510C2 (en) | 1997-12-22 |
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