WO1997033319A1 - Bipolar soi device having a tilted pn-junction, and a method for producing such a device - Google Patents

Bipolar soi device having a tilted pn-junction, and a method for producing such a device Download PDF

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Publication number
WO1997033319A1
WO1997033319A1 PCT/SE1997/000377 SE9700377W WO9733319A1 WO 1997033319 A1 WO1997033319 A1 WO 1997033319A1 SE 9700377 W SE9700377 W SE 9700377W WO 9733319 A1 WO9733319 A1 WO 9733319A1
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WO
WIPO (PCT)
Prior art keywords
base
emitter
region
insulator
tilted
Prior art date
Application number
PCT/SE1997/000377
Other languages
French (fr)
Inventor
Andrej Litwin
Torkel Arnborg
Original Assignee
Telefonaktiebolaget L M Ericsson (Publ)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telefonaktiebolaget L M Ericsson (Publ) filed Critical Telefonaktiebolaget L M Ericsson (Publ)
Priority to AU20493/97A priority Critical patent/AU2049397A/en
Priority to EP97908624A priority patent/EP0963610A1/en
Priority to JP9531710A priority patent/JP2000506311A/en
Publication of WO1997033319A1 publication Critical patent/WO1997033319A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66265—Thin film bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/7317—Bipolar thin film transistors

Definitions

  • the invention relates to a bipolar semiconductor-on-insulator sdevice as well as to a method of producing such a device.
  • bipolar semiconductor devices A large number of bipolar semiconductor devices be designed without heavily doped, buried layers on semiconductor substrates has been proposed.
  • Isolating shallow lateral devices can be achieved more easily 25than isolating vertical devices since a simple LOCOS or mesa isolation can be utilized instead of a trench or junction isolation. However, the control of base and emitter doping is difficult, since lateral diffusion has to be utilized.
  • the object of the invention is to provide a bipolar semicon ⁇ ductor-on-insulator device which combines the high speed s features of a lateral semiconductor device and the high voltage features of a vertical semiconductor device.
  • This object is attained by a bipolar semiconductor-on-insulator device having base-emitter and collector-base junctions which are tilted.
  • ⁇ oThis object is also attained by a method of producing a bipolar semiconductor-on-insulator device comprising that the base region and the emitter region are produced to have a tilted con ⁇ figuration.
  • Fig. 1 is a schematic cross-sectional view of a bipolar semi ⁇ conductor-on-insulator device
  • Figs . 2 and 3 are diagrams illustrating calculated dopant profiles at the emitter of a bipolar device according to Fig. 1,
  • Fig. 4 is a diagram illustrating measured dopant profiles at the emitter of a bipolar device according to Fig. 1.
  • FIG. 25 Figure 1 schematically shows an embodiment of a bipolar semi ⁇ conductor-on-insulator device 1, where the semiconductor is a monocrystalline silicon wafer, the device 1 thus being a silicon-on-insulator (SOI) semiconductor device.
  • the silicon wafer is denoted 2
  • the insulator e.g. a silicon oxide
  • the device as illustrated has a generally rectangular cross-section.
  • the silicon wafer 2 includes an emitter region 4, a base region 5, and a collector contacting region 6, the collector being the region of the bulk silicon material 2 located between the base region 5 and the collector contacting region 6.
  • the emitter region 4 has an n-doping of e.g. arsenic
  • the base region has a p-doping of e.g. boron
  • the collector con ⁇ tacting region 6 has a heavy n-doping of e.g. arsenic.
  • the base-emitter junction and the collector- base junction are parallel to each other and they are both tilted in relation to the interface between the silicon wafer 2 ⁇ oand the insulator 3. This is accomplished by the fact that the thin emitter region or layer 4 and the thin base region or layer 5 are tilted in relation to said interface between the silicon wafer 2 and the insulator 3.
  • the angle of tilt of the base-emitter and collector-base isjunctions in relation to the interf ce between the silicon wafer 2 and the insulator 3, is typically in the range of 45° ⁇ 20°, i.e. between 25 and 65°.
  • the emitter and base regions 4, 5 are located at an upper edge line of the wafer structure where the structure has a tilted
  • the configuration being obtained by cutting away a corner region of the generally rectangular cross-section.
  • the emitter and base regions are located at this tilted surface 7, the emitter region 5 being a thin layer located directly inside the tilted surface and the base region 4 being a thin layer
  • the emitter and base regions thus extending in parallel to the tilted surface 7.
  • the tilted surface 7 is only a surface of the silicon layer 2 and does not extend into the insulator layer 3.
  • the collector con ⁇ tacting region 6 is located at the upper edge line of the
  • a method of producing the semiconductor device 1 shown comprises etching anisotropically an SOI film, having a (100) silicon crystal orientation of the plane along its surface.
  • the etching 5 is made with a solution of KOH in order to produce the tilted surface 7 achieving that this surface will always be located along a (111) crystal plane of the silicon wafer 2.
  • T he etc h ing is made only at one of the lateral edges of the SOI film, re ⁇ quiring that a suitable mask is applied before the etching step.
  • a base region 5 and an emitter region 4 are doped so that they will be parallel to the tilted surface 7 and thus to a s (111) crystal plane in the silicon wafer 2, which is supposed to already include a collector contacting region 6 made in some earlier processing step.
  • the angle of tilt of the parallel base- emitter and collector-base junctions will thus correspond to the angle of tilt of the (111) crystal plane of the silicon wafer 2 ⁇ oin relation to its upper surface.
  • Emitter-, base- and collector contacts, not shown, are finally produced in some conventional way such as by making heavily doped contacting regions at suitable places and by producing metallizations on top of these regions or by making polysilicon structures at suitable con- istacting places.
  • the method can also be used for producing transistors on a wafer such as for an integrated circuit having several different com ⁇ ponents on the same chip. Then the anisotropic etching is made to produce V-grooves having sides walls located along (111)
  • the diagram of Fig. 2 shows a one-dimensional simulation of the 30doping profiles as taken perpendicularly to the tilted surface 7 of the emitter 4 for a typical embodiment of a transistor as described with reference to Fig. 1.
  • the various lines drawn illustrate the concentrations of arsenic, boron and phosphorous as functions of the distance from the surface 7.
  • the net 35dopant concentration is shown.
  • the net donor concentration and the net acceptor concentrations are illustrated as functions of the same distance.
  • the net dopant concentration is shown.
  • measured values of the actual concentrations of dopant atoms are shown for a npn-transis or doped with arsenic and boron, also as functions of the same perpendicular distance from the tilted surface of the emitter region.
  • etching as described above may be used to produce tilted parallel base-emitter and collector-base junctions.
  • another crystal surface than the (111) crystal plane of the silicon wafer may be exposed for producing the tilted surface to ⁇ o e doped to achieve a base region and an emitter region parallel to the exposed crystal surface.
  • the dimensions of the SOI film are chosen in such a way that the electric field perpendicular to the emitter-base junction will be reduced. This will increase the breakdown voltage of the issemiconductor device. Due to its geometry, the charge is injected into the collector space charge region in the direction of the electric field. Since no potential lock-up is present, and thus, the lateral field is never zero, the transport will be by drift and not by diffusion as in the case of a semiconductor
  • the invention is not re ⁇ stricted to the use of silicon as a semiconducting material in 25the semiconductor-on-insulator device.
  • silicon e.g. GaAs or SiC may equally well be used.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Transistors (AREA)

Abstract

In a bipolar semiconductor-on-insulator transistor device (1) comprising an emitter region (4), a base region (5), a collector region (2) and a collector contacting region (6) in a semiconductor wafer, e.g. a monocrystalline silicon wafer (2), on top of an insulator (3), the base-emitter and collector-base junctions are tilted relative to the interface between the semiconductor wafer (2) and the insulator (3). The device can be made by anisotropic etching in order to produce a tilted surface (7) at an edge of the device or equivalently a V-groove having tilted sidewalls. The base and emitter regions (5, 4) are then produced by diffusing suitable donor and acceptor atoms into the material inside the tilted surface. Such a bipolar semiconductor-on-insulator transistor combines the high speed features of a lateral semiconductor device and the high voltage features of a vertical semiconductor device.

Description

BIPOLAR SOI DEVICE HAVING A TILTED PN-JUNCTΪON. AND A METHOD FOR PRODUCING SUCH A DEVICE
TECHNICAL FIELD
The invention relates to a bipolar semiconductor-on-insulator sdevice as well as to a method of producing such a device.
BACKGROUND AND PRIOR ART
A large number of bipolar semiconductor devices be designed without heavily doped, buried layers on semiconductor substrates has been proposed. There are two basic types of such bipolar 10 semiconductor devices, namely lateral devices and vertical devices .
Lateral devices (see e.g. Stephen A. Parke, Chenming Hu, Ping K. Ko: "A High-Performance Lateral Bipolar Transistor Fabricated on Simox", IEEE Electron Dev. Lett., vol. 14, pp. 33-35, Jan. 1993, isand R. Dekker, W.T.A. v.d. Einden and H.G.R. Maas: "An Ultra Low Power Lateral Bipolar Emitter Technology on SOI", 1993 IEDM Conference Digest, pp. 75-77), are intended for high speed applications but are able to support only quite small voltages.
Vertical devices (see e.g. Andrej Litwin and Torkel Arnborg: 20 "Compact Very High Voltage Compatible Bipolar Silicon-On- Insulator Transistor", ISPSD'94, Davos, June 1994, and U.S. Patent No. 4,868,624) are intended more for high voltages and moderate switching velocities.
Isolating shallow lateral devices can be achieved more easily 25than isolating vertical devices since a simple LOCOS or mesa isolation can be utilized instead of a trench or junction isolation. However, the control of base and emitter doping is difficult, since lateral diffusion has to be utilized. The lateral devices exhibit lower breakdown voltages BVceo than 3overtical devices, in which BVceo = BVcbo. On the other hand, vertical devices which are capable of supporting high voltages, suffer from low switching speeds, limited by the transit time for lateral carrier transport along the semiconductor-insulator interface below the base due to potential lock-up (see Torkel asArnborg: "Modelling and Simulation of High Speed, High Voltage Bipolar SOI Transistor with fully Depleted Collector" presented in 1994 IEDM Conference Digest) .
SUMMARY
The object of the invention is to provide a bipolar semicon¬ ductor-on-insulator device which combines the high speed s features of a lateral semiconductor device and the high voltage features of a vertical semiconductor device.
This object is attained by a bipolar semiconductor-on-insulator device having base-emitter and collector-base junctions which are tilted.
ιoThis object is also attained by a method of producing a bipolar semiconductor-on-insulator device comprising that the base region and the emitter region are produced to have a tilted con¬ figuration.
BRIEF DESCRIPTION OF THE DRAWINGS isThe invention will be described in detail by way of a non- limiting embodiment with reference to the accompanying drawings in which:
- Fig. 1 is a schematic cross-sectional view of a bipolar semi¬ conductor-on-insulator device,
20- Figs . 2 and 3 are diagrams illustrating calculated dopant profiles at the emitter of a bipolar device according to Fig. 1,
- Fig. 4 is a diagram illustrating measured dopant profiles at the emitter of a bipolar device according to Fig. 1.
DETAILED DESCRIPTION
25Figure 1 schematically shows an embodiment of a bipolar semi¬ conductor-on-insulator device 1, where the semiconductor is a monocrystalline silicon wafer, the device 1 thus being a silicon-on-insulator (SOI) semiconductor device. The silicon wafer is denoted 2, whereas the insulator, e.g. a silicon oxide
30 layer, is denoted 3 and is located underneath the silicon wafer as seen in the figure. The device as illustrated has a generally rectangular cross-section.
The silicon wafer 2 includes an emitter region 4, a base region 5, and a collector contacting region 6, the collector being the region of the bulk silicon material 2 located between the base region 5 and the collector contacting region 6. In an npn- transistor the emitter region 4 has an n-doping of e.g. arsenic, the base region has a p-doping of e.g. boron, the bulk silicon
5material has a n doping of e.g. arsenic and the collector con¬ tacting region 6 has a heavy n-doping of e.g. arsenic. In the silicon wafer 2, the base-emitter junction and the collector- base junction are parallel to each other and they are both tilted in relation to the interface between the silicon wafer 2 ιoand the insulator 3. This is accomplished by the fact that the thin emitter region or layer 4 and the thin base region or layer 5 are tilted in relation to said interface between the silicon wafer 2 and the insulator 3.
The angle of tilt of the base-emitter and collector-base isjunctions in relation to the interf ce between the silicon wafer 2 and the insulator 3, is typically in the range of 45° ± 20°, i.e. between 25 and 65°.
The emitter and base regions 4, 5 are located at an upper edge line of the wafer structure where the structure has a tilted
20surface 7, the configuration being obtained by cutting away a corner region of the generally rectangular cross-section. The emitter and base regions are located at this tilted surface 7, the emitter region 5 being a thin layer located directly inside the tilted surface and the base region 4 being a thin layer
25located directly inside the emitter region, the emitter and base regions thus extending in parallel to the tilted surface 7. The tilted surface 7 is only a surface of the silicon layer 2 and does not extend into the insulator layer 3. The collector con¬ tacting region 6 is located at the upper edge line of the
30structure which is opposite the edge where the tilted surface 7 is located.
A method of producing the semiconductor device 1 shown comprises etching anisotropically an SOI film, having a (100) silicon crystal orientation of the plane along its surface. The etching 5is made with a solution of KOH in order to produce the tilted surface 7 achieving that this surface will always be located along a (111) crystal plane of the silicon wafer 2. The etching is made only at one of the lateral edges of the SOI film, re¬ quiring that a suitable mask is applied before the etching step. Thereupon a base region 5 and an emitter region 4 are doped so that they will be parallel to the tilted surface 7 and thus to a s (111) crystal plane in the silicon wafer 2, which is supposed to already include a collector contacting region 6 made in some earlier processing step. The angle of tilt of the parallel base- emitter and collector-base junctions will thus correspond to the angle of tilt of the (111) crystal plane of the silicon wafer 2 ιoin relation to its upper surface. Emitter-, base- and collector contacts, not shown, are finally produced in some conventional way such as by making heavily doped contacting regions at suitable places and by producing metallizations on top of these regions or by making polysilicon structures at suitable con- istacting places.
The method can also be used for producing transistors on a wafer such as for an integrated circuit having several different com¬ ponents on the same chip. Then the anisotropic etching is made to produce V-grooves having sides walls located along (111)
2oplanes of the silicon monocrystalline material. In the V- grooves, from the sides thereof suitable dopants are diffused into the silicon material to produce the base and emitter regions. This method will then differ from conventional methods of producing transistors mainly in the step of producing the V-
25grooves before the diffusion steps or in producing V-grooves having tilted sidewalls instead of rectangular cross-section grooves having sidewalls perpendicular to the surface of the wafer.
The diagram of Fig. 2 shows a one-dimensional simulation of the 30doping profiles as taken perpendicularly to the tilted surface 7 of the emitter 4 for a typical embodiment of a transistor as described with reference to Fig. 1. The various lines drawn illustrate the concentrations of arsenic, boron and phosphorous as functions of the distance from the surface 7. Also, the net 35dopant concentration is shown. In the diagram of Fig. 3 the net donor concentration and the net acceptor concentrations are illustrated as functions of the same distance. Also here, the net dopant concentration is shown. In Fig. 4 measured values of the actual concentrations of dopant atoms are shown for a npn-transis or doped with arsenic and boron, also as functions of the same perpendicular distance from the tilted surface of the emitter region.
sit is to be understood, however, that other methods in addition to etching as described above may be used to produce tilted parallel base-emitter and collector-base junctions. Also, another crystal surface than the (111) crystal plane of the silicon wafer may be exposed for producing the tilted surface to ιo e doped to achieve a base region and an emitter region parallel to the exposed crystal surface.
The dimensions of the SOI film are chosen in such a way that the electric field perpendicular to the emitter-base junction will be reduced. This will increase the breakdown voltage of the issemiconductor device. Due to its geometry, the charge is injected into the collector space charge region in the direction of the electric field. Since no potential lock-up is present, and thus, the lateral field is never zero, the transport will be by drift and not by diffusion as in the case of a semiconductor
20device having a fully depleted collector. This feature will make the semiconductor device as described above faster having a per¬ formance comparable to a lateral semiconductor device.
Moreover, it is to be understood that the invention is not re¬ stricted to the use of silicon as a semiconducting material in 25the semiconductor-on-insulator device. Instead of silicon, e.g. GaAs or SiC may equally well be used.

Claims

1. A bipolar semiconductor-on-insulator device (1) comprising an emitter region (4), a base region (5), and a collector region in a semiconductor wafer (2) on an insulator (3), characterized in sthat the base-emitter and collector-base junctions are tilted in relation to the interface between the semiconductor wafer (2) and the insulator (3).
2. A device according to claim 1, characterized in that the angle of tilt of the base-emitter and collector-base junctions ιois in the range of 45° ± 20°.
3. A device according to claim 1 or 2, in the case where the semiconductor wafer is made of monocrystalline silicon (Si), characterized in that the angle of tilt of the base-emitter and collector-base junctions corresponds to the (111) crystal plane isof the silicon wafer (2).
4. A method of producing a bipolar semiconductor-on-insulator device from a semiconductor wafer (2) on an insulator (3), chaxacterized by doping the wafer to produce a base region (5) and an emitter region (4) which are tilted in relation to the
20interface between the semiconductor wafer (2) and the insulator (3).
5. A method according to claim 4, characterized in that the base-emitter and collector-base junctions are tilted in an angle in the range of 45° ± 20°.
256. A method according to claim 4 or 5, in the case where the semiconductor wafer is made of monocrystalline silicon (Si), characterized by anisotropically etching the silicon wafer (2) to expose a (111) crystal plane at one of lateral edges thereof before doping the base region (5) and the emitter region (4)
30parallel to the exposed (111) crystal plane of the silicon wafer (2).
PCT/SE1997/000377 1996-03-07 1997-03-05 Bipolar soi device having a tilted pn-junction, and a method for producing such a device WO1997033319A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
AU20493/97A AU2049397A (en) 1996-03-07 1997-03-05 Bipolar soi device having a tilted pn-junction, and a method for producing such a device
EP97908624A EP0963610A1 (en) 1996-03-07 1997-03-05 Bipolar soi device having a tilted pn-junction, and a method for producing such a device
JP9531710A JP2000506311A (en) 1996-03-07 1997-03-05 Bipolar SOI device with graded PN junction and method of manufacturing such device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SE9600898-2 1996-03-07
SE9600898A SE506510C2 (en) 1996-03-07 1996-03-07 Semiconductors including inclined base emitter and collector base transitions and method for producing such

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Publication Number Publication Date
WO1997033319A1 true WO1997033319A1 (en) 1997-09-12

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EP (1) EP0963610A1 (en)
JP (1) JP2000506311A (en)
KR (1) KR19990087554A (en)
CN (1) CN1212787A (en)
AU (1) AU2049397A (en)
CA (1) CA2243998A1 (en)
SE (1) SE506510C2 (en)
WO (1) WO1997033319A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6482712B1 (en) * 1996-05-02 2002-11-19 Lg Semicon Co., Ltd. Method for fabricating a bipolar semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1188688A (en) * 1966-06-28 1970-04-22 Asea Ab Semi-conductor Device
US5040034A (en) * 1989-01-18 1991-08-13 Nissan Motor Co., Ltd. Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1188688A (en) * 1966-06-28 1970-04-22 Asea Ab Semi-conductor Device
US5040034A (en) * 1989-01-18 1991-08-13 Nissan Motor Co., Ltd. Semiconductor device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN, Vol. 95, No. 1; & JP,A,06 295 921 (CANON INC) 21 October 1994. *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6482712B1 (en) * 1996-05-02 2002-11-19 Lg Semicon Co., Ltd. Method for fabricating a bipolar semiconductor device

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CA2243998A1 (en) 1997-09-12
SE9600898L (en) 1997-09-08
JP2000506311A (en) 2000-05-23
CN1212787A (en) 1999-03-31
AU2049397A (en) 1997-09-22
SE9600898D0 (en) 1996-03-07
SE506510C2 (en) 1997-12-22
KR19990087554A (en) 1999-12-27
EP0963610A1 (en) 1999-12-15

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