CA2243998A1 - Bipolar soi device having a tilted pn-junction, and a method for producing such a device - Google Patents
Bipolar soi device having a tilted pn-junction, and a method for producing such a device Download PDFInfo
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- CA2243998A1 CA2243998A1 CA002243998A CA2243998A CA2243998A1 CA 2243998 A1 CA2243998 A1 CA 2243998A1 CA 002243998 A CA002243998 A CA 002243998A CA 2243998 A CA2243998 A CA 2243998A CA 2243998 A1 CA2243998 A1 CA 2243998A1
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- insulator
- tilted
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- 238000004519 manufacturing process Methods 0.000 title 1
- 239000012212 insulator Substances 0.000 claims abstract description 25
- 239000004065 semiconductor Substances 0.000 claims abstract description 22
- 238000005530 etching Methods 0.000 claims abstract description 8
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 20
- 229910052710 silicon Inorganic materials 0.000 claims description 20
- 239000010703 silicon Substances 0.000 claims description 20
- 239000013078 crystal Substances 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 9
- 239000000463 material Substances 0.000 abstract description 3
- 239000002019 doping agent Substances 0.000 description 6
- 229910052785 arsenic Inorganic materials 0.000 description 5
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 239000000306 component Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000004576 sand Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66265—Thin film bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/7317—Bipolar thin film transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Bipolar Transistors (AREA)
Abstract
In a bipolar semiconductor-on-insulator transistor device (1) comprising an emitter region (4), a base region (5), a collector region (2) and a collector contacting region (6) in a semiconductor wafer, e.g. a monocrystalline silicon wafer (2), on top of an insulator (3), the base-emitter and collector-base junctions are tilted relative to the interface between the semiconductor wafer (2) and the insulator (3). The device can be made by anisotropic etching in order to produce a tilted surface (7) at an edge of the device or equivalently a V-groove having tilted sidewalls. The base and emitter regions (5, 4) are then produced by diffusing suitable donor and acceptor atoms into the material inside the tilted surface. Such a bipolar semiconductor-on-insulator transistor combines the high speed features of a lateral semiconductor device and the high voltage features of a vertical semiconductor device.
Description
B~POLAR SOT DEvrCE ~AV~NG A TILl'ED PN-JUNCrlON. AND A MEIHOD FOR PRODUCTNG
SUCH A DEVICE
TECHNICAL FIE~D
The invention relates to a bipolar semiconductor-on-insulator 5 device as well as to a method of producing such a device.
R~RG~OUND AND PRIOR ART
A large number of bipolar semiconductor devices be designed without heavily doped, buried layers on semiconductor substrates has been proposed. There are two basic types of such bipolar osemiconductor devices, namely lateral devices and vertical devices.
Lateral devices (see e.g. Stephen A. Parke, Chenming ~u, Ping R.
Ko: "A High-Performance Lateral Bipolar Transistor Fabricated on Simox", IEEE Electron Dev. Lett., vol. 14, pp. 33-35, Jan. 1993, ~sand R. Dekker, W.T.A. v.d. Einden and H.G.R. Maas: "An Ultra Low Power ~ateral Bipolar Emitter Technology on SOI", ~993 IEDM
Conference Digest, pp. 7~-77~, are intended for high speed applications but are able to support only quite small voltages.
Vertical devices (see e.g. Andrej Litwin and Torkel Arnborg:
~"Compact Very High Voltage Compatible Bipolar Silicon-On-Insulator Transistor", ISPSD'94, Davos, June 1994, and U.S.
Patent No. 4,8~8,624) are intended more for high voltages and moderate switching velocities.
Isolating shallow lateral devices can be achieved more easily ~than isolating vertical devices since a simple LOCOS or mesa isolation can be utilized instead of a trench or iunction isolation. However, the control of base and emitter doping is difficult, since lateral diffusion has to be utilized. The lateral devices exhibit lower breakdown voltages BVCeo than ~vertical devices, in which BVCeo = BVC~o. On the other hand, vertical devices which are capable of supporting high voltages, suffer from low switching speeds, limited by the transit time for lateral carrier transport along the semiconductor-insulator interface below the base due to potential lock-up (see Torkel ~Arnborg: ~Modelling and Simulation of High Speed, High Voltage Bipolar SOI Transistor with fully Depleted Collector" presented in 1994 IEDM Conference Digest).
SUMMARY
The o~ject of the invention is to provide a bipolar semicon-ductor-on-insulator device which combines the high speed 5 features of a lateral semiconductor device and the high voltage features of a vertical semiconductor device.
This object is attained by a bipolar semiconductor-on-insulator device having base-emitter and collector-base junctions which are tilted.
o~his object is also attAine~ by a method of producing a bipolar semiconductor-on-insulator device comprising that the base region and the emitter region are produced to have a tilted con-figuration.
BRIEF DESCRIPTION OF THE DRAWINGS
t~ The invention will be described in detail by way of a non-limiting embodiment with reference to the accompanying drawings in which:
- Fig. 1 is a schematic cross-~ectional view of a bipolar semi-conductor-on-insulator device, ~- Figs. 2 and 3 are diagrams illustrating calculated dopant profiles at the emitter of a bipolar device according to Fig. 1, - Fig. 4 is a diagram illustrating measured dopant pro~iles at the emitter of a bipolar device according to Fig. 1.
DETATT.F~ DESCRIPTION
~Figure 1 schematically shows an embodiment of a bipolar semi-conductor-on-insulator device 1, where the semiconductor is a monocrystalline silicon wafer, the device 1 thus being a silicon-on-insulator (SOI) semiconductor device. The silicon wafer ifi denoted 2, whereas the insulator, e.g. a silicon oxide ~layer, is denoted 3 and is located underneath the silicon wafer as seen in the figure. The device as illustrated has a generally rectangular cross-section.
The silicon wafer 2 includes an emitter region 4, a base region 5, and a collector contacting region 6, the collector being the -CA 02243998 l998-07-22 region of the bulk silicon material 2 located between the base region 5 and the collector contacting region 6. In an npn-transistor the emitter region 4 has an n-doping of e.g. arsenic, the base region has a p-doping of e.g. boron, the bulk silicon 5 material has a n doping of e.g. arsenic and the collector con-tacting region 6 has a heavy n-doping of e.g. arsenic. In the silicon wafer 2, the base-emitter junction and the collector-base junction are parallel to each other and they are both tilted in relation to the interface between the silicon wafer 2 ~oand the insulator 3. This is accomplished by the fact that the thin emitter region or layer 4 and the thin base region or layer 5 are tilted in relation to said interface between the silicon wafer 2 and the insulator 3.
The angle of tilt of the base-emitter and collector-base 15 junctions in relation to the interface between the silicon wafer 2 and the insulator 3, is typically in the range of 45~ + 20~, i.e. between 25 and 6~~.
The emitter and base regions 4, 5 are located at an upper edge line of the wafer structure where the structure has a tilted ~surface 7, the configuration being obt~ine~ by cutting away a corner region of the generally rectangular cross-section. The emitter and base regions are located at this tilted surface 7, the emitter region 5 being a thin layer located directly inside the tilted surface and the base region 4 being a thin layer ~located directly inside the emitter region, the emitter and base regions thus ext~n~i ng in parallel to the tilted surface 7. The tilted surface 7 is only a surface of the silicon layer 2 and does not extend into the insulator layer 3. The collector con-tacting region 6 is located at the upper edge line of the ~structure which is opposite the edge where the tilted surface 7 is located.
A method of producing the semiconductor device 1 shown comprises etching anisotropically an SOI film, having a (100) silicon crystal orientation of the plane along its surface. The etching ~is made with a solution of KOH in order to produce the tilted surface 7 achieving that this surface will always be located along a ~111) crystal plane of the silicon wafer 2. The etching i8 made only at one of the lateral edges of the SOI film, re-~uiring that a suitable mask is applied before the etching step.
Thereupon a base region 5 and an emitter region 4 are doped so that they will ~e parallel to the tilted surface 7 and thus to a s(lll) crystal plane in the silicon wafer 2, which is supposed to already include a collector contacting region 6 made in some earlier processing step. The angle of tilt of the parallel base-emitter and collector-base junctions will thus correspond to the angle of tilt of the (111) crystal plane of the silicon wafer 2 10 in relation to its upper surface. Emitter-, base- and collector con~acts, not shown, are finally produced in some conventional way such as by ~king heavily doped contacting regions at suitable places and by producing metallizations on top of these regions or by making polysilicon structures at suitable con-15 tacting places.
The method can also be used for producing transistors on a wa~ersuch as for an integrated circuit having several different com-ponents on the same chip. Then the anisotropic etching is made to produce V-grooves having sides walls located along (111) ~planes of the silicon monocrystalline material. In the V-grooves, from the sides thereof suitable dopants are dif~used into the silicon material to produce the base and emitter regions. This method will then differ from conventional methods of producing transistors mainly in the step of producing the V-~grooves ~efore the diffusion steps or in producing V-grooves having tilted sidewalls instead of rectangular cross-section grooves having sidewalls perpendicular to the surface of the wafer.
The diagram of Fig. 2 shows a one-dimensional simulation of the ~doping profiles as taken perpendicularly to the tilted surface 7 of the emitter 4 for a typical embodiment of a transistor as described with reference to Fig. 1. The various lines drawn illustrate the concentrations of arsenic, boron and phosphorous as functions of the distance from the surface 7. Also, the net ~dopant concentration is shown. In the diagram of Fig. 3 the net donor concentration and the net acceptor concentrations are illustrated as functions of the same distance. Also here, the net dopant concentration is shown.
. . , _ CA 02243998 l998-07-22 -In Fig. 4 measured values of the actual concentrations of dopant atoms are shown for a npn-transistor doped with arsenic and boron, also as functions of the same perpendicular distance from v the tilted surface of the emitter region.
sIt is to be understood, however, that other methods in addition to etching as described above may be used to produce tilted parallel base-emitter and collector-base junctions. Also, another crystal surface than the (lll) crystal plane of the silicon wafer may be exposed for producing the tilted surface to t~be doped to achieve a base region and an emitter region parallel to the exposed crystal surface.
The ~ n~ions of the SOI film are chosen in such a way that the electric field perpendicular to the emitter-base junction will be reduced. This will increase the breakdown voltage of the 5 semiconductor device. Due to its geometry, the charge is injected into the collector space charge region in the direction of the electric field. Since no potential lock-up is present, and thus, the lateral field is never zero, the transport will be by drift and not by diffusion 8S in the case of a semiconductor ~device having a fully depleted collector. This feature will make the semiconductor device as described above faster having a per-formance comparable to a lateral semiconductor device.
Moreover, it is to be understood that the invention is not re-stricted to the use of silicon as a semiconducting material in ~the semiconductor-on-insulator device. Instead of silicon, e.g.
GaAs or SiC may equally well be used.
SUCH A DEVICE
TECHNICAL FIE~D
The invention relates to a bipolar semiconductor-on-insulator 5 device as well as to a method of producing such a device.
R~RG~OUND AND PRIOR ART
A large number of bipolar semiconductor devices be designed without heavily doped, buried layers on semiconductor substrates has been proposed. There are two basic types of such bipolar osemiconductor devices, namely lateral devices and vertical devices.
Lateral devices (see e.g. Stephen A. Parke, Chenming ~u, Ping R.
Ko: "A High-Performance Lateral Bipolar Transistor Fabricated on Simox", IEEE Electron Dev. Lett., vol. 14, pp. 33-35, Jan. 1993, ~sand R. Dekker, W.T.A. v.d. Einden and H.G.R. Maas: "An Ultra Low Power ~ateral Bipolar Emitter Technology on SOI", ~993 IEDM
Conference Digest, pp. 7~-77~, are intended for high speed applications but are able to support only quite small voltages.
Vertical devices (see e.g. Andrej Litwin and Torkel Arnborg:
~"Compact Very High Voltage Compatible Bipolar Silicon-On-Insulator Transistor", ISPSD'94, Davos, June 1994, and U.S.
Patent No. 4,8~8,624) are intended more for high voltages and moderate switching velocities.
Isolating shallow lateral devices can be achieved more easily ~than isolating vertical devices since a simple LOCOS or mesa isolation can be utilized instead of a trench or iunction isolation. However, the control of base and emitter doping is difficult, since lateral diffusion has to be utilized. The lateral devices exhibit lower breakdown voltages BVCeo than ~vertical devices, in which BVCeo = BVC~o. On the other hand, vertical devices which are capable of supporting high voltages, suffer from low switching speeds, limited by the transit time for lateral carrier transport along the semiconductor-insulator interface below the base due to potential lock-up (see Torkel ~Arnborg: ~Modelling and Simulation of High Speed, High Voltage Bipolar SOI Transistor with fully Depleted Collector" presented in 1994 IEDM Conference Digest).
SUMMARY
The o~ject of the invention is to provide a bipolar semicon-ductor-on-insulator device which combines the high speed 5 features of a lateral semiconductor device and the high voltage features of a vertical semiconductor device.
This object is attained by a bipolar semiconductor-on-insulator device having base-emitter and collector-base junctions which are tilted.
o~his object is also attAine~ by a method of producing a bipolar semiconductor-on-insulator device comprising that the base region and the emitter region are produced to have a tilted con-figuration.
BRIEF DESCRIPTION OF THE DRAWINGS
t~ The invention will be described in detail by way of a non-limiting embodiment with reference to the accompanying drawings in which:
- Fig. 1 is a schematic cross-~ectional view of a bipolar semi-conductor-on-insulator device, ~- Figs. 2 and 3 are diagrams illustrating calculated dopant profiles at the emitter of a bipolar device according to Fig. 1, - Fig. 4 is a diagram illustrating measured dopant pro~iles at the emitter of a bipolar device according to Fig. 1.
DETATT.F~ DESCRIPTION
~Figure 1 schematically shows an embodiment of a bipolar semi-conductor-on-insulator device 1, where the semiconductor is a monocrystalline silicon wafer, the device 1 thus being a silicon-on-insulator (SOI) semiconductor device. The silicon wafer ifi denoted 2, whereas the insulator, e.g. a silicon oxide ~layer, is denoted 3 and is located underneath the silicon wafer as seen in the figure. The device as illustrated has a generally rectangular cross-section.
The silicon wafer 2 includes an emitter region 4, a base region 5, and a collector contacting region 6, the collector being the -CA 02243998 l998-07-22 region of the bulk silicon material 2 located between the base region 5 and the collector contacting region 6. In an npn-transistor the emitter region 4 has an n-doping of e.g. arsenic, the base region has a p-doping of e.g. boron, the bulk silicon 5 material has a n doping of e.g. arsenic and the collector con-tacting region 6 has a heavy n-doping of e.g. arsenic. In the silicon wafer 2, the base-emitter junction and the collector-base junction are parallel to each other and they are both tilted in relation to the interface between the silicon wafer 2 ~oand the insulator 3. This is accomplished by the fact that the thin emitter region or layer 4 and the thin base region or layer 5 are tilted in relation to said interface between the silicon wafer 2 and the insulator 3.
The angle of tilt of the base-emitter and collector-base 15 junctions in relation to the interface between the silicon wafer 2 and the insulator 3, is typically in the range of 45~ + 20~, i.e. between 25 and 6~~.
The emitter and base regions 4, 5 are located at an upper edge line of the wafer structure where the structure has a tilted ~surface 7, the configuration being obt~ine~ by cutting away a corner region of the generally rectangular cross-section. The emitter and base regions are located at this tilted surface 7, the emitter region 5 being a thin layer located directly inside the tilted surface and the base region 4 being a thin layer ~located directly inside the emitter region, the emitter and base regions thus ext~n~i ng in parallel to the tilted surface 7. The tilted surface 7 is only a surface of the silicon layer 2 and does not extend into the insulator layer 3. The collector con-tacting region 6 is located at the upper edge line of the ~structure which is opposite the edge where the tilted surface 7 is located.
A method of producing the semiconductor device 1 shown comprises etching anisotropically an SOI film, having a (100) silicon crystal orientation of the plane along its surface. The etching ~is made with a solution of KOH in order to produce the tilted surface 7 achieving that this surface will always be located along a ~111) crystal plane of the silicon wafer 2. The etching i8 made only at one of the lateral edges of the SOI film, re-~uiring that a suitable mask is applied before the etching step.
Thereupon a base region 5 and an emitter region 4 are doped so that they will ~e parallel to the tilted surface 7 and thus to a s(lll) crystal plane in the silicon wafer 2, which is supposed to already include a collector contacting region 6 made in some earlier processing step. The angle of tilt of the parallel base-emitter and collector-base junctions will thus correspond to the angle of tilt of the (111) crystal plane of the silicon wafer 2 10 in relation to its upper surface. Emitter-, base- and collector con~acts, not shown, are finally produced in some conventional way such as by ~king heavily doped contacting regions at suitable places and by producing metallizations on top of these regions or by making polysilicon structures at suitable con-15 tacting places.
The method can also be used for producing transistors on a wa~ersuch as for an integrated circuit having several different com-ponents on the same chip. Then the anisotropic etching is made to produce V-grooves having sides walls located along (111) ~planes of the silicon monocrystalline material. In the V-grooves, from the sides thereof suitable dopants are dif~used into the silicon material to produce the base and emitter regions. This method will then differ from conventional methods of producing transistors mainly in the step of producing the V-~grooves ~efore the diffusion steps or in producing V-grooves having tilted sidewalls instead of rectangular cross-section grooves having sidewalls perpendicular to the surface of the wafer.
The diagram of Fig. 2 shows a one-dimensional simulation of the ~doping profiles as taken perpendicularly to the tilted surface 7 of the emitter 4 for a typical embodiment of a transistor as described with reference to Fig. 1. The various lines drawn illustrate the concentrations of arsenic, boron and phosphorous as functions of the distance from the surface 7. Also, the net ~dopant concentration is shown. In the diagram of Fig. 3 the net donor concentration and the net acceptor concentrations are illustrated as functions of the same distance. Also here, the net dopant concentration is shown.
. . , _ CA 02243998 l998-07-22 -In Fig. 4 measured values of the actual concentrations of dopant atoms are shown for a npn-transistor doped with arsenic and boron, also as functions of the same perpendicular distance from v the tilted surface of the emitter region.
sIt is to be understood, however, that other methods in addition to etching as described above may be used to produce tilted parallel base-emitter and collector-base junctions. Also, another crystal surface than the (lll) crystal plane of the silicon wafer may be exposed for producing the tilted surface to t~be doped to achieve a base region and an emitter region parallel to the exposed crystal surface.
The ~ n~ions of the SOI film are chosen in such a way that the electric field perpendicular to the emitter-base junction will be reduced. This will increase the breakdown voltage of the 5 semiconductor device. Due to its geometry, the charge is injected into the collector space charge region in the direction of the electric field. Since no potential lock-up is present, and thus, the lateral field is never zero, the transport will be by drift and not by diffusion 8S in the case of a semiconductor ~device having a fully depleted collector. This feature will make the semiconductor device as described above faster having a per-formance comparable to a lateral semiconductor device.
Moreover, it is to be understood that the invention is not re-stricted to the use of silicon as a semiconducting material in ~the semiconductor-on-insulator device. Instead of silicon, e.g.
GaAs or SiC may equally well be used.
Claims (6)
1. A bipolar semiconductor-on-insulator device (1) comprising an emitter region (4), a base region (5), and a collector region in a semiconductor wafer (2) on an insulator (3), characterized in that the base-emitter and collector-base junctions are tilted in relation to the interface between the semiconductor wafer (2) and the insulator (3).
2. A device according to claim 1, characterized in that the angle of tilt of the base-emitter and collector-base junctions 3 is in the range of 45° ~ 20°.
3. A device according to claim 1 or 2, in the case where the semiconductor wafer is made of monocrystalline silicon (Si), characterized in that the angle of tilt of the base-emitter and collector-base junctions corresponds to the (111) crystal plane of the silicon wafer (2).
4. A method of producing a bipolar semiconductor-on-insulator device from a semiconductor wafer (2) on an insulator (3), characterized by doping the wafer to produce a base region (5) and an emitter region (4) which are tilted in relation to the interface between the semiconductor wafer (2) and the insulator (3).
5. A method according to claim 4, characterized in that the base-emitter and collector-base junctions are tilted in an angle in the range of 45° ~ 20°.
6. A method according to claim 4 or 5, in the case where the semiconductor wafer is made of monocrystalline silicon (Si), characterized by anisotropically etching the silicon wafer (2) to expose a (111) crystal plane at one of lateral edges thereof before doping the base region (5) and the emitter region (4) parallel to the exposed (111) crystal plane of the silicon wafer (2).
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| SE9600898A SE506510C2 (en) | 1996-03-07 | 1996-03-07 | Semiconductors including inclined base emitter and collector base transitions and method for producing such |
| SE9600898-2 | 1996-03-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2243998A1 true CA2243998A1 (en) | 1997-09-12 |
Family
ID=20401711
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002243998A Abandoned CA2243998A1 (en) | 1996-03-07 | 1997-03-05 | Bipolar soi device having a tilted pn-junction, and a method for producing such a device |
Country Status (8)
| Country | Link |
|---|---|
| EP (1) | EP0963610A1 (en) |
| JP (1) | JP2000506311A (en) |
| KR (1) | KR19990087554A (en) |
| CN (1) | CN1212787A (en) |
| AU (1) | AU2049397A (en) |
| CA (1) | CA2243998A1 (en) |
| SE (1) | SE506510C2 (en) |
| WO (1) | WO1997033319A1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100197001B1 (en) * | 1996-05-02 | 1999-07-01 | 구본준 | Bipolar device and manufacturing method thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE1589453A1 (en) * | 1966-06-28 | 1970-04-02 | Asea Ab | Semiconductor device |
| DE4001350C2 (en) * | 1989-01-18 | 1993-10-07 | Nissan Motor | Semiconductor device |
-
1996
- 1996-03-07 SE SE9600898A patent/SE506510C2/en not_active IP Right Cessation
-
1997
- 1997-03-05 EP EP97908624A patent/EP0963610A1/en not_active Withdrawn
- 1997-03-05 WO PCT/SE1997/000377 patent/WO1997033319A1/en not_active Application Discontinuation
- 1997-03-05 KR KR1019980706992A patent/KR19990087554A/en active IP Right Grant
- 1997-03-05 CN CN97192844A patent/CN1212787A/en active Pending
- 1997-03-05 JP JP9531710A patent/JP2000506311A/en active Pending
- 1997-03-05 AU AU20493/97A patent/AU2049397A/en not_active Abandoned
- 1997-03-05 CA CA002243998A patent/CA2243998A1/en not_active Abandoned
Also Published As
| Publication number | Publication date |
|---|---|
| JP2000506311A (en) | 2000-05-23 |
| SE9600898L (en) | 1997-09-08 |
| SE9600898D0 (en) | 1996-03-07 |
| WO1997033319A1 (en) | 1997-09-12 |
| EP0963610A1 (en) | 1999-12-15 |
| KR19990087554A (en) | 1999-12-27 |
| CN1212787A (en) | 1999-03-31 |
| AU2049397A (en) | 1997-09-22 |
| SE506510C2 (en) | 1997-12-22 |
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