RU2792973C1 - Trigger logic element and-not/or-not - Google Patents

Abstract

FIELD: digital circuitry; automation; industrial electronics.

SUBSTANCE: AND/OR trigger logic element contains seven transistors, six resistors and constant voltage sources, it also has a two-emitter npn first additional transistor, pnp second additional transistor, and an additional resistor. The collector of the first additional transistor is connected to the base of the first transistor, the outputs of the two emitters of the first additional transistor form two inputs for the AND-NOT logic element, an additional resistor is connected between the base of the first additional transistor and the output of the first and third resistors, the emitter of the second additional transistor is connected to the common output of the first resistor and collectors of the first, second and third transistors, the base of the second additional transistor is connected to the third resistor, the collector of the second additional transistor is connected to the fifth transistor and to the fifth resistor, the free terminal of the fifth resistor is connected to the fourth resistor and their output forms the output of the logic element.

EFFECT: increasing the load capacity of the trigger logic element AND-NOT/OR-NOT.

1 cl, 3 dwg

Description

The invention relates to digital circuitry, automation and industrial electronics. In particular, it can be used in computer technology blocks built on logical elements.

Known logical element OR/OR-NOT [1 Goldenberg L.M. impulse devices. - M.: Radio and communication, 1981, p. 51, fig. 2.26, b], containing six transistors, one diode, five resistors and a DC supply voltage source.

Its disadvantage is that it has a low load capacity. The electric current of only one transistor forms the electric current of the external load. If it were possible to increase the number of transistors that form the load current, then this would lead to an increase in the maximum electric current of the external load of the logic element and, as a result, to an increase in the load capacity. The circuit of the above element has two inputs, each of which is a two-input (contains two outputs, which form two inputs relative to the "ground").

The closest in technical essence and the achieved result is the logical element OR/OR-NOT chosen as a prototype [Manaev EI, Fundamentals of radio electronics. - M .: Radio and communication, 1985, p. 342, fig. 14.23) containing six transistors, five resistors and two constant voltage sources.

Its disadvantage lies in the low load capacity. The electric current of only one transistor generates an external load current. If it were possible to increase the number of transistors that form the electric current of the external load, then this would lead to an increase in the maximum strength of the electric load current of the logic element and, as a result, to an increase in the load capacity. The given logical element refers to ESL elements (ESL - emitter-coupled logic).

The problem to be solved by the invention is to increase the load capacity of the trigger logic element AND-NOT/OR-NOT.

This is achieved by the fact that in the trigger logic element AND-NOT/OR-NOT, containing a supply DC voltage source, the negative output of which is connected to a common bus and grounded, the first, second and third npn transistors connected in parallel, the outputs of the bases of the second and third transistors form relative to the "ground" two inputs for the OR-NOT logic element, the first resistor connected between the positive output of the DC supply voltage source and the common output of the collectors of the first, second and third transistors, the second resistor connected between the "ground" and the common output of the emitters of the same three transistors (first, second and third), the third resistor connected in series and the fourth also an npn transistor, the free terminal of the third resistor is connected to the common terminal of the first resistor and the positive terminal of the DC supply voltage source, the emitter of the fourth transistor is connected to the common terminal of the second resistor, the emitters of the first, of the second and third transistors, the positive output of the reference voltage source is connected to the base of the fourth transistor, the negative output of this source is grounded, the fifth npn transistor and the fourth resistor are connected in series with each other, connected to the emitter of the fifth transistor, there is also a fifth resistor, a two-emitter npn first additional transistor is introduced , pnp the second additional transistor, an additional resistor and the inclusion of elements has been changed, the collector of the first additional transistor is connected to the base of the first transistor, the two outputs of the two emitters of the first additional transistor form, relative to the "ground", two inputs for the NAND logic element, between the base of the first additional transistor and the common output of the first, third resistors, the positive output of the DC supply voltage source, an additional resistor is turned on, the emitter of the second additional transistor is connected to the common output of the first resistor and the collectors of the first, second and third transistors, the base of the second additional transistor is connected to the common output of the third resistor, the collectors of the fourth and of the fifth transistor, the collector of the second additional transistor is connected both to the base of the fifth transistor and to one of the two terminals of the fifth resistor, the free terminal of this fifth resistor is connected to the free terminal of the fourth resistor and their common terminal forms the output of the logic element relative to the ground.

The essence of the invention is illustrated by the trigger logic element AND-NOT/OR-NOT (Fig. 1) and the truth table for AND-NOT (Fig. 2) and the truth table for OR-NOT (Fig. 3).

In the trigger logic element AND-NOT/OR-NOT, the common bus (negative terminal) of the source 1 of the DC supply voltage is grounded. One of the terminals of the resistor 2 is connected to the output (positive terminal) of the supply source. The other terminal of this resistor is connected to the base of the two-emitter npn transistor 3. The two outputs of the emitters of this transistor form two inputs x ₁ and x ₂ of the logic element relative to the “ground” for AND-NOT . In parallel, npn transistors 4 and 5 are connected to each other. The base of transistor 4 is connected to the collector of transistor 3. The base of transistor 5 forms one (the first X ₁ ) of the two inputs for the NOR logic element relative to the "ground". Resistor 6 is connected between the common terminal of resistor 2 and the positive terminal of source 1 and the common terminal of the collectors of transistors 4 and 5. Resistor 7 is connected between the common terminal of the emitters of transistors 4 and 5 and ground. The collector of transistor 8 is connected to the common terminal of resistor 6 and the collectors of transistors 4 and 5. The base terminal of transistor 8 forms, relative to ground, the second input X ₂ for the NOR gate. The emitter of transistor 8 is connected to the common terminal of resistor 7 and the emitters of transistors 4 and 5. Resistor 9 and npn transistor 10 are connected in series with each other. The free terminal of resistor 9 is connected to the common terminal of resistors 2, 6 and the positive terminal of the DC supply voltage source 1. The emitter of the transistor 10 is connected to the common terminal of the resistor 7 and the emitters of the transistors 4, 5 and 8. The positive terminal of the reference DC voltage source 11 is connected to the base of the transistor 10, the negative terminal of this source is grounded.

логического элемента относительно «земли». Также последовательно включены p-n-р транзистор 14 и резистор 15. Эмиттер транзистора 14 подсоединен к общему выводу резистора 6, коллекторов транзисторов 4, 5 и 8. База транзистора 14 подключена к общему выводу резистора 9, коллекторов транзисторов 10 и 12. Общий вывод коллектора транзистора 14 и резистора 15 соединен с базой транзистора 12. Свободный вывод резистора 15 подключен к общему выводу резистора 13 и выхода

логического элемента. The npn transistor 12 and resistor 13 are connected in series. The collector of transistor 12 is connected to the common terminal of resistor 9 and the collector of transistor 10. The free terminal of resistor 13 is connected to the output terminal

logical element relative to the "ground". The pn-p transistor 14 and resistor 15 are also connected in series. The emitter of transistor 14 is connected to the common terminal of resistor 6, the collectors of transistors 4, 5 and 8. The base of transistor 14 is connected to the common terminal of resistor 9, the collectors of transistors 10 and 12. The common terminal of the transistor collector 14 and resistor 15 is connected to the base of transistor 12. The free terminal of resistor 15 is connected to the common terminal of resistor 13 and output

logical element.

In FIG. 1 part of the circuit on transistors 12 and 14 is a flip-flop on transistors of the opposite type of conductivity, and part of the circuit on transistors 4, 5, 8 and 10 is a current switch. Resistors 6 and 9 are both part of the current switch and the trigger on transistors of the opposite type of conductivity. In FIG. 1 also shows the resistor R _n in dashed lines, conditionally displaying the external load of the logic element.

Trigger logic element AND-NOT/OR-NOT works as follows. Digital electronics uses low and high level electrical input and output signals. Low level - the level of logical zero corresponds to voltage values in the region of zero (closer to zero), high level - the level of logical one corresponds to voltage values \u200b\u200bin the region of units of volts (often in the region of four volts).

The flip-flop on transistors 12, 14 of the opposite type of conductivity has two equilibrium states. In the first (conditionally) state, both transistors are closed and do not conduct electricity. Then, including resistors 9 and 15, zero voltage values. They are applied to the bases of transistors 12, 14 less than the threshold voltages of these transistors in absolute value and eventually keep these transistors in the closed state. In the second (conditionally) state, transistors 12 and 14 are open, their electric currents create voltages, including those on resistors 9 and 15, in absolute value and in values greater than the threshold voltages of the transistors and keep transistors 12, 14 in the open state. A trigger on transistors of the opposite type of conductivity, like other common triggers, passes from the first state to the second and vice versa when the control input voltages exceed the values of the voltages of the corresponding trigger thresholds.

- условное отображение выходного сигнала и N - номер строки по порядку. Обратимся к таблице истинности на фиг.2. На входы Х ₁ , и Х ₂ здесь подаются напряжения уровня логического нуля. Тогда состояние транзисторов 5 и 8 в худшем случае находятся в районе порогового напряжения, сила электрических токов коллекторов этих транзисторов мала, напряжение на резисторе 6 мало по абсолютной величине и по полярности минусом приложено к эмиттеру p-n-p транзистора 14 и не может перевести триггер на транзисторах 12 и 14 во второе состояние. В соответствии с первыми тремя строками таблицы истинности на фиг. 2 на один или оба входа х ₁ , х ₂ логического элемента поступает напряжение уровня логического нуля. Тогда один или оба базо-эмиттерных p-n перехода транзистора 3 открыты и на них весьма малое значение напряжения, как на диодах в проводящем электрический ток состоянии. Базо-коллекторный переход транзистора 3 тоже открыт, в итоге на базе транзистора 4 низкий уровень напряжения и его состояние в худшем случае в районе порогового напряжения. Сила коллекторного тока транзистора 4 мала и напряжение на резисторе 6 тоже имеет малое значение. Кроме того, это напряжение через резистор 9 плюсом приложено к базе p-n-р транзистора 14 и не может перевести его в открытое состояние. The work of the logical element AND-NOT/OR-NOT is reflected by the truth table for the AND-NOT operation at X ₁ =X ₂ =0 (Fig. 2) and the truth table for the OR-NOT operation at x ₁ =x ₂ =0, where x ₁ , x ₂ , x ₁ , x ₂ - conditional display of the input signals of the logic element,

- conditional display of the output signal and N - line number in order. Referring to the truth table in Fig.2. The inputs X ₁ and X ₂ are supplied with the voltage level of logic zero. Then the state of transistors 5 and 8 in the worst case is in the region of the threshold voltage, the strength of the electric currents of the collectors of these transistors is small, the voltage across the resistor 6 is small in absolute value and is applied minus in polarity to the emitter of the pnp transistor 14 and cannot transfer the trigger on transistors 12 and 14 to the second state. According to the first three rows of the truth table in FIG. 2, one or both inputs x ₁ , x ₂ of the logic element receives a logic zero level voltage. Then one or both base-emitter pn junctions of the transistor 3 are open and they have a very low voltage value, as on diodes in a conductive state. The base-collector junction of transistor 3 is also open, as a result, the base of transistor 4 has a low voltage level and its state, in the worst case, is in the region of the threshold voltage. The collector current strength of transistor 4 is small and the voltage across resistor 6 is also small. In addition, this voltage is positively applied through resistor 9 to the base of the pn-p transistor 14 and cannot switch it to the open state.

логического элемента напряжение уровня логической единицы.The voltage value of the source 11 of the reference constant voltage is chosen so as to provide the transistor 10 in the open state in the above state of the circuit, to provide the required value of the collector current of the transistor 10, respectively, the required voltage value across the resistor 9 in order to transfer the trigger on the transistors 12, 14 to the second state. The voltage across the resistor 9 minus is applied to the base of the pn-p transistor 14. The electric currents of the two trigger transistors 12, 14 in the second state form an external load electric current and provide output

logic element voltage level logic one.

логического элемента напряжение уровня логического нуля. Возросшая сила тока транзистора 4 повышает напряжение на резисторе 7, которое плюсом приложено к эмиттеру n-p-n транзистора 10. От этого транзистор 10 переходит в режим близкий к пороговому напряжению. Сила коллекторного тока этого транзистора мала и соответственно мало напряжение на резисторе 9 от этого тока. В базо-эмиттерной цепи p-n-p транзистора 14 напряжения на резисторах 6 и 9 включены встречно и существенно различны по абсолютной величине. Напряжение на резисторе 6 превалирует и обеспечивает приведенное выше состояние схемы с учетом малого значения напряжения на резисторе 9 от коллекторного тока транзистора 10.In accordance with the fourth row of the truth table (Fig. 2) for two inputsX ₁ AndX ₂ logic element is supplied with a logic-one level voltage. The base-emitter and base-collector junctions of transistor 3 are still open, but the base of transistor 4 now has a logic-one voltage. The collector current of the transistor 4 and the voltage across the resistor 6 increase significantly. Voltage across resistor 6 minus applied to emitterpnp transistor 14 and plus through resistor 9 to the base of this transistor. This voltage maintains the transistor 14 in the closed state. Then the flip-flop on transistors of the opposite type of conductivity in the first state. The current strength of transistors 12, 14 trigger in the first state provides on the external load and at the output

logic element voltage level logic zero. The increased current strength of transistor 4 increases the voltage across resistor 7, which is positively applied to the emitternpn transistor 10. From this, transistor 10 switches to a mode close to the threshold voltage. The strength of the collector current of this transistor is small and, accordingly, the voltage across the resistor 9 from this current is small. In the base-emitter circuitpnp transistor 14, the voltages across resistors 6 and 9 are connected in opposite directions and are significantly different in absolute value. The voltage on the resistor 6 prevails and provides the above state of the circuit, taking into account the low value of the voltage on the resistor 9 from the collector current of the transistor 10.

напряжение уровня логической единицы.Let us next turn to the truth table in Fig. 3. To the inputsX ₁ AndX ₂ logic zero level voltages are applied here. Then, as justified earlier, the voltage across resistor 6 from the effect of voltages of such signals is small, and in polarity, the plus is applied through resistor 9 to the basepnp transistor 14 and cannot transfer the flip-flop on transistors 12, 14 to the second state. According to the first row of the truth table in FIG. 3 for both inputsX ₁ AndX ₂ logical element receives the voltage level of logical zero. Accordingly, the strength of the collector currents of the transistors 5, 8 is small, the voltage from them across the resistor 6 is also small. In the current state of the circuit, the voltage value of the source 11 of the reference voltage of the source 11 provides the required collector current strength of the transistor 10 and the required voltage across the resistor 9, which is applied to the base with a minuspnp transistor 14 and ensures its open state, taking into account the low voltage across resistor 6. Then the trigger on transistors 12, 14 in the second state and the electric currents of its two transistors provide on the external load of the logic element and at its output

logic-one level voltage.

напряжение уровня логического нуля. Возросшее напряжение на резисторе 7 плюсом прикладывается к эмиттеру транзистора 10 и переводит его в состояние, близкое к пороговому напряжению. Тогда сила коллекторного тока транзистора 10 и, соответственно, напряжение на резисторе 9 весьма малы, не изменяют приведенные выше положения и состояние схемы.According to the 2nd, 3rd and 4th rows of the truth table in FIG. 3, the bases of one of the transistors 5, 8 or both are supplied with a logic-one level voltage and the strength of the electric currents of these transistors increases accordingly. The voltage across the resistors 6, 7 also increases from them. The increased voltage on the resistor 6 is positively applied through the resistor 9 to the base of the pnp transistor 14 and switches it to the closed state or to a state close to the threshold voltage. Then the trigger on transistors 12, 14 in the first state and currents close to zero of its two transistors are created on the external load of the logic element and at its output

logic zero level voltage. The increased voltage across the resistor 7 is positively applied to the emitter of the transistor 10 and puts it into a state close to the threshold voltage. Then the strength of the collector current of the transistor 10 and, accordingly, the voltage across the resistor 9 are very small, do not change the above positions and the state of the circuit.

When the input signals go from logical zero levels ( X ₁ =X ₂ =0 ) to input signals, where one signal or both correspond to the voltage of the logical one level, the total strength of the emitter currents of transistors 5, 8 in resistor 7 increases, and the strength of the emitter current of the transistor 10 in this resistor decreases. In the transition from the input signals, where the voltage of one of them or both correspond to the level of logical one, to both input signals of the level of logical zero ( X ₁ =X ₂ =0 ), the total strength of the emitter currents of the transistors 5, 8 through the resistor 7 decreases, and the strength of the emitter the current of the transistor 10 through this resistor increases.

The given prototype and the trigger logic element AND-NOT/OR-NOT refer to ESL elements (ESL-emitter-coupled logic). It is known that ESL elements have increased performance [for example, Goldenberg L.M. Pulse devices - M .: Radio and communication, 1981, p. 57, section "Dynamic characteristics" paragraphs 1, 2, ... 6].

логического элемента равна сумме силы токов двух транзисторов 12, 14, что повышает нагрузочную способность этого логического элемента. В прототипе электрический ток нагрузки формирует только один из транзисторов.Thus, in the trigger logic element AND-NOT / OR-NOT, the strength of the electric current of the external load and at the output

logic element is equal to the sum of the currents of the two transistors 12, 14, which increases the load capacity of this logic element. In the prototype, the load current forms only one of the transistors.

Claims (1)

Trigger logic element AND-NOT/OR-NOT, containing a DC supply voltage source, the negative terminal of which is connected to a common bus and grounded, the first, second and third n-p-n transistors connected in parallel, the base terminals of the second and third transistors form two inputs relative to the "ground" for a NOR logic element, the first resistor connected between the positive output of the DC supply voltage source and the common output of the collectors of the first, second and third transistors, the second resistor connected between the "ground" and the common output of the emitters of the same three transistors (the first, second and third), the third resistor and the fourth also an n-p-n transistor are connected in series, the free terminal of the third resistor is connected to the common terminal of the first resistor and the positive terminal of the DC supply voltage source, the emitter of the fourth transistor is connected to the common terminal of the second resistor, the emitters of the first, second and third transistors, to the base of the fourth transistor is connected to the positive output of the reference voltage source, the negative output of this source is grounded, the fifth n-p-n transistor and the fourth resistor are connected in series with each other, connected to the emitter of the fifth transistor, there is also a fifth resistor, characterized in that it contains a two-emitter n-p-n first additional transistor , p-n-p the second additional transistor, an additional resistor and the inclusion of elements has been changed, the collector of the first additional transistor is connected to the base of the first transistor, two outputs of the two emitters of the first additional transistor form, relative to the "ground", two inputs for the NAND logic element, between the base of the first additional transistor and the common output of the first, third resistors, the positive output of the DC supply voltage source, an additional resistor is turned on, the emitter of the second additional transistor is connected to the common output of the first resistor and the collectors of the first, second and third transistors, the base of the second additional transistor is connected to the common output of the third resistor, the collectors of the fourth and of the fifth transistor, the collector of the second additional transistor is connected both to the base of the fifth transistor and to one of the two terminals of the fifth resistor, the free terminal of this fifth resistor is connected to the free terminal of the fourth resistor and their common terminal forms the output of the logic element relative to the ground.

Images