RU2518641C1 - Parallel single signal counter - Google Patents

Abstract

FIELD: information technology.

SUBSTANCE: invention can be used in digital computer systems as a means of pre-processing discrete information. The device includes sixteen XOR elements and twelve AND elements.

EFFECT: reduced hardware costs and high speed of operation.

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Description

The invention relates to computer technology and can be used to build automation, functional units of control systems, etc.

Known parallel counters of single signals (see, for example, RF patent 2256211, CL G06F 7/38, 2005), which contain logic elements and form a binary code for the number of single signals of the input tuple (x ₁ , ..., x ₈ ), where x _q ∈ {0,1}.

The reason that impedes the achievement of the technical result indicated below when using known parallel counters of single signals includes high hardware costs and low speed, due to the fact that, in particular, the aforementioned analogue contains twenty-two AND elements, twenty-two EXCLUSIVE OR elements, and the maximum the propagation delay time of the signal in it is equal to 10τ _LE , where τ _LE is the delay time of the logic element.

The closest device of the same purpose to the claimed invention in terms of features is the parallel counter of single signals adopted for the prototype (RF patent 2260204, class G06F5 / 00, 2005), which contains logic elements and generates a binary code for the number of single signals of the input tuple ( x ₁ , ..., x ₈ ), where x _q ∈ {0,1}.

The reasons that impede the achievement of the technical result indicated below when using the prototype include high hardware costs and low speed, due to the fact that the prototype contains thirteen AND elements, seventeen EXCLUSIVE OR elements and the maximum signal propagation delay time in it is 9τ _LE , where τ _LE is the delay time of the logical element.

The technical result of the invention is to reduce hardware costs and increase speed while maintaining the functionality of the prototype.

и первый, второй входы j-го

элементов И подключены соответственно к выходам (i+2)-го, (i+4)-го элементов ИСКЛЮЧАЮЩЕЕ ИЛИ и выходам (j-4)-го, (j-2)-го элементов И, выходы i-го, j-го элементов ИСКЛЮЧАЮЩЕЕ ИЛИ и выходы i-го, j-го элементов И соединены соответственно с i-ым входом девятого, вторым входом (j+7)-го и первым входом (i+13)-го, (j-6)-м входом одиннадцатого элементов ИСКЛЮЧАЮЩЕЕ ИЛИ, выходы (i+13)-го, (i+9)-го, тринадцатого элементов ИСКЛЮЧАЮЩЕЕ ИЛИ и выход (i+8)-го элемента И подключены соответственно к i-му входу десятого, вторым входам (i+11)-го, шестнадцатого и первому входу (i+11)-го элементов ИСКЛЮЧАЮЩЕЕ ИЛИ, а выходы девятого, двенадцатого, шестнадцатого элементов ИСКЛЮЧАЮЩЕЕ ИЛИ и выход одиннадцатого элемента И являются соответственно первым, вторым, третьим и четвертым выходами параллельного счетчика единичных сигналов, первый, третий и второй, четвертый, шестой, восьмой входы которого соединены соответственно с первыми входами третьего, пятого и вторыми входами третьего, пятого, четвертого, шестого элементов И.The specified technical result in the implementation of the invention is achieved by the fact that in a parallel counter of single signals containing sixteen elements EXCLUSIVE OR and twelve elements AND, the first and second inputs of the rth (r∈ {1, ..., 7, 9, ..., 12}) EXCLUSIVE OR elements are connected respectively to the first and second inputs of the rth AND element, and the first inputs of the fourth, sixth and output of the twelfth elements AND are connected respectively to the fifth, seventh inputs of the parallel counter of unit signals and the first input of the sixteenth element EXCLUSIVE OR, the peculiarity is that the first and second inputs of the eighth element of the EXCLUSIVE OR are connected respectively to the first and second inputs of the eighth element of And, the first, second inputs of the i-th

and the first, second inputs of the j-th

AND elements are connected respectively to the outputs of the (i + 2) th, (i + 4) th elements EXCLUSIVE OR and the outputs of the (j-4) th, (j-2) th elements AND, outputs of the i-th, j -th elements EXCLUSIVE OR and the outputs of the i-th, j-th elements AND are connected respectively to the i-th input of the ninth, second input of the (j + 7) -th and first input of (i + 13) -th, (j-6) -th input of the eleventh element EXCLUSIVE OR, outputs of the (i + 13) th, (i + 9) th, thirteenth element of the EXCLUSIVE OR and the output of the (i + 8) th element AND are connected respectively to the i-th input of the tenth, second the inputs of the (i + 11) th, sixteenth and first input of the (i + 11) th IP elements BUT OR, and the outputs of the ninth, twelfth, sixteenth elements EXCLUSIVE OR and the output of the eleventh element And are respectively the first, second, third and fourth outputs of the parallel counter of single signals, the first, third and second, fourth, sixth, eighth inputs of which are connected respectively to the first the inputs of the third, fifth and second inputs of the third, fifth, fourth, sixth elements I.

The drawing shows a diagram of the proposed parallel counter of single signals.

соединены соответственно с первым и вторым входами элемента 2_r, первый, второй входы элемента 2i

и первый, второй входы элемента 2j

подключены соответственно к выходам элементов 1_i+2, 1_i+4 и 2_j-4, 2_j-2, выходы элементов 1_i, 1_j и 2_i, 2_j соединены соответственно с i-м входом элемента 1₉, вторым входом элемента 1_j+7 и первым входом элемента 1_i+13, (j-6)- м входом элемента 1₁₁, выходы элементов 1_i+13, 1_i+9, 1₁₃ и 2_i+8, 2₁₂ подключены соответственно к i-му входу элемента 1₁₀, вторым входам элементов 1_i+11, 1₁₆ и первым входам элементов 1_i+11, 1₁₆, а выходы элементов 1₉, l₁₂, 1₁₆ и 2₁₁ являются соответственно первым, вторым, третьим и четвертым выходами параллельного счетчика единичных сигналов, первый, третий, пятый, седьмой и второй, четвертый, шестой, восьмой входы которого соединены соответственно с первыми входами элементов 1₃, 1₅, 1₄, 1₆ и вторыми входами элементов 2₃, 2₅, 2₄, 2₆.The parallel counter of single signals contains the elements EXCLUSIVE OR 1 ₁ , ..., 1 ₁₆ and the elements AND 2 ₁ , ..., 2 ₁₂ , the first and second inputs of the element 1 _r

connected respectively to the first and second inputs of the element 2 _r , the first, second inputs of the element 2i

and the first, second inputs of element 2j

connected respectively to the outputs of the elements 1 _{i + 2} , 1 _{i + 4} and 2 _j-4 , 2 _j-2 , the outputs of the elements 1 _i , 1 _j and 2 _i , 2 _{j are} connected respectively to the i-th input of element 1 ₉ , the second the input of element 1 _{j + 7} and the first input of element 1 _{i + 13} , (j-6) - the m input of element 1 ₁₁ , the outputs of elements 1 _{i + 13} , 1 _{i + 9} , 1 ₁₃ and 2 _{i + 8} , 2 _{12 are} connected respectively, to the i-th input of element 1 ₁₀ , the second inputs of elements 1 _{i + 11} , 1 ₁₆ and the first inputs of elements 1 _{i + 11} , 1 ₁₆ , and the outputs of elements 1 ₉ , l ₁₂ , 1 ₁₆ and 2 ₁₁ are respectively the first, second, third and fourth outputs of a parallel counter of single signals, first, third the fifth, seventh and second, fourth, sixth, eighth inputs of which are connected respectively to the first inputs of the elements 1 ₃ , 1 ₅ , 1 ₄ , 1 ₆ and the second inputs of the elements 2 ₃ , 2 ₅ , 2 ₄ , 2 ₆ .

The work of the proposed parallel counter of single signals is as follows. At its first, ..., eighth inputs, signals x ₁ , ..., x ₈ ∈ {0,1} are to be processed, respectively. Then the signals Z ₁ , ..., Z ₄ (see drawing) will be determined by the expressions

Z ₁ = x ₁ ⊕x ₂ ⊕x ₃ ⊕x ₄ ⊕x ₅ ⊕x ₆ ⊕x ₇ ⊕x ₈ ,

Z ₂ = (x ₁ ⊕x ₂ ⊕x ₃ ⊕x ₄ ) (x ₅ ⊕x ₆ ⊕x ₇ ⊕x ₈ ) ⊕x ₁ x ₂ ⊕x ₁ x ₃ ⊕x ₁ x ₄ ⊕x ₂ x ₃ ⊕ x ₂ x ₄ ⊕ x ₃ x ₄ ⊕ x ₅ x ₆ ⊕ x ₅ x ₇ ⊕ x ₅ x ₈ ⊕ x ₆ x ₇ ⊕ x ₆ x ₈ ⊕ x ₇ x ₈ ,

Z ₃ = (x ₁ ⊕x ₂ ⊕x ₃ ⊕x ₄ ) (x ₅ ⊕x ₆ ⊕x ₇ ⊕x ₈ ) (x ₁ x ₂ ⊕x ₁ x ₃ ⊕x ₁ x ₄ ⊕x ₂ x ₃ ⊕ x ₂ x ₄ ⊕x ₃ x ₄ ⊕x ₅ x ₆ ⊕x ₅ x ₇ ⊕x ₅ x ₈ ⊕x ₆ x ₇ ⊕x ₆ x ₈ ⊕x ₇ x ₈ ) ⊕ (x ₁ x ₂ ⊕x ₁ x ₃ ⊕x ₁ x ₄ ⊕x ₂ x ₃ ⊕x ₂ x ₄ ⊕x ₃ x ₄ ) (x ₅ x ₆ ⊕x ₅ x ₇ ⊕x ₅ x ₈ ⊕x ₆ x⊕x ₆ x ₈ ⊕x ₇ x ₈ )

Z ₄ = x ₁ x ₂ x ₃ x ₄ x ₅ x ₆ x ₇ x ₈ ,

where the symbols ⊕ and ^. the operations EXCLUSIVE OR and I. are denoted, respectively. Expanding the brackets and simplifying the penultimate equality using the relation y⊕y = 0 (y∈ {0,1}), we obtain

; m=2^g-1; x_k1, …, x_km∈{x₁, …, x₈}, 1≤k1<…<km≤8;

есть количество неповторяющихся конъюнкций x_k1…x_km, определяемое как число сочетаний из 8 по m. Таким образом, на выходах предлагаемого счетчика имеем Z₁=β₀, Z₂=β₁, Z₃=β₂, Z₄=β₃, где β₃β₂β₁β₀ есть двоичный код числа единичных сигналов в кортеже (x₁, …, x₈). При этом максимальное время задержки распространения сигнала в предлагаемом счетчике равно 6τ_ЛЭ (τ_ЛЭ - время задержки логического элемента).Where

; m is 2 ^g-1 ; x _k1 , ..., x _km ∈ {x ₁ , ..., x ₈ }, 1≤k1 <... <km≤8;

there is the number of non-repeating conjunctions x _k1 ... x _km , defined as the number of combinations of 8 over m. Thus, at the outputs of the proposed counter we have Z ₁ = β ₀ , Z ₂ = β ₁ , Z ₃ = β ₂ , Z ₄ = β ₃ , where β ₃ β ₂ β ₁ β ₀ is the binary code of the number of unit signals in the tuple ( x ₁ , ..., x ₈ ). In this case, the maximum delay time of the signal propagation in the proposed counter is 6τ _LE (τ _LE is the delay time of the logic element).

The above information allows us to conclude that the proposed parallel counter of single signals has the functionality of the prototype, lower hardware costs and higher speed compared to it.

Claims (1)

A parallel counter of single signals containing sixteen EXCLUSIVE OR elements and twelve AND elements, the first and second inputs of the rth (r∈ {1, ..., 7, 9, ..., 12}) EXCLUSIVE OR elements being connected to the first and second inputs, respectively of the rth element AND, and the first inputs of the fourth, sixth and the output of the twelfth elements AND are connected respectively to the fifth, seventh inputs of the parallel counter of unit signals and the first input of the sixteenth element EXCLUSIVE OR, characterized in that the first and second inputs of the eighth element AND Plug or respectively connected to first and second inputs of the eighth AND gate, the first inputs of the second i-th $$\left(i=\overline{\mathrm{1,2}}\right)$$

and the first, second inputs of the j-th $$\left(j=\overline{7.8}\right)$$

AND elements are connected respectively to the outputs of the (i + 2) th, (i + 4) th elements EXCLUSIVE OR and the outputs of the (j-4) th, (j-2) th elements AND, outputs of the i-th, j -th elements EXCLUSIVE OR and outputs of the i-th, j-th elements AND are connected respectively to the i-th input of the ninth, the second input of the (j + 7) -th and the first input of (i + 13) -th, (j-6) - by the mth input of the eleventh element EXCLUSIVE OR, the outputs of the (i + 13) th, (i + 9) th, thirteenth elements of the EXCLUSIVE OR and the output of the (i + 8) th element AND are connected respectively to the i-th input of the tenth, second the inputs of the (i + 11) th, sixteenth and first input of the (i + 11) th elements of the ISK BUT OR, and the outputs of the ninth, twelfth, sixteenth elements EXCLUSIVE OR and the output of the eleventh element And are respectively the first, second, third and fourth outputs of the parallel counter of single signals, the first, third and second, fourth, sixth, eighth inputs of which are connected respectively to the first the inputs of the third, fifth and second inputs of the third, fifth, fourth, sixth elements I.

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