RU2761103C1 - Parallel unit counter - Google Patents

Abstract

FIELD: computing technology.

SUBSTANCE: parallel unit counter comprises four EXCLUSIVE OR elements (1₁, …, 1₄) and four majority elements (2₁, …, 2₄). Due to said elements and a new connection configuration thereof with a depth of 3, the amount of units in a seven-digit binary number set by seven input binary signals is determined.

EFFECT: expanded operational capabilities of the parallel unit counter with maintained prototype configuration depth.

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Description

The invention relates to computer technology and can be used in the construction of automation tools, functional units of control systems, etc.

Known parallel unit counters (see, for example, Fig. 9.6a on page 215 in the book Tokheim R. Fundamentals of digital electronics. M .: Mir, 1988), which determine the number of units in a three-digit binary number, specified by three input binary signals.

The reason that prevents the achievement of the technical result indicated below when using the known parallel unit counters is limited functionality due to the fact that the processing of a seven-bit binary number specified by seven input binary signals is not allowed.

The closest device for the same purpose to the claimed invention in terms of a set of features is the parallel counter of units adopted as a prototype (Fig. 9.6b on page 215 in the book of Tokheim R. Fundamentals of digital electronics. M .: Mir, 1988), which contains logical elements and determines the number of ones in a three-bit binary number, given by three input binary signals. In this case, the depth of the prototype circuit is formed by three logical elements.

The reason that prevents the achievement of the technical result indicated below when using the prototype includes limited functionality due to the fact that processing of a seven-bit binary number specified by seven input binary signals is not allowed.

The technical result of the invention is to expand the functionality by ensuring the determination of the number of units in a seven-bit binary number, specified by seven input binary signals, while maintaining the depth of the prototype circuit.

элемента ИСКЛЮЧАЮЩЕЕ ИЛИ соединены соответственно с первым, вторым, третьим входами i-го мажоритарного элемента, первый, третий входы третьего и первый, второй, третий входы четвертого элементов ИСКЛЮЧАЮЩЕЕ ИЛИ соединены соответственно с выходами первого, второго элементов ИСКЛЮЧАЮЩЕЕ ИЛИ и выходами первого, третьего, второго мажоритарных элементов, а первый, второй, третий входы j-го

второй вход третьего элементов ИСКЛЮЧАЮЩЕЕ ИЛИ и выход четвертого мажоритарного элемента соединены соответственно с (3 × j-2)-ым, (3 × j-1)-ым, (3 × j)-ым, седьмым входами и третьим выходом параллельного счетчика единиц, первый и второй выходы которого образованы соответственно выходами третьего и четвертого элементов ИСКЛЮЧАЮЩЕЕ ИЛИ.The specified technical result in the implementation of the invention is achieved by the fact that in a parallel unit counter containing two EXCLUSIVE OR elements, the peculiarity lies in the fact that two EXCLUSIVE OR elements and four majority elements are additionally introduced into it, and the first, second, third inputs of the i-th

of the EXCLUSIVE OR element are connected respectively to the first, second, third inputs of the i-th majority element, the first, third inputs of the third and first, second, third inputs of the fourth EXCLUSIVE OR elements are connected respectively to the outputs of the first, second EXCLUSIVE OR elements and the outputs of the first, third, of the second majority element, and the first, second, third inputs of the j-th

the second input of the third EXCLUSIVE OR elements and the output of the fourth majority element are connected, respectively, to the (3 × j-2) th, (3 × j-1) th, (3 × j) th, seventh inputs and the third output of the parallel unit counter , the first and second outputs of which are formed, respectively, by the outputs of the third and fourth EXCLUSIVE OR elements.

The drawing shows a diagram of the proposed parallel counter of units.

соединены соответственно с первым, вторым, третьим входами элемента 2_i, первый, третий входы элемента 1₃ и первый, второй, третий входы элемента 1₄ соединены соответственно с выходами элементов 1₁, 1₂ и 2₁, 2₃, 2₂, а первый, второй, третий входы элемента

второй вход элемента 1₃ и выходы элементов 1₃, 1₄, 2₄ соединены соответственно с (3 × j-2)-ым, (3 × j-1)-ым, (3 × j)-ым, седьмым входами и первым, вторым, третьим выходами параллельного счетчика единиц.Parallel counter of ones contains elements EXCLUSIVE OR 1 ₁ , ..., 1 ₄ and majority elements 2 ₁ , ..., 2 ₄ , and the first, second, third inputs of the element

are connected respectively to the first, second, third inputs of element 2 _i , the first, third inputs of element 1 ₃ and the first, second, third inputs of element 1 ₄ are respectively connected to the outputs of elements 1 ₁ , 1 ₂ and 2 ₁ , 2 ₃ , 2 ₂ , and the first, second, third inputs of the element

the second input of the element 1 ₃ and the outputs of the elements 1 ₃ , 1 ₄ , 2 _{4 are} connected, respectively, with the (3 × j-2) th, (3 × j-1) th, (3 × j) th, seventh inputs and the first, second, third outputs of the parallel counter of units.

, полученные с учетом работы элементов 1_j, 2_j для всех возможных наборов значений входных сигналов x_3×j-2, x_3×j-1, x_3×j. В табл. 2 указаны значения выходных сигналов z₁, z₂, z₃ предлагаемого счетчика, полученные с учетом работы соответствующих элементов для всех возможных наборов значений сигналов у₁, у₂, у_з, у₄, х₇.The proposed parallel counter of units is carried out as follows. On its first, ..., seventh inputs, respectively, binary signals x ₁ , ..., x ₇ ∈ {0, l} are supplied, which specify the seven-bit binary number to be processed. In the table below. 1 shows the signal values

obtained taking into account the operation of elements 1 _j , 2 _j for all possible sets of values of the input signals x _{3 × j-2} , x _{3 × j-1} , x _{3 × j} . Table 2 shows the values of the output signals z ₁ , z ₂ , z _{3 of the} proposed counter, obtained taking into account the operation of the corresponding elements for all possible sets of signal values y ₁ , y ₂ , y _z , y ₄ , x ₇ .

According to the table. 1, tab. 2 we have z ₁ = β ₀ , z ₂ = β ₁ , z ₃ = β ₂ , where β ₂ β ₁ β ₀ is the binary code of the number of ones in a seven-bit binary number, specified by binary signals x ₁ , ..., x ₇ .

The above information allows us to conclude that the proposed parallel counter of units has wider functional capabilities in comparison with the prototype, since it determines the number of units in a seven-bit binary number specified by seven input binary signals. In this case, the depth of the circuit of the proposed parallel counter of units is formed by three logical elements.

Claims (1)

Parallel counter of ones, containing two EXCLUSIVE OR elements, characterized in that two EXCLUSIVE OR elements and four majority elements are additionally introduced into it, and the first, second, third inputs of the i-th

of the EXCLUSIVE OR element are connected respectively to the first, second, third inputs of the i-th majority element, the first, third inputs of the third and first, second, third inputs of the fourth EXCLUSIVE OR elements are connected respectively to the outputs of the first, second EXCLUSIVE OR elements and the outputs of the first, third, of the second majority element, and the first, second, third inputs of the j-th

the second input of the third EXCLUSIVE OR elements and the output of the fourth majority element are connected, respectively, to the (3 × j-2) th, (3 × j-1) th, (3 × j) th, seventh inputs and the third output of the parallel unit counter , the first and second outputs of which are formed, respectively, by the outputs of the third and fourth EXCLUSIVE OR elements.

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