RU2120137C1 - Interpolator - Google Patents

Abstract

FIELD: computer engineering. SUBSTANCE: device has input information bus, start bus, clock bus, counter, converter to complementary code, six multipliers, memory unit, commutator, three delay gates, subtraction unit, four registers, two setting buses, adder and control unit, which has RS flip-flop, two AND gates, counter and two comparison units. EFFECT: increased precision of interpolation for functions with continuous fourth and higher derivatives. 2 cl, 1 dwg

Description

 The invention relates to computing, in particular to devices for implementing functions, and can be used to reproduce nonlinear dependencies of one variable.

 Known devices (USSR AS N 1405074, G 06 F 15/353, 10/27/1986, USSR AS N 1686461, G 06 F 15/353, 02/13/1989) allow reproducing a wide class of functional dependencies, but have low accuracy.

 Closest to the claimed device in its technical essence is an interpolator (AS USSR N 1405074, G 06 F 15/353, 10/27/1986), selected as a prototype device.

 The prototype device contains an accumulating adder, a multiplier, the first and second memory blocks, a switch, an additional code converter, a counter and a register, the output of which is connected to the first information input of the switch, the output of the first bit of the register connected to the control input of the switch, the second information input of which connected to the output of the converter in an additional code, the input of which is connected to the output of the register, the information input of which is the input of the least significant bits of the interpolator argument, in the course of the upper bits of which is connected to the input of the initial value of the counter, the output of which is connected to the address input of the first memory block, the output of the multiplier is connected to the information input of the accumulating adder, the output of which is the output of the interpolator, the inputs of the counter and register data and the reset input of the accumulating adder are connected to the input of the initial installation of the interpolator, the counting input of the counter and the synchronization input of the accumulating adder are connected to the clock input of the interpolator The first memory block is connected to the input of the first multiplier factor, the input of the second factor of which is connected to the output of the first memory block, and the output of the switch is connected to the address input of the second memory block.

где

максимум третьей производной функции f(x);
h - расстояние между отсчетами функции f(x).The known technical solution has insufficient interpolation accuracy, which is characterized by an interpolation error equal to

Where

the maximum of the third derivative of the function f (x);
h is the distance between the samples of the function f (x).

Moreover, this accuracy is ensured for functions having a continuous third derivative (f (x) ∈C ³ ) or higher. When interpolating functions having a continuous fourth derivative (f (x) ∈C ⁴ ) and higher, information about the smoothness of functions is not fully taken into account, as a result of which the prototype does not provide higher accuracy.

The aim of the invention is to develop a device that provides higher accuracy of interpolation of functions having a continuous fourth derivative (f (x) ∈C ⁴ ) and higher.

 This goal is achieved by the fact that in a known interpolator containing a series-connected first multiplier, an adder and a first register, the information outputs of which are the output bus of the interpolator, a memory unit and a first counter, the information inputs of which are the input information bus of the interpolator, and the information outputs are connected to the address the inputs of the memory unit, the converter to additional code, the switch, the second register and the control unit, the first input of which is the start input of the interp the second input is connected to the input of the zeroing of the first register and the input of zeroing the first counter, and the second output is connected to the input of the control of the first register, the second, third, fourth, fifth and sixth multipliers, the third and fourth registers are additionally introduced , first, second and third delay elements and a subtraction block. The group of inputs of the last to be reduced through the second delay element is connected to the outputs of the fourth multiplier, the first and second groups of inputs of which are bitwise combined and connected to the outputs of the converter in an additional code, the group of inputs of the subtracted subtraction block is connected to the outputs of the third multiplier, the first group of inputs of which is connected to the outputs of the second a multiplier, the first and second groups of inputs of which are bitwise combined and connected to the inputs of the converter in an additional code and with the input information bus interpolator. The outputs of the subtraction unit are connected to the first group of inputs of the fifth multiplier. The second group of inputs of the fifth multiplier through the third register is connected to the second group of outputs of the switch. The outputs of the fifth multiplier are connected to the second group of information inputs of the adder. The third group of information inputs of the adder is connected to the outputs of the sixth multiplier. The first group of inputs of the sixth multiplier through the third delay element is combined with the inputs of the second delay element. The second group of inputs of the sixth multiplier through the fourth register is combined with the third group of outputs of the switch. The group of information inputs of the switch is connected to the outputs of the memory block. The group of address inputs of the switch is connected to the third group of outputs of the control unit. The first installation bus of the control unit is the first installation bus of the interpolator and is connected to the second group of inputs of the third multiplier. The first group of inputs of the third multiplier through the delay element is combined with the first group of inputs of the first multiplier. The second group of inputs of the first multiplier through the second register is connected to the first group of outputs of the switch. The second group of inputs of the second multiplier is combined with its first group of inputs. The second group of inputs of the fourth multiplier is combined with its first group of inputs. The counting input of the first counter is combined with the control inputs of the second, third and fourth registers, and the fourth output of the control unit. The fifth output of the control unit is connected to the control inputs of the first, second and third delay elements, the control input of the subtraction unit and the control input of the adder. The second mounting bus of the control unit is the second mounting bus of the interpolator.

 The control unit contains the first and second comparison elements, the second counter, the first and second elements And and the RS-trigger, the S-input of the RS-trigger is combined with the zeroing input of the second counter, the first input of the control unit and the first output of the control unit. The R-input is connected to the output of the second comparison element and the second output of the control unit. The output of the RS-trigger is connected to the first input of the second element I. The second input of the second element And is connected to the second input of the control unit. The output of the second element And is the fifth output of the control unit and is connected to the first input of the first element And and the counting input of the second counter. The information outputs of the second counter are the third group of outputs of the control unit and are connected to the first group of inputs of the second comparison unit and the first group of inputs of the first comparison unit. The second group of inputs of the first comparison unit is the first installation bus of the control unit. The output of the first comparison unit is connected to the second input of the first element I. The output of the first element And is the fourth output of the control unit. The second installation bus of the control unit is connected to the second group of inputs of the second comparison unit.

и выше. Это достигается тем, что интерполяция осуществляется более точно исходя из априорной информации о степени гладкости функций.The listed new set of essential features of the claimed device provides a higher accuracy of interpolation of functions having a continuous fourth derivative

and higher. This is achieved by the fact that the interpolation is carried out more accurately based on a priori information about the degree of smoothness of the functions.

 The claimed device is illustrated by the drawings shown in FIG. 1, which shows a structural diagram of the claimed device.

 The interpolator shown in FIG. 1, consists of an input information bus 1, a start bus 2, a clock bus 3, a counter 4, a converter to additional code 5, multipliers 6, 7, 10, 15, 17, 19, a memory block 8, a switch 9, delay elements 11, 12, 14, subtraction unit 13, registers 16, 18, 20, 25, control unit 21, mounting buses 22 and 23, adder 24.

 The control unit 21, also shown in FIG. 1, consists of an RS-flip-flop 26, elements AND 27, 29, counter 28, comparison blocks 30 and 31.

 The multiplier 15, the adder 24 and the register 25 are connected in series. The information outputs of the register 25 are the output bus of the interpolator. The information inputs of the counter 4 are connected to the input information bus 1 of the interpolator. The information outputs of the counter 4 are connected to the address inputs of the memory unit 8. The first input of the control unit 21 is connected to the trigger bus 2 of the interpolator. The second input is with a clock bus 3 of the interpolator. The first output of the control unit 21 is connected to the input of zeroing the register 25 and the input of the zeroing of the counter 4. The second output of the control unit 21 is connected to the input of the control of the register 25. The group of inputs of the reduced block of subtraction 13 is connected through the delay element 11 to the outputs of the multiplier 7. The first and second groups of inputs the latter bitwise combined and connected to the outputs of the Converter in an additional code 5. The group of inputs of the subtracted subtraction block 13 is connected to the outputs of the multiplier 10. The first group of inputs of the multiplier 10 is connected to the outputs of a factor of 6, the first and second groups of inputs of which are bitwise combined and connected to the inputs of the converter in additional code 5 and the input information bus 1 of the interpolator. The outputs of the subtraction unit 13 are connected to the first group of inputs of the multiplier 17. The second group of inputs of the multiplier 17 is connected through the register 18 to the second group of outputs of the switch 9. The outputs of the multiplier 17 are connected to the second group of information inputs of the adder 24. The third group of information inputs of the adder 24 is connected to the outputs of the multiplier 19. The first group of inputs of the multiplier 19 through the delay element 14 is combined with the inputs of the delay element 11. The second group of inputs of the multiplier 19 through the register 20 is combined with the third group of outputs of the switch 9 The group of information inputs of the switch 9 is connected to the outputs of the memory unit 8. The group of address inputs of the switch 9 is connected to the third group of outputs of the control unit 21. The first installation bus of the control unit 21 is the first installation bus 22 of the interpolator and connected to the second group of inputs of the multiplier 10. The first group the inputs of the multiplier 10 through the delay element 12 is connected to the first group of inputs of the multiplier 15. The second group of inputs of the multiplier 15 through the register 16 is connected to the first group of outputs of the switch 9. The second group of inputs The ode of multiplier 6 is combined with its first group of inputs. The second group of inputs of the multiplier 7 is combined with its first group of inputs. The counting input of the counter 4 is combined with the control inputs of the registers 16, 18, 20 and with the fourth output of the control unit 21. The fifth output of the control unit 21 is connected to the control inputs of the delay elements 11, 12, 14, the control input of the subtraction unit 13 and the control input of the adder 24. The second mounting bus of the control unit 21 is the second mounting bus 23 of the interpolator.

 The control unit 21 contains an RS-flip-flop 26, elements And 27 and 29, a counter 28, comparison elements 30 and 31. The S-input of the RS-flip-flop 26 is combined with the zeroing input of the counter 28, the first input of the control unit 21 and the first output of the control unit 21. The R-input is connected to the output of the comparison element 31 and the second output of the control unit 21. The output of the RS flip-flop 26 is connected to the first input of the And 29 element. The second input of the And 29 element is connected to the second input of the control unit 21. The output of the And 29 element is the fifth output of the block control 21 and is connected to the first input of the element And 27 and the counting input ohm counter 28. The information outputs of the counter 28 are the third group of outputs of the control unit 21 and are connected to the first group of inputs of the comparison unit 31 and the first group of inputs of the comparison unit 31. The second group of inputs of the comparison unit 30 is the first installation bus of the control unit 21. The output of the comparison unit 30 connected to the second input of the first element And 27. The output of the first element And 27 is the fourth output of the control unit 21. The second installation bus of the control unit 21 is connected to the second group of inputs of the comparison unit 31.

The elements included in the structural diagram of the claimed device are known and described, for example, in the book of V.L. Awl. Popular digital circuits. Directory. -M. : Radio and communication, 1988. So, in the specified source describes the principles of construction and implementation examples:
counters 4, 28 on pp. 85-86 (can be implemented on the K155IE5 chip);
memory block 8 on p. 171-174 (can be implemented on the chip K155PR6);
elements I 27, 29 on p. 35 fig. 1.19a (can be implemented on the K155LI1 chip);
registers 16, 18, 20, 25 on p.104-105 (can be implemented on the chip K155IR13- p. 111 Fig. 1.78);
RS-trigger 26 on p.62-67 (can be implemented on the chip K155LE1 - p. 63 Fig. 1.42).

 The principle of operation of the multipliers 6, 7, 10, 15, 17, 19 is known and described in the book: M. A. Kartsev, V. A. Brick. Computing systems and synchronous arithmetic. -M .: Radio and communications, 1981, p.163 - 221. They can be implemented on the chips SN54284 and SN54285, p.305, Fig. 6.3.12 or on the ADSP1016 microcircuit (S. Kun. Matrix processors on VLSI: Transl. From English. –M .: Mir, 1991, p. 502, table 7.4).

 In the book of V.L. Awl. Popular digital circuits. Directory. 2nd ed., Rev., Chelyabinsk: Metallurgy, 1989 describes the principle of operation of delay elements 11, 12, 14 on pages 181 - 187 (can be implemented on K564AG1 microcircuits, page 285, Fig. 2.83a), and the pairing order K564 with TTL is described in the book: Digital Integrated Circuits: Reference Book / P.P. Maltsev, N.S. Dolidze et al. - M.: Radio and Communications, 1994, p. 101 - 103.

 The principle of operation of the comparison blocks 30, 31 is known and described in the book of Yu.V. Gavrilov, A.N. A bunch. Arithmetic devices of high-speed digital computers. -M .: Soviet Radio, 1970, p.234-257. Can be implemented on chips K561IP2 (V.N. Veniaminov, ON Lebedev, A.I. Miroshnichenko. Chips and their application. Reference manual. 3rd ed. Revised and enlarged. - M .: Radio and communications, 1989, p. 114, Fig. 4, 12 b).

 The operating principles of the adder 24 and the subtraction unit 13 are known and described in the book: D. Givone, R. Rosset. Microprocessors and microcomputers: Introductory course: Trans. from English -M.: Mir, 1983, p. 184-198. The full adder is described in the book of V.L. Awl. Popular digital circuits. Directory. 2nd ed., Rev., - Chelyabinsk: Metallurgy, 1989.S. 152, Fig. 1.112, p. 153, fig. 1.113. The subtraction block based on full adders is given in the book by D. Givone, R. Rosset. Microprocessors and microcomputers: Introductory course: Trans. from English -M.: Mir, 1983, p. 190, fig. 5.38. It can be implemented on the elements of EXCL. OR - K155LP5, AND - K155LI1, OR - from OR-NOT K155LE4 and NOT K155LN1.

 The principle of implementation of the converter into additional code 5 is known and described in the book of L.M. Goldenberg. Pulse and digital devices. M .: Communication, 1973, p. 462 - 468. Can be implemented on the K155LAZ chip.

 The implementation principle of the switch 9 is known and described in the book of V.L. Awl. Popular digital circuits. Directory. 2nd ed., Rev., - Chelyabinsk: Metallurgy, 1989, p. 220. It can be implemented on the chip K561KT3.

где
h - шаг между отсчетами функции f(x);
B - сплайн степени m-1.The implementation of the claimed device is explained as follows. From the articles: Zheludev V.A. Local spline approximation on a uniform grid // Journal of Computational Mathematics and Mathematical Physics, 1987, v. 27, No. 9, p. 1296 - 1310 and Zheludev V.A. Recovery of functions and their derivatives from grid data with an error using local splines // Journal of Computational Mathematics and Mathematical Physics, 1987, v. 27, No. 1, p. 22-34 it is known that the expression for calculating the spline derivative can be written

Where
h is the step between the samples of the function f (x);
B is a spline of degree m-1.

число сочетаний из m по i:

x = h(N + τ), τ∈[0,1].
При S = 0 выражение (2) упрощается. В этом случае для квадратичного сплайна (m-1 = 2):

Из статей: Желудев В.А. Локальная сплайн-аппроксимация на равномерной сетке// Журнал вычислительной математики и математической физики, 1987, т. 27, N 9, с. 1296 - 1310 и Желудев В.А. Восстановление функций и их производных по сеточным данным с погрешностью при помощи локальных сплайнов// Журнал вычислительной математики и математической физики, 1987, т. 27, N 1, с. 22-34 известно, что значение B-сплайна b $\genfrac{}{}{0ex}{}{\text{3}}{\text{h}}$ (x) отлично от нуля на участке (0, 3h) и на различных интервалах наблюдения определяется следующим образом

-3(τ•h)²]=h²[(τ+1)²-3τ²]/(2h³)=[(τ+1)²-3τ²]/(2h),

Из (3) имеем

Учтем симметрию B-сплайна относительно точки h•m/2 (упомянутые выше статьи). Тогда получим квадратичный сплайн минимального шаблона

где
g $\genfrac{}{}{0ex}{}{\text{3}}{\text{n}}$ определяется (4).

the number of combinations from m to i:

x = h (N + τ), τ∈ [0,1].
At S = 0, expression (2) is simplified. In this case, for a quadratic spline (m-1 = 2):

From the articles: Zheludev V.A. Local spline approximation on a uniform grid // Journal of Computational Mathematics and Mathematical Physics, 1987, v. 27, No. 9, p. 1296 - 1310 and Zheludev V.A. Recovery of functions and their derivatives from grid data with an error using local splines // Journal of Computational Mathematics and Mathematical Physics, 1987, v. 27, No. 1, p. 22-34 it is known that the value of the B-spline b $\genfrac{}{}{0ex}{}{\text{3}}{\text{h}}$ (x) is nonzero in (0, 3h) and at different observation intervals is defined as follows

-3 (τ • h) ² ] = h ² [(τ + 1) ² -3τ ² ] / (2h ³ ) = [(τ + 1) ² -3τ ² ] / (2h),

From (3) we have

We take into account the symmetry of the B-spline with respect to the point h • m / 2 (the articles mentioned above). Then we get the quadratic spline of the minimal template

Where
g $\genfrac{}{}{0ex}{}{\text{3}}{\text{n}}$ defined by (4).

Implementation of (5) in the form of a device allows one to calculate the functions f (x) εC ⁴ with an accuracy determined by an error less than or equal to (Zheludev V.A. Restoration of functions and their derivatives from grid data // Journal of Computational Mathematics and Mathematical Physics, 1987, t. 27, No. 1, p. 24).

что лучше не менее чем на 5% по сравнению с прототипом. Точность последнего определяется из выражения (1).

which is better by at least 5% compared with the prototype. The accuracy of the latter is determined from expression (1).

где
f(x_i-1), f(x_i), f(x_i+1) - значения функции в узловых точках.Let x _i be the number formed by K high order bits of the argument x, where 2≤ K≤m-1; m is the length of the binary code of x. The number x _i represents the nodal point number. Let Δx - be the number formed by mK by the least significant bits of the argument so that x = x _i + Δx • 2 ^-k , 0 ≤ Δx ≤ 1. Then, using interpolation formula (5) by quadratic splines of the minimal pattern, we have

Where
f (x _i-1 ), f (x _i ), f (x _{i + 1} ) are the values of the function at the nodal points.

 The operation of the interpolator based on expression (5) and FIG. 1 is carried out as follows.

Before starting work, a value of 0.5 • g is recorded in memory unit 8 $\genfrac{}{}{0ex}{}{\text{3}}{\text{n-1}}$ , 0.5 • g $\genfrac{}{}{0ex}{}{\text{3}}{\text{n}}$ , 0.5 • g $\genfrac{}{}{0ex}{}{\text{3}}{\text{n + 1}}$ with an address shift so that the jth value of the address code corresponds to a value of 0.5 • g $\genfrac{}{}{0ex}{}{\text{3}}{\text{j-2}}$ .
In the initial state, meander-type clock pulses are sent to bus 3, the number 3 code is present on the first installation bus 22, and the number 5 code is on the second installation bus 23. The value x variable code is sent to the interpolator information bus 1.

 When a positive polarity pulse is applied to bus 2, register 25 is reset, and the high-order code of variable x is written to counter 4. At the same time, counter 28 is reset, and the RS-flip-flop 26 is set to a single state, in which the logical level “1” is formed at its output. The latter is fed to the first input of the And 29 element, allowing the passage of clock pulses through it. In addition, the code of the number 0 from the output of the counter 28 goes to the first group of inputs of the comparison unit 30. The code of the number 3 from the first installation bus 22 is received to another group of its inputs. As a result of the comparison operation, a signal with a unit level is generated at the output of unit 30. It should be noted that the temporary position of the leading edges of the clock pulses will further correspond to the new clock cycles of the device.

At the first clock cycle of the device, the clock pulse from the output of the And 29 element is supplied to the counting input of the counter 4 through the And 27 element, opened by the unit level supplied to its input from the output of the comparison unit 30. The contents of the counter 4 are increased by one, taking the value x _{i + 1} . The latter enters the address inputs of memory block 8, determining the number of the cell whose contents are 0.5 • g $\genfrac{}{}{0ex}{}{\text{3}}{\text{n-1}}$ fed to the input of the switch 9. Due to the fact that the control inputs of the switch 9 receives the code number 1 from the outputs of the counter 28, the value of 0.5 $\genfrac{}{}{0ex}{}{\text{3}}{\text{n-1}}$ written to register 16.

In the next two clock cycles, values of 0.5 • g, respectively, are recorded in registers 18 and 19 $\genfrac{}{}{0ex}{}{\text{3}}{\text{n}}$ and 0.5 • g $\genfrac{}{}{0ex}{}{\text{3}}{\text{n + 1}}$ . At the same time, at the end of the third clock cycle of the device, the contents of the counter 28 coincides with the number code supplied to the installation bus 22. As a result, a zero level is formed at the output of the comparison unit 30, closing the AND element 27 and causing the counter to stop.

At the same time, during the device operation cycles described above, the least significant bits of the variable code (Δx value) are supplied to the inputs of the multiplier 6 and, through the conversion unit to the additional code 5, to the inputs of the multiplier 7. At the outputs of the multipliers 6 and 7, the values Δx ² and ( 1 - Δx) ² . These values are respectively supplied to the first group of inputs of the multiplier 10 and to the input of the delay element 11. The code of the number 3 from the first installation bus 22 is supplied to the second group of inputs of the multiplier 10. At the output of the multiplier 10, the value 3 • Δx ² is generated, which is fed to the input of the subtracted block subtracting 13. The delayed value (1 - Δx) ² is supplied to the input of the block to be reduced 13. As a result of the subtraction operation, the value (1 - Δx) ² - 3 • Δx ² is formed at the output of block 13. The latter arrives at the first group of inputs of the multiplication block 17. Simultaneously, the values Δx ² delayed by the delay elements 12 and 14 from the output of the multiplier 6 and (1 - Δx) ² from the output of the multiplier 7 are supplied to the first groups of inputs of the multiplication blocks 15 and 19.

On the fourth clock cycle of the device in the multipliers 15, 17, 19, the products are subtracted, respectively 0.5 • g $\genfrac{}{}{0ex}{}{\text{3}}{\text{n-1}}$ Δx ² , 0.5 • g $\genfrac{}{}{0ex}{}{\text{3}}{\text{n}}$ [(1-Δx) ² -3 • Δx ² ], 0.5 • g $\genfrac{}{}{0ex}{}{\text{3}}{\text{n + 1}}$ (1-Δx) ² . . The calculation results are fed to the inputs of the adder 24. At the previous clock cycles, the calculation results in blocks 15, 17, 19 are not taken into account in the subsequent algorithm of the device.

 At the fifth clock cycle of the device, in block 24, the summation of the obtained products takes place, which corresponds to the formation of the value of the function f (x). At the end of the fifth cycle of the device, the contents of the counter 28 coincides with the number code supplied to the second installation bus 23. As a result, a unit level is generated at the output of the comparison unit 31. The latter is fed to the input of the register 25. The computational value of the function f (x) from the output of the adder 24 is written to the register 25. In addition, the unit level from the output of the comparison unit 31 is fed to the R-input of the RS-flip-flop 26, translating it to the zero state. As a result, the zero level from the output of the RS-flip-flop 26 closes the And 29 element and thereby prevents the passage of clock pulses through the And 29 element. This completes the work of the device for calculating the value of the function f (x). The device is ready for a new cycle of work.

Claims (2)

 1. An interpolator comprising in series a first multiplier, an adder and a first register, the information outputs of which are the output bus of the interpolator, a memory unit and a first counter, the information inputs of which are the input information bus of the interpolator, and the information outputs are connected to the address inputs of the memory unit, the converter into additional code, switch, second register and control unit, the first input of which is the start input of the interpolator, the second input is the clock input of the interpolator RA, the first output is connected to the zeroing input of the first register and the zeroing input of the first counter, and the second output is connected to the control input of the first register, characterized in that the second, third, fourth, fifth and sixth multipliers, the third and fourth registers are added to it, the first, second and third delay elements and a subtraction unit, in which the group of inputs of the delayed through the second delay element is connected to the outputs of the fourth multiplier, the first and second groups of inputs of which are bitwise combined and connected to the outputs converter into an additional code, and the group of inputs of the subtracted subtraction block is connected to the outputs of the third multiplier, the first group of inputs of which is connected to the outputs of the second multiplier, the first and second groups of inputs of which are bit-wise combined and connected to the inputs of the converter in the additional code and with the input information bus of the interpolator, and the outputs of the subtraction unit are connected to the first group of inputs of the fifth multiplier, the second group of inputs of which through the third register is connected to the second group of outputs of the commutator ora, and the outputs of the fifth multiplier are connected to the second group of information inputs of the adder, the third group of information inputs of which are connected to the outputs of the sixth multiplier, the first group of inputs of which through the third delay element is combined with the inputs of the second delay element, and the second group of inputs - through the fourth register with the third the group of outputs of the switch, the group of information inputs of which is connected to the outputs of the memory unit, and the group of address inputs is connected to the third group of outputs of the control unit the new bus of which is the first installation bus of the interpolator and is connected to the second group of inputs of the third multiplier, the first group of inputs of which through the first delay element is combined with the first group of inputs of the first multiplier, the second group of inputs of which through the second register is connected to the first group of outputs of the switch, the counting input of the first the counter is combined with the control inputs of the second, third and fourth registers and the fourth output of the control unit, the fifth output of which is connected to the control inputs I have the first, second and third delay elements, the control input of the subtraction unit and the control input of the adder, and the second installation bus of the control unit is the second installation bus of the interpolator.  2. The device according to claim 1, characterized in that the control unit is made comprising first and second comparison elements, a second counter, first and second elements And and an RS trigger, the S-input of which is combined with the zeroing input of the second counter, the first input of the control unit and the first output of the control unit, the R-input is connected to the output of the second comparison element and the second output of the control unit, and the output is connected to the first input of the second element And, the second input of which is connected to the second input of the control unit, and the output is the fifth output of the control unit connected to the first input of the first AND element and the counting input of the second counter, the information outputs of which are the third group of outputs of the control unit and are connected to the first group of inputs of the second comparison unit and the first group of inputs of the first comparison unit, the second group of inputs of which is the first installation bus of the control unit, and the output is connected to the second input of the first AND element, the output of which is the fourth output of the control unit, the second installation bus of which is connected to the second group of inputs cerned comparison unit.