RU2127901C1 - Spline interpolator - Google Patents

Abstract

FIELD: automation and computer engineering, in particular, automatic control systems. SUBSTANCE: device has memory units 1, 6, multipliers 7, 8, 9, 10, 11, 12, adder 13, register 14, control unit 3, counter 2, spline coefficients generation unit 4, and spline parameters generation unit 5. EFFECT: increased precision of interpolation for functions with continuous seventh derivative due to use of information about smoothness. 4 cl, 7 dwg

Description

 The invention relates to automation and computer engineering, in particular to polynomial and spline interpolators, and can be used in automatic control systems for reproducing nonlinear dependencies of one variable.

 Known devices (AS of the USSR N 1405074, G 06 F 15/353 of 10/27/1986, AS of the USSR N 1686461, G 06 F 15/353 of 02/13/1989) allow reproducing a wide class of functional dependencies, but have low accuracy.

 Closest to the claimed device in its technical essence is the "Spline interpolator" (USSR AS N 1686461, G 06 F 15/353 of 02/13/1989), selected as the prototype device.

 The prototype device contains the first and second counters, the first and second blocks of memory, the first, second, third and fourth blocks of multiplication, the adder, the result register, the control unit, and the start input of the interpolator is connected to the first input of the control unit, the clock input of the interpolator is connected to the second input control unit, the first output of which is connected to the reset inputs of the first, second counters and the result register, the second output is connected to the summing input of the first counter, the output of the first counter is connected to the first address input ohm of the first memory block, the output of which is connected to the first information inputs of the first, second, third, fourth multiplication blocks, the second information inputs of which are connected to the output of the second memory block, the outputs of the first, second, third, fourth multiplication blocks are connected respectively to the first, second, third, fourth inputs of the adder, the output of which is connected to the first information input of the result register, the output of which is the output of the interpolator, the first and second control inputs of the first, second, three fifth, fourth multiplication blocks are connected respectively to the third and fourth outputs of the control unit, the fifth, sixth, seventh, eighth, ninth, tenth and eleventh outputs of which are connected respectively to the first control input of the result register, with the subtracting input of the first counter, with the control input of the first block memory, with the control input of the second memory block, with the recording input of the second counter, with the subtracting input of the second counter, with the second control input of the result register, the second information input the second is connected to the output of the second memory unit, the input of the number of function values inside the interpolator interval is connected to the information input of the second counter and to the second address input of the first memory unit, the third address input of which is connected to the output of the first counter and to the third input of the control unit, the fourth input of which is connected with the third address input of the first memory block and with the output of the second counter, the input of the interpolator function value is connected to the information input of the second memory block.

где f $\genfrac{}{}{0ex}{}{\text{(3)}}{\text{max}}$ - максимум третьей производной функции f(x);
h - расстояние между отсчетами функции f(x).The known technical solution has insufficient interpolation accuracy, which is characterized by an interpolation error equal to

where f $\genfrac{}{}{0ex}{}{\text{(3)}}{\text{max}}$ is the maximum of the third derivative of the function f (x);
h is the distance between the samples of the function f (x).

Moreover, this accuracy is ensured for functions having a continuous third derivative (f (x) ∈ C ³ ). When interpolating functions having a continuous seventh derivative (f (x) ∈ C ⁷ ), the information on the smoothness of functions is not fully taken into account in this device, as a result of which the prototype does not provide the necessary accuracy.

The aim of the invention is to develop a device that provides higher accuracy of interpolation of functions having a continuous seventh derivative (f (x) ∈ C ⁷ ).
This goal is achieved by the fact that in the spline interpolator containing the first and second memory blocks, a counter, a control unit, the first, second, third and fourth multipliers, an adder and a register, the information counter inputs and address inputs of the first memory block are combined and connected to the first installation bus of the spline interpolator, and the counter outputs are connected to the third group of inputs of the control unit, the first input of which is the clock bus of the spline interpolator, the second input is the trigger bus of the spline interpolator, the tenth One is connected to the control input of the register and the subtracting input of the counter, and the eighth output of the control unit is connected to the control input of the second memory unit, the first, second, third and fourth groups of outputs of which are connected respectively to the first inputs of the first, second, third and fourth multipliers, the outputs of which connected respectively to the first, second, third and fourth groups of information inputs of the adder, the outputs of which are connected to the information inputs of the register, the outputs of which are outputs of the spline-int rpolyatora additionally introduced fifth and sixth multipliers generating unit and the spline coefficients of the spline generating unit parameters. The first input of the formation of the spline coefficients is connected to the ninth output of the control unit. The fourth, fifth, sixth and seventh groups of inputs of the control unit are respectively the second, third, fourth and fifth installation bus spline interpolator. The eleventh output of the control unit is connected to the sixth input of the spline parameter forming unit and the adder control input. The fifth and sixth groups of information inputs of the adder are connected respectively to the outputs of the fifth and sixth multipliers. The first groups of inputs of the fifth and sixth multipliers are connected respectively to the fifth and sixth groups of outputs of the second memory block. The information inputs of the second memory block are connected to the ninth group of outputs of the block forming the spline coefficients. The second, third, fourth, sixth, seventh and eighth groups of inputs of the block forming the spline coefficients, respectively, are the sixth, seventh, eighth, ninth, tenth and eleventh installation bus spline interpolator. The fifth group of inputs of the block forming the spline coefficients is the information bus of the spline interpolator. The twelfth installation bus of the spline interpolator is connected to the first group of inputs of the spline parameter forming unit. The second and third groups of inputs of the spline parameter forming unit are respectively the thirteenth and fourteenth installation buses of the spline interpolator. The fourth group of inputs of the spline parameter forming unit is connected to the outputs of the first memory block, and the fifth group of inputs is connected to the outputs of the counter. The control input of the counter is combined with the second input of the control unit and at the same time is the trigger bus for the spline interpolator. The seventh, eighth, ninth, tenth, eleventh and twelfth output groups of the spline parameter forming unit are connected to the second groups by input of the sixth, fifth, fourth, third, second and first multipliers, respectively.

 Block forming spline coefficients.

 The spline coefficient generating unit contains the first, second, third, fourth, fifth, sixth and seventh multipliers, the first, second, third, fourth, fifth, sixth, seventh and eighth delay elements, the first, second and third adders. The first group of inputs of the first multiplier is combined with the first groups of inputs of the second, third and fourth multipliers, the groups of information inputs of the first, third and sixth delay elements, the first group of the second adder and at the same time is the fifth group of inputs of the spline coefficient generation unit and the information bus of the spline interpolator. The second group of inputs of the first multiplier is the second group of inputs of the block forming the spline coefficients and the sixth installation bus of the spline interpolator, and the outputs are connected to the information inputs of the second delay element. The control input of the second delay element is combined with the control inputs of the first, third, fourth, fifth, sixth, seventh and eighth delay elements, the control inputs of the first, second and third adders and at the same time is the first input of the spline coefficient generation unit. The outputs of the second delay element are connected to the second group of inputs of the first adder. The first and third groups of inputs of the first adder, respectively, are connected to the outputs of the first and third delay elements, and the outputs are connected to the first group of inputs of the fifth multiplier. The second group of inputs of the fifth multiplier is the third group of inputs of the block forming the spline coefficients and the seventh installation bus of the spline interpolator, and the outputs are connected to the information inputs of the seventh delay element. The outputs of the seventh delay element are connected to the first group of inputs of the third adder. The second group of inputs of the third adder is connected to the outputs of the eighth delay element, the information inputs of which are combined with the third group of inputs of the second adder and the outputs of the fourth delay element. The information inputs of the fourth delay element are connected to the outputs of the third multiplier. The second group of inputs of the third multiplier is the fourth group of inputs of the block forming the spline coefficients and the eighth installation bus of the spline interpolator. The second group of inputs of the fourth multiplier is combined with the second group of inputs of the second multiplier and is the sixth group of inputs of the block forming the spline coefficients and the ninth installation bus of the spline interpolator. The outputs of the fourth multiplier are connected to the information inputs of the fifth delay element, the outputs of which are connected to the fourth group of inputs of the second adder. The second group of inputs of the second adder is connected to the outputs of the second multiplier, and the fifth group of inputs is connected to the outputs of the sixth delay element. The outputs of the second adder are connected to the first group of inputs of the sixth multiplier, the second group of inputs of which is the seventh group of inputs of the block forming the spline coefficients and the tenth installation bus of the spline interpolator, and the outputs are connected to the third group of inputs of the third adder. The outputs of the third adder are connected to the first group of inputs of the seventh multiplier, the second group of inputs of which is the eighth group of inputs of the block forming the spline coefficients and the eleventh installation bus of the spline interpolator, and the outputs are the ninth group of outputs of the block forming the spline coefficients.

 Block forming spline parameters.

 The spline parameter generating unit contains the first, second, third, fourth, fifth, sixth and seventh multipliers, a converter to an additional code, the first, second, third, fourth, fifth, sixth, seventh and eighth adders, the first, second, third, fourth, fifth and sixth delay elements, first, second, third, fourth, fifth and sixth fifth degree blocks. The first and second groups of inputs of the first multiplier, respectively, are the fifth and fourth groups of inputs of the block forming the spline parameters, and the outputs are connected to the inputs of the converter unit into an additional code, the first group of inputs of the first adder and the inputs of the first block of raising to the fifth degree. The outputs of the first block raising to the fifth degree are connected to the information inputs of the third delay element, the first group of inputs of the second multiplier and the first group of inputs of the third multiplier. The second group of inputs of the third multiplier is combined with the second group of inputs of the fourth, fifth and sixth multipliers and is the second group of inputs of the spline parameter forming unit and the thirteenth installation bus of the spline interpolator. The outputs of the third multiplier are connected to the first group of inputs of the fifth adder. The second group of inputs of the fifth adder is combined with the first group of inputs of the fourth multiplier and the outputs of the second block raising to the fifth degree, and the outputs of the fifth adder are connected to the information inputs of the fourth delay element. The outputs of the fourth delay element are the eleventh group of outputs of the spline parameter forming unit, and the control input is combined with the control inputs of the first, second, third, fourth, fifth, and sixth delay elements and the first, second, third, fourth, fifth, sixth, seventh and eighth adders and is the sixth input of the spline parameter forming unit. The second group of inputs of the second multiplier is combined with the second group of inputs of the seventh multiplier and is the first group of inputs of the spline parameter forming unit and the twelfth installation bus of the spline interpolator, and the outputs are connected to the information inputs of the first delay element. The outputs of the first delay element are connected to the first group of inputs of the sixth adder. The second group of inputs of the sixth adder is connected to the outputs of the fourth multiplier, and its outputs are the tenth group of outputs of the spline parameter forming unit. The second group of inputs of the first adder is combined with the second groups of inputs of the second, third and fourth adders and is the third group of inputs of the spline parameter forming unit and the fourteenth installation bus of the spline interpolator. The outputs of the first adder are connected to the inputs of the second block raising to the fifth degree and the first group of inputs of the third adder. The outputs of the third adder are connected to the inputs of the fifth block of raising to the fifth degree, the outputs of which are connected to the third group of inputs of the sixth adder. The outputs of the converter in the additional code are connected to the inputs of the fourth block raising to the fifth degree and the first group of inputs of the second adder. The outputs of the second adder are connected to the inputs of the third fifth degree block and the first group of inputs of the fourth adder, the outputs of which are connected to the inputs of the sixth fifth degree block. The outputs of the sixth fifth degree block are connected to the first group of inputs of the seventh adder, the second group of inputs of which are connected to the outputs of the fifth multiplier. The first group of inputs of the fifth multiplier is connected to the outputs of the third block of raising to the fifth degree and the first group of inputs of the eighth adder. The second group of inputs of the eighth adder is connected to the outputs of the sixth multiplier, and the outputs are connected to the information inputs of the fifth delay element. The outputs of the fifth delay element are the eighth group of outputs of the spline parameter forming unit. The outputs of the fourth block of raising to the fifth degree are connected to the first group of inputs of the sixth multiplier, the first group of inputs of the seventh multiplier and the information inputs of the sixth delay element, the outputs of which are the seventh group of outputs of the spline parameter forming unit. The outputs of the seventh multiplier are connected to the information inputs of the second delay element, the outputs of which are connected to the third group of inputs of the seventh adder. The outputs of the seventh adder are the ninth group of outputs of the spline parameter forming unit. The outputs of the third delay element are the twelfth group of outputs of the spline parameter forming unit.

 Control block.

 The control unit contains the first and second RS-flip-flops, the first, second, third and fourth AND elements, the first and second counters, the first, second, third and fourth comparison blocks, the delay element and the element NOT. The first group of inputs of the first comparison unit is the third group of inputs of the control unit. The second group of inputs is combined with the information inputs of the second counter and is the fourth group of inputs of the control unit and the second installation bus of the spline interpolator, and the output is connected to the R-input of the first RS-trigger. The S-input of the first RS-trigger is combined with the reset input of the first counter, the control input of the second counter, the S-input of the second RS-trigger and at the same time is the second input of the control unit and the trigger bus of the spline interpolator. The output of the first RS-trigger is connected to the first input of the first element I. The second input of the first element And is the first input of the control unit and the clock bus of the spline interpolator, and the output is connected to the second input of the fourth element And and the first input of the second element I. The output of the second element And is the ninth output of the control unit and is simultaneously connected to the first input of the third AND element and the counting input of the first counter. The outputs of the first counter are connected to the first group of inputs of the third comparison unit. The second group of inputs of the third comparison unit is the sixth group of inputs of the control unit and the fourth installation bus of the spline interpolator, and the output is connected to the second input of the second AND element and the input of the NOT element. The output of the element is NOT connected to the R-input of the second RS-flip-flop, the inverse output of which is connected to the first input of the fourth element I. The output of the fourth element And is the eleventh output of the control unit and is simultaneously connected to the counting input of the second counter, the outputs of which are connected to the first group of inputs of the fourth block comparison. The second group of inputs of the fourth comparison unit is the seventh group of inputs of the control unit and the fifth installation bus of the spline interpolator, and the output is connected to the reset input of the second counter and the input of the delay element. The output of the delay element is the tenth output of the control unit. The second group of inputs of the second comparison unit is the fifth group of inputs of the control unit and the third installation bus of the spline interpolator, and the output is connected to the second input of the third element I. The output of the third element And is the eighth output of the control unit.

The listed new set of essential features of the claimed device provides a higher accuracy of interpolation of functions having a continuous seventh derivative (f (x) ∈ C ⁷ ). This is achieved by the fact that the interpolation is carried out more accurately based on a priori information about the degree of smoothness of the function.

The claimed device is illustrated by drawings, in which:
in FIG. 1 shows a structural diagram of the claimed device;
in FIG. 2 is a structural diagram of a block for generating spline coefficients;
in FIG. 3 is a structural diagram of a spline parameter forming unit;
in FIG. 4 shows a block diagram of a control unit;
in FIG. 5 shows one of the possible options for constructing a second memory block;
in FIG. 6 shows an embodiment of a delay element;
in FIG. 7 presents one of the possible options for the implementation of the block raising to the fifth degree.

 The spline interpolator shown in FIG. 1, consists of memory blocks 1 and 6, multipliers 7, 8, 9, 10, 11 and 12, an adder 13, a register 14, a control unit 3, a counter 2, a unit for generating spline coefficients 4 and a unit for generating spline parameters 5. Information group the inputs of the counter 2 are combined with the address inputs of the first memory block 1 and at the same time is the first installation bus 15 of the spline interpolator. The subtractive input of the counter 2 is combined with the control input of the register 14 and the tenth output of the control unit 3. The information outputs of the counter 2 are combined with the third group of inputs of the control unit 3. The first input of the control unit 3 is the clock bus 17 of the spline interpolator, the second input is the start bus 18. The eighth output of the control unit 3 is connected to the control input of the second memory unit 6. The first, second, third, fourth, fifth and sixth groups of information outputs of the memory unit 6 are connected to the first groups of inputs, respectively, multiply her 7, 8, 9, 10, 11 and 12. The groups of outputs of the multipliers 7, 8, 9, 10, 11 and 12 are connected respectively to the first, second, third, fourth, fifth and sixth groups of inputs of the adder 13. Group of outputs of the adder 13 connected to the information inputs of the register 14, the outputs of which are a group of information outputs of the spline interpolator. The fourth group of inputs of the spline parameter forming unit 5 is connected to the information outputs of the first memory unit 1. The first group of inputs of the spline parameter forming unit is connected to the twelfth installation bus 29 of the spline interpolator. The fifth group of inputs of the spline parameter forming unit is connected to the information outputs of the counter 2. The second group of inputs of the spline parameter forming unit is connected to the thirteenth installation bus 30 of the spline interpolator. The third group of its inputs is the fourteenth installation bus 31 of the spline interpolator. The fifth group of inputs of block 5 is also combined with the third group of inputs of control unit 3. The twelfth, eleventh, tenth, ninth, eighth and seventh groups of outputs of the block forming parameters of spline 5 are connected to the second groups of inputs of multipliers 7, 8, 9, 10, 11, and 12 respectively. The sixth input of the spline 5 parameter forming unit is combined with the control input of the adder 13 and the eleventh output of the control unit 3. The second input of the control unit 3 is combined with the control input of the counter 2 and at the same time is the trigger bus 18 of the spline interpolator. The fourth group of inputs of the control unit 3 is the second installation bus 16 of the spline interpolator, the fifth group of inputs is the third installation bus 19 of the spline interpolator, the sixth group of inputs is the fourth installation bus 20 of the spline interpolator. The seventh group of inputs of the control unit 3 is the fifth installation bus 21 of the spline interpolator. The eighth output of the control unit 3 is connected to the control input of the second memory block 6. The ninth output of the control unit is connected to the first input of the spline coefficient generation unit 4. The tenth output of block 3 is combined with a subtracting counter input and a register control input. The eleventh output of block 3 is combined with the fifth input of the spline parameter generating unit 5 and the control input of the adder 13. The second group of inputs of the spline coefficient generating unit 4 is the sixth information bus 22 of the spline interpolator, the third group of inputs is the seventh installation bus 23 of the spline interpolator, the fourth group inputs - the eighth installation bus 24 of the spline interpolator. The fifth group of inputs of block 4 is the information bus 25 of the spline interpolator. The sixth group of inputs of block 4 is the ninth installation bus 26 of the spline interpolator. The seventh group of outputs of block 4 is connected to the tenth installation bus 27 of the spline interpolator. The eighth group of inputs of block 4 is the eleventh installation bus 28 of the spline interpolator. The ninth group of outputs of block 4 is connected to the information inputs of the second memory block 6.

 The spline 4 coefficient generating unit shown in FIG. 2 consists of multipliers 41, 42, 43, 44, 412, 416 and 418, delay elements 45, 46, 47, 48, 49, 410, 414 and 415, adders 411, 413 and 417. The first group of inputs of the first multiplier 41 combined with the first groups of inputs of the multipliers 42, 43 and 44, the groups of information inputs of the delay elements 45, 47 and 410, the first group of inputs of the adder 413 and at the same time is the fifth group of inputs of the block forming the coefficients of the spline 4 and the information bus 25 of the spline interpolator. The second group of inputs of the multiplier 41 is the second group of inputs of the block forming the coefficients of the spline 4 and the installation bus 22 of the spline interpolator, and the outputs are connected to the information inputs of the delay element 46. The control input of the delay element 46 is combined with the control inputs of the delay elements 45, 47, 48, 49 , 410, 414 and 415, controlling the inputs of the adders 411, 413 and 417 and at the same time is the first input of the block forming the coefficients of the spline 4. The outputs of the delay element 46 are connected to the second group of inputs of the adder 411. The first and third I groups of inputs of the adder 411 are respectively connected to the outputs of the delay elements 45 and 47, and the outputs are connected to the first group of inputs of the multiplier 412. The second group of inputs of the multiplier 412 is the third group of inputs of the block forming the coefficients of the spline 4 and the installation bus 23 of the spline interpolator, and the outputs are connected with the information inputs of the delay element 414. The outputs of the delay element 414 are connected to the first group of inputs of the adder 417. The second group of inputs of the adder 417 is connected to the outputs of the delay element 415, information inputs otorrhea combined with the third group of inputs of the adder 413 and outputs the delay element 48. Information inputs of the delay element 48 are connected to outputs of the multiplier group 43. The second input of multiplier 43 is the fourth group of inputs forming unit 4 and the spline coefficients of the mounting rail 24 spline interpolator. The second group of inputs of the multiplier 44 is combined with the second group of inputs of the multiplier 42 and is the sixth group of inputs of the block forming the coefficients of the spline 4 and the installation bus 26 of the spline interpolator. The outputs of the multiplier 44 are connected to the information inputs of the delay element 49, the outputs of which are connected to the fourth group of inputs of the adder 413. The second group of inputs of the adder 413 is connected to the outputs of the multiplier 42, and the fifth group of inputs is connected to the outputs of the delay element 410. The outputs of the adder 413 are connected to the first group the inputs of the multiplier 416, the second group of inputs of which is the seventh group of inputs of the block forming the coefficients of the spline 4 and the installation bus 27 of the spline interpolator, and the outputs are connected to the third group of inputs of the adder 417 The outputs of the adder 417 are connected to the first group of inputs of the multiplier 418, the second group of inputs of which is the eighth group of inputs of the block forming the coefficients of spline 4 and the installation bus 28 of the spline interpolator, and the outputs are the ninth group of outputs of the block of forming the coefficients of spline 4.

 The spline parameter generating unit 5 shown in FIG. 3, consists of multipliers 51, 511, 512, 513, 516, 517 and 518, a converter to additional code 52, adders 53, 54, 57, 58, 521, 522, 523 and 524, delay elements 519, 520, 525, 526, 527 and 528, fifth degree blocks 55, 56, 59, 510, 514 and 515. The first and second groups of inputs of the multiplier 51 are respectively the fifth and fourth groups of inputs of the block forming the parameters of spline 5, and the outputs are connected to the inputs of the converter block in additional code 52, the first group of inputs of the adder 53 and the inputs of the block raising to the fifth degree 55. The outputs of the block raising to the fifth degree 55 connected to the information inputs of the delay element 525, the first group of inputs of the multiplier 511 and the first group of inputs of the multiplier 512. The second group of inputs of the multiplier 512 is combined with the second groups of inputs of the multipliers 513 and 516 and is the second group of inputs of the block forming the parameters of spline 5 and the installation bus 30 spline interpolator. The outputs of the multiplier 512 are connected to the first group of inputs of the adder 521. The second group of inputs of the adder 521 is combined with the first group of inputs of the multiplier 513 and the outputs of the fifth power block 56, and the outputs of the adder 521 are connected to the information inputs of the delay element 526. The outputs of the delay element 526 are the eleventh the group of outputs of the spline parameter forming unit 5, and the control input is combined with the control inputs of the delay elements 519, 520, 525, 527 and 528 and the adders 53, 54, 57, 58, 521, 522, 523 and 524 and is the sixth input of the forming unit the parameters of the spline 5. The second group of inputs of the multiplier 511 is combined with the second group of inputs of the multiplier 518 and is the first group of inputs of the block for generating parameters of the spline 5 and the installation bus 29 of the spline interpolator, and the outputs are connected to the information inputs of the delay element 519. The outputs of the delay elements 519 are connected with the first group of inputs of the adder 522. The second group of inputs of the adder 522 is connected to the outputs of the multiplier 513, and the outputs of block 522 are the tenth group of outputs of the block forming the parameters of spline 5. The second group and the inputs of the adder 53 is combined with the second groups of inputs of the adders 54, 57 and 58 and is the third group of inputs of the spline parameter forming unit 5 and the installation bus 31 of the spline interpolator. The outputs of the adder 53 are connected to the inputs of the fifth degree block 56 and the first group of inputs of the adder 57. The outputs of the adder 57 are connected to the inputs of the fifth degree block 514, the outputs of which are connected to the third group of inputs of the adder 522. The outputs of the converter into additional code 52 are connected to the inputs of the fifth degree block 510 and the first group of inputs of the adder 54. The outputs of the adder 54 are connected to the inputs of the fifth degree block 59 and the first group of inputs of the adder 58, the outputs of which are connected to the inputs of the block the fifth degree 515. The outputs of the fifth degree 515 are connected to the first group of inputs of the adder 523, the second group of inputs of which is connected to the outputs of the multiplier 516. The first group of inputs of the multiplier 516 is connected to the outputs of the fifth degree block 59 and the first group of inputs adder 524. The second group of inputs of adder 524 is connected to the outputs of the multiplier 517, and the outputs are connected to the information inputs of the delay element 527. The outputs of the delay element 527 are the eighth group of outputs of the parameter forming unit spline 5. The outputs of the fifth degree block 510 are connected to the first group of inputs of the multiplier 517, the first group of inputs of the multiplier 518 and the information inputs of the delay element 528, the outputs of which are the seventh group of outputs of the block forming the parameters of the spline 5. The outputs of the multiplier 518 are connected to the information inputs of the element delays 520, the outputs of which are connected to the third group of inputs of the adder 523. The outputs of the adder 523 are the ninth group of outputs of the spline parameter generating unit 5. The outputs of the delay element 525 are are the twelfth group of outputs of the block forming the parameters of spline 5.

 The control unit 3 shown in FIG. 4, consists of RS-flip-flops 31 and 310, AND element 33, 34, 37 and 311, counters 35 and 312, comparison units 32, 36, 38 and 313, delay element 314 and element NOT 39. The first group of inputs of comparison unit 32 is the third group of inputs of the control unit 3. The second group of inputs of the unit 32 is combined with the information inputs of the counter 312 and is the fourth group of inputs of the control unit 3 and the installation bus 16 of the spline interpolator, and the output is connected to the R-input of the RS flip-flop 31. S-input The RS flip-flop 31 is combined with the reset input of the counter 35, the control input of the counter 312, the S-input of the RS-three 310 and at the same time is the second input of the control unit 3 and the trigger bus of the spline interpolator 18. The output of the RS trigger 31 is connected to the first input of the And 33 element. The second input of the And 33 element is the first input of the control unit 3 and the clock bus 17 of the spline interpolator, and the output is connected to the second input of the element And 311 and the first input of the element And 34. The output of the element And 34 is the ninth output of the control unit 3 and is simultaneously connected to the first input of the element And 37 and the counting input of the counter 35. The outputs of the counter 35 are connected to the first group of inputs of and comparisons 38. The second group of inputs of the comparison unit 38 is the sixth group of inputs of the control unit 3 and the installation bus 20 of the spline interpolator, and the output is connected to the second input of the AND 34 element and the input of the HE 39 element. The output of the HE 39 element is connected to the R-input RS -trigger 310, the inverse output of which is connected to the first input of the And 311 element. The output of the And 311 element is the eleventh output of the control unit 3 and is simultaneously connected to the counting input of the counter 312, the outputs of which are connected to the first group of inputs of the comparison unit 313. The second group of inputs the comparison block 313 is the seventh group of inputs of the control unit 3 and the installation bus 21 of the spline interpolator, and the output is connected to the reset input of the counter 312 and the input of the delay element 314. The output of the delay element 314 is the tenth output of the control unit 3. The second group of inputs of the comparison unit 36 is the fifth group of inputs of the control unit 3 and the installation bus 19 of the spline interpolator, and the output is connected to the second input of the element And 37. The output of the element And 37 is the eighth output of the control unit 3.

где h - шаг между отсчетами функции f(x);
b $\genfrac{}{}{0ex}{}{\text{m}}{\text{h}}$ - B-сплайн степени m-1:

C $\genfrac{}{}{0ex}{}{\text{m}}{\text{i}}$ - число сочетаний из m по i:

x = h(N+τ), τ∈[0,1].
Для сплайна пятой степени m = 6, s = 0, коэффициент g_n ^m+s в выражении (2) вычисляется по формуле

Из (3) можно получить

Из статей: Желудев В.А. Локальная сплайн-аппроксимация на равномерной сетке. / Журнал вычислительной математики и математической физики. - 1987. - Том 27. - N 9. - С. 1296 - 1310. и Желудев В.А. Восстановление функций и их производных по сеточным данным с погрешностью при помощи локальных сплайнов. / Журнал вычислительной математики и математической физики. - 1987. - Том 27. - N 1. - С. 22 - 34 известно, что значение B-сплайна b $\genfrac{}{}{0ex}{}{\text{6}}{\text{h}}$ (x) отлично от нуля на участке (0, 6h) и на различных интервалах наблюдения определяется следующим образом:
[x_i,x_i+1] (когда x∈[hi,h(i+1)], x = h(i+τ), τ∈[0,1]):

[x_i+2,x_i+3] (когда x∈[h(i+2),h(i+3)], x = h(i+2+τ)):

Учитывая, что носитель B-сплайна supp b $\genfrac{}{}{0ex}{}{\text{6}}{\text{h}}$ (x) = (0,6h) и b⁶(x) симметричен относительно точки h • m/2 (за τ можно принять (1 - τ)), получим для интервалов
[x_i+3,x_i+4] (когда x∈[h(i+3),h(i+4)], x = h(i+3+τ)):

[x_i+4,x_i+5] (когда x∈[h(i+4),h(i+5)], x = h(i+4+τ)):

[x_i+5,x_i+6] (когда x∈[h(i+5),h(i+6)], x = h(i+5+τ)):

Тогда из выражения (2)

где g_n определяется из (4).The implementation of the claimed device is explained as follows. From the articles: Zheludev V.A. Local spline approximation on a uniform grid. / Journal of Computational Mathematics and Mathematical Physics. - 1987. - Volume 27. - N 9. - S. 1296 - 1310. and Zheludev V.A. Recovery of functions and their derivatives from grid data with an error using local splines. / Journal of Computational Mathematics and Mathematical Physics. - 1987. - Volume 27. - N 1. - P. 22 - 34 it is known that the expression for calculating the s-th derivative of the spline can be written

where h is the step between the samples of the function f (x);
b $\genfrac{}{}{0ex}{}{\text{m}}{\text{h}}$ - B-spline of degree m-1:

C $\genfrac{}{}{0ex}{}{\text{m}}{\text{i}}$ - the number of combinations from m to i:

x = h (N + τ), τ∈ [0,1].
For a fifth-degree spline, m = 6, s = 0, the coefficient g _n ^{m + s} in expression (2) is calculated by the formula

From (3) we can obtain

From the articles: Zheludev V.A. Local spline approximation on a uniform grid. / Journal of Computational Mathematics and Mathematical Physics. - 1987. - Volume 27. - N 9. - S. 1296 - 1310. and Zheludev V.A. Recovery of functions and their derivatives from grid data with an error using local splines. / Journal of Computational Mathematics and Mathematical Physics. - 1987. - Volume 27. - N 1. - P. 22 - 34 it is known that the value of the B-spline b $\genfrac{}{}{0ex}{}{\text{6}}{\text{h}}$ (x) is nonzero at (0, 6h) and at different observation intervals is defined as follows:
[x _i , x _{i + 1} ] (when x∈ [hi, h (i + 1)], x = h (i + τ), τ∈ [0,1]):

[x _{i + 2} , x _{i + 3} ] (when x∈ [h (i + 2), h (i + 3)], x = h (i + 2 + τ)):

Given that the support of the B-spline supp b $\genfrac{}{}{0ex}{}{\text{6}}{\text{h}}$ (x) = (0,6h) and b ⁶ (x) is symmetric with respect to the point h • m / 2 (for τ we can take (1 - τ)), we obtain for the intervals
[x _{i + 3} , x _{i + 4} ] (when x∈ [h (i + 3), h (i + 4)], x = h (i + 3 + τ)):

[x _{i + 4} , x _{i + 5} ] (when x∈ [h (i + 4), h (i + 5)], x = h (i + 4 + τ)):

[x _{i + 5} , x _{i + 6} ] (when x∈ [h (i + 5), h (i + 6)], x = h (i + 5 + τ)):

Then from the expression (2)

where g _n is determined from (4).

Точность же устройства-прототипа не лучше

Поэтому, например, для функций f ∈ C⁷ при h = 0,1 и в случае f⁽³⁾ _max ≈ f⁶ _max выигрыш может достигать μ₁/μ₂ свыше тысячи.Realization of (5) in the form of a device allows one to calculate the functions f (x) ∈ C ⁷ with an accuracy determined by the error (Zheludev V.A. Restoration of functions and their derivatives from grid data with an error using local splines. / Journal of Computational Mathematics and Mathematical Physics . - 1987. - Volume 27. - N 1. - p. 24)

The accuracy of the prototype device is no better.

Therefore, for example, for functions f ∈ C ⁷ with h = 0.1 and in the case f ⁽³⁾ _max ≈ f ⁶ _{max, the} gain can reach μ ₁ / μ ₂ over a thousand.

 The operation of the spline interpolator based on FIG. 1 and expression (5) is as follows.

In the initial state, the code of the number M is supplied to the installation bus 15. The clock signals of the meander type are received on the clock bus 17. On the installation bus 16 there is a code of the number 0, on the installation bus 19 - the code of the number 8, on the installation bus 20 - the code of the number 14, on the installation bus 21 - the code of the number 7, on the installation bus 22 - the code of the number - 2, on the installation bus 23 - code number -1/4, on installation bus 24 - code number 6, on installation bus 26 - code number -4, on installation bus 27 - code number 13/240, on installation bus 28 - code number 1/120, on docking bus 29 - code numbers 15, 30 on the mounting rail - -6 number code on the mounting rail 31 - 1. The code number storage unit 1 recorded values τ ₀ so that the cell M is stored with the address value τ _{0 /} equal to 1 / (1 + M).

When a positive polarity pulse is applied to the start bus 18, the code of number M is written to counter 2. The data of function f (x): f _-2 , f _-1 , ..., f ₃ , which enter the coefficient generation block, are sent to data bus 25 spline 4. Under the influence of the control signals supplied to the installation bus 22, 23, 24, 26, 27, 28, as well as the signals from the output of the control unit 3, in the block forming the coefficients of the spline 4, the coefficient is calculated (1/120) • g _-2 . The specified value is written to the memory unit 6 under the influence of a pulse supplied to its control input from the output of the control unit 3.

Then, in a similar way, in the block for generating the coefficients of spline 4, the values (1/120) • g _-1 , (1/120) • g ₀ , (1/120) • g ₁ , (1/120) • g ₂ , (1 / 120) • g ₃ , which are recorded in memory unit 6.

After that, under the influence of information signals (coming from the outputs of blocks 1 and 2, and also supplied to the installation buses 29, 30 and 31) and control signals (from the output of the control unit 3) in the block for generating parameters of spline 5, the values are calculated: τ ⁵ , [(1 + τ) ⁵ - 6 τ ⁵ ], [(2 + τ) ⁵ - 6 (1 + τ) ⁵ + 15 τ ⁵ ], [(3 - τ) ⁵ - 6 (2 - τ) ⁵ + 15 (1 - τ) ⁵ ], [(2 - τ) ⁵ - 6 (1 - τ) ⁵ ], (1 - τ) ⁵ . The obtained values are received at the first inputs of the multipliers 7, 8, 9, 10, 11 and 12. The corresponding inputs are received at the second inputs of the last (1/120) • g _-2 , (1/120) • g _-1 , (1/120 ) • g ₀ , (1/120) • g ₁ , (1/120) • g ₂ , (1/120) • g ₃ .

As a result of performing the operations of multiplication at the outputs of the multipliers 7, 8, 9, 10, 11 and 12, the products are formed (1/120) • g ₃ τ ⁵ , (1/120) • g ₂ [(1 + τ) ⁵ - 6 τ ⁵ ], (1/120) • g ₁ [(2 + τ) ⁵ - 6 (1 + τ) ⁵ + 15 τ ⁵ ], (1/120) • g ₀ [(3 - τ) ⁵ - 6 ( 2 - τ) ⁵ + 15 (1 - τ) ⁵ ], (1/120) • g _-1 [(2 - τ) ⁵ - 6 (1 - τ) ⁵ ], (1/120) • g _-2 (1 - τ) ⁵ . The obtained values go to the corresponding groups of inputs of the adder 13.

 In block 13, the summation of these works is performed under the influence of signals arriving at its control input (from control output 3). As a result, at the output of the adder 13, the value of the function f (x) at the first interpolation point is generated.

 The obtained value of the function f (x) is written to the register 14 using a single pulse from the output of the control unit 3 to the input of the register register 14. In addition, the same single pulse from the output of the control unit 3 is fed to the subtracting input of the counter 2, reducing its content per unit.

Further, the algorithm of the device is similar. In block 5, the values of the spline parameters are generated, and in blocks 7 through 13, the values of the function f (x) are calculated, which are recorded in register 14. This operation is repeated for values of τ equal to τ ₀ · (M-1), then τ ₀ · ( M-2) etc. until the contents of counter 2 become zero. In this case, the code number 0 from the output of the counter 2 is fed to the input of the control unit 3, which stops the operation of the device. This completes the work of the device for calculating the values of the function f (x). The device is ready for a new cycle of work.

The elements included in the structural diagram of the claimed device are known and described, for example, in the book of V.L. Awl. Popular digital circuits. Directory. - M .: Radio and communications, 1988. So, in the specified source describes the principles of construction and implementation examples
counter 2 on page 85 - 86 (can be implemented on the K155IE5 chip);
memory block 1 on page 171 - 174 (can be implemented on the K155PR6 chip);
register 14 on p. 104 - 105 (can be implemented on the K155IR13 microcircuit - p. 111, Fig. 1.78).

 The principle of operation of the multipliers 7, 8, 9, 10, 11 and 12 is known and described in the book: M. A. Kartsev, V. A. Brick. Computing systems and synchronous arithmetic. - M .: Radio and communications, 1981, p. 163 - 221. They can be implemented on the SN54284 and SN54285 world circuits, p. 305, fig. 6.3.12, or on the ADSP1016 chip (S. Kun. Matrix processors on VLSI: Transl. From English. - M.: Mir, 1991, p. 502, table 7.4).

 The principle of operation of the adder 13 is known and described in the book: D. Givone, R. Rosset. Microprocessors and microcomputers: Introductory course: Per. from English - M .: Mir, 1983, p. 184 - 198. The full adder is described in the book of V.L. Awl. Popular digital circuits. Directory. 2nd ed., Rev., - Chelyabinsk: Metallurgy, 1989, p. 152, fig. 1.112, p. 153, fig. 1.113. It can be implemented on the elements of EXCL. OR - K155LP5, AND - K155LI1, OR - from OR-NOT K155LE4 and NOT K155LN1.

 One of the possible options for constructing the memory block 6 is shown in FIG. 5. The memory block 6 consists of six series-connected registers. The inputs of the register of the block registers are connected and connected to the control input of the block 6. The input of the first register is the information input of the block. The outputs of the registers are the output information buses of the block. Registers can be implemented on the K155IR13 chip.

 The operation of the spline 4 coefficient generating unit based on FIG. 2 is carried out as follows.

 In the initial state, input 4.2 is supplied with the code of the number -2 from the installation bus 22 of the device. At the input 4.3, the code of the number -1/4 is supplied from the installation bus 23 of the device. Input 4.4 receives the code number 6 from the installation bus 24 of the device. Input 4.6 contains the code number -4 from the installation bus 26 of the device. Input 4.7 serves the code number 13/240 from the installation bus 27 of the device. Input 4.8 contains the code number 1/120 from the installation bus 28 of the device.

When applying to the input 4.1 of the block 4 control pulses (from the output 3.9 of the control unit 3) to the input 4.5 the values of the function f (x): f _-3 , f _-2 , ..., f ₅ . The latter alternately follow in eight directions: to the first inputs of the multipliers 44, 43, 42, and 41, the inputs of the delay elements 410, 47, and 45, and the first input of the adder 413. Blocks 41, 45, 46, and 47 form three terms that go to the input of the adder 411 at the same time. The result of the calculation in adder 411 is the value of δ ² f _n (see expression (4)). Blocks 42, 43, 44, 48, 49 and 410 form four terms for the adder 413. The fifth term comes from input 4.5 to the adder 413 directly. All five terms are fed to the inputs of the adder 413 at the same time. As a result of the addition operation, the values of δ ⁴ f _n are generated at the output of the adder 413 (see expression (4)). The quantity δ ² f _n times -1/4 in block 412 and delayed in block 414 is the first term for adder 417. The second term is the value f _{n of the} function f (x) delayed in block 415. The third term is δ ⁴ f _n multiplied in block 416 by 13/240. The result of the operation in block 417 of the summation operation is multiplied in block 418 by the number 1/120. As a result, at the output of the block forming the coefficients of spline 4, the coefficient value (1/120) g _{n is formed} (see expression (5)).

 One of the possible options for constructing delay elements 45, 46, 47, 48, 49, 410, 414 and 415 is shown in FIG. 6. In accordance with FIG. 6, these blocks are made up of n series-connected registers. The inputs of the register entries are connected and connected to the control input of the block. The input of the first register is the information input of the block. The output of the nth register is the output of the block. Registers can be implemented on the K155IR13 chip. For delay elements 45, 46, 48 and 414 n = 2. For delay element 49 n = 3. For delay element 47 n = 4. For delay elements 410 and 415 n = 5.

 Multipliers 41 - 44, 412, 416 and 418 can be implemented on the SN54284 and SN54285 chips or on the ADSP1016 chip.

 Adders 411, 413 and 417 can be implemented on K155LP5, K155LI1, K155LE4 and NOT K155LN1.

 The operation of the spline parameter forming unit 5 based on FIG. 3 is carried out as follows.

 In the initial state, the code number 15 from the installation bus 29 is input to input 5.1 of the spline 5 parameter generation unit. The number -6 code from the bus 30 is input to input 5.2. The code 1 from the installation bus 31 is input to input 5.3. The control signals are input to input 5.6 output 3.11 of the control unit 3.

A first input of multiplier 51 receives the value of τ ₀ from the output of the storage unit 1, and a second input of multiplier 51 - value M output from the counter 2. As a result of the multiplication operation on the output value of the multiplier 51 is formed M · τ = τ _0. The latter goes to the input of the converter in additional code 52, at the output of which we have the value (1-τ). The value of τ from the output of the multiplier 51 also goes to the first input of the adder 53, and to the first input of the adder 54, the value (1-τ). The code of number 1 is supplied to the second inputs of adders 53 and 54. Under the influence of control signals received at input 5.6 of block 5 (from output 3.11 of control unit 3), values of (1 + τ) and (2- τ). The latter are fed to the first inputs of the adders 57 and 58, respectively. A code of the number 1 is supplied to the second inputs of the adders. As a result of the summation operation, the outputs of adders 57 and 58 generate values of τ + 2 and 3-τ, respectively. The indicated values are supplied to the inputs of the corresponding blocks of raising to the fifth power 514 and 515. At the input of the block of raising to the fifth power 55, the value τ is received from the output of the multiplier 51. The value of τ + 1 from the output of the adder 53 is received at the input of the block of raising to the fifth power 56. the input of the block of raising to the fifth power 59 receives the value of 2-τ from the output of the adder 54. The input of the block of raising to the fifth power 510 receives the value 1-τ from the output of the converter to the additional code 52. At the outputs of the blocks of raising to the fifth power 55, 56, 514 , 515, 59 and 510 have the meanings respectively, τ ⁵ , (τ + 1) ⁵ , (τ + 2) ⁵ , (3-τ) ⁵ , (2-τ) ⁵ and (1-τ) ⁵ . The value of τ ⁵ from the output of the fifth degree raising block 55 is supplied to the first inputs of the multipliers 511 and 512. The code of the number 15 is supplied to the second input of the multiplier 511, and the code of the number -6 is sent to the second input of the multiplier 512. As a result of the multiplication operation, the outputs of the multipliers 511 and 512 generate values of 15τ ⁵ and -6τ ^5, respectively. The values (τ + 1) ⁵ and (2-τ) ⁵ are fed to the first inputs of the multipliers 513 and 516, respectively. At the second inputs of these multipliers, the code of the number -6 is supplied. As a result of the operation of multiplication, the outputs of the multipliers 513 and 516 generate values of -6 (τ + 1) ⁵ and -6 (2-τ) ^5, respectively. The value (1-τ) ⁵ from the output of the fifth degree block 510 is supplied to the first inputs of the multipliers 517 and 518. The code of the number -6 is supplied to the second input of the multiplier 517, and the code of the number 15 is sent to the second input of the multiplier 518. As a result of the operation multiplication at the outputs of the multipliers 517 and 518 values are formed, respectively -6 (1-τ) ⁵ and 15 (1-τ) ⁵ . From the output of the multiplier 512, the value -6τ ^{5 is} supplied to the first input of the adder 521. At the same time, the value (τ + 1) ^{5 is} supplied to the second input of adder 521 from the output of the fifth power raising block 56. As a result of the summation operation, the value (τ + 1) ⁵ - 6τ ⁵ is generated at the output of adder 521. The latter through the delay element 526 is fed to the output 5.11 of the spline parameter generation block 5. The value of 15τ ⁵ from the output of the multiplier 511 is fed through the delay element 519 to the first input of the adder 522. At the same time, the value -6 (τ + 1) ^{5 is} output multiplier 513, and to the third input, the value (τ + 2) ⁵ from the output of the fifth degree 514 block. As a result of the summation operation, the output of adder 522 generates the value 15τ ⁵ + (τ + 2) ⁵ - 6 (τ + 1 ) ⁵ . The latter is fed to the output 5.10 of block 5. From the output of the multiplier 517, the value -6 (τ-1) ^{5 is} supplied to the first input of the adder 524. At the same time, the value (2-τ) ⁵ arrives at the second input of the adder 524 from the output of the fifth power raising block 59. As a result of the summation operation, the value (2-τ) ⁵ - 6 (1-τ) ⁵ is generated at the output of the adder 524. The latter, through the delay element 527, is fed to the output 5.8 of the spline parameter generation block 5. The value of 15 (1-τ) ⁵ from the output of the multiplier 518 is fed through the delay element 520 to the first input of adder 523. At the same time, the value -6 (2- τ) ⁵ from the output of the multiplier 516, and to the third input, the value (3-τ) ⁵ from the output of the block of raising to the fifth power 515. As a result of the operation of summation, the value 15 (1-τ) ⁵ + (3 -τ) ⁵ - 6 (2-τ) ⁵ . The latter is fed to the output 5.10 of block 5. The value of τ ⁵ from the output of the block of raising to the fifth power 55 through the delay element 525 goes to the output 5.12. The value (1-τ) ⁵ from the output of the block of raising to the fifth power 510 through the delay element 528 goes to the output 5.7 of block 5. Thus, the indicated values of the spline parameters are formed at the outputs 5.7, 5.8, 5.9, 5.10, 5.11 and 5.12 of block 5 simultaneously .

 Multipliers 51, 511-513, 516-518 can be implemented on the SN54284 and SN54285 microcircuits or on the ADSP1016 microcircuit.

 Adders 53, 54, 57, 58, 521-524 can be implemented on K155LP5, K155LI1, K155LE4 and NOT K155LN1.

 The principle of implementation of the converter into additional code 52 is known and described in the book of L.M. Goldenberg. Pulse and digital devices. M .: Communication, 1973, - p. 462 - 468. Can be implemented on chips K155LA3, K155LP5, K155LE4 and K155LN1.

 Delay elements 519, 520, 525-528 can be implemented on the K155IR13 chip in accordance with FIG. 6. For elements 519, 520, 526 and 527 n = 2. For elements 525 and 528 n = 4.

 Fifth degree blocks 55, 56, 59, 510, 514 and 515 can be implemented using multipliers, as shown in FIG. 7.

 The operation of the control unit 3 based on FIG. 4 is as follows.

 In the initial state, meander type pulses are fed to input 3.1 of control unit 3, input code 3.2 is the number code from the output of device counter 2, input 3.4 is the number 0 code from the installation bus 16, input 3.5 is the number 8 code from the installation bus 19 , input 3.6 is the code of the number 14 from the installation bus 20, input 3.7 is the code of the number 7 from the installation bus 21.

 At the beginning of the operation of the spline interpolator, a positive polarity pulse is supplied to input 3.2 of control unit 3. The latter is fed to the reset input of counter 35, as a result of which counter 35 is reset. In addition, the indicated pulse of positive polarity is fed to the control input of the counter 312, to the S-input of the RS-flip-flop 31 and the S-input of the RS-flip-flop 310. As a result, the value 31 is written to the counter 312. The RS-flip-flop 31 is set to a single state, when which at its output is formed by the level of logical "1". The latter is fed to the first input of the And 33 element, allowing the passage of clock pulses through it. At the inverse output of the RS flip-flop 310, a logic level of "0" is formed, which is fed to the first input of AND 311, closing the last.

 The code of the number 0 from the output of the counter 35 is supplied to the first group of inputs of the comparison unit 36. The code of the number 8 from the input 3.5 of the control unit 3 is supplied to the second group of inputs of the last one. As a result of the comparison operation, a signal with a zero level is formed at the output of the block 36, which covers the AND 34.

 In addition, the code of the number 0 from the output of the counter 35 is supplied to the first group of inputs of the comparison unit 38. The code of the number 14 from the input 3.6 of the control unit 3 is supplied to the second group of inputs of the last one. As a result of the save operation, a signal with a unit level is generated at the output of unit 38, opening element And 34.

 The pulses from the output of the element And 34 are received at the counting input of the counter 35, increasing each time its contents by one. In addition, the pulses from the output of the element And 34 go to the output 3.9 of the control unit 3. When the value of the contents of the counter 35 matches the number code supplied to the input 3.5 of the control unit 3, a signal with a unit level is formed at the output of the comparison unit 36. The latter opens the element And 37. The pulses from the output of the elements And 34 through the element And 37 are fed to the output 3.8 of the control unit 3.

 If the contents of the counter 35 coincide with the code of the number supplied to the input 3.6 of the control unit 3, a zero level is formed at the output of the comparison unit 38. The latter closes the And 34 element and through the NOT 39 element acts on the R-input of the RS flip-flop 310. As a result, a single level is formed at the inverse output of the RS flip-flop 310, opening the And 311 element. Pulses from the output of the And 33 element through the And 311 element go to the output 3.11 of the control unit 3, as well as the counting input of the counter 312. When the contents of the counter 312 matches the number code supplied to the input 3.7 of the control unit 3, a single pulse is generated at the output of the comparison unit 313. The latter is fed to the reset input of the counter 312, setting it to zero. In addition, a single pulse from the output of the comparison unit 313 through the delay element 314 is supplied to the output 3.10 of the control unit 3.

 At the moment when the code number 0 is received at the input 3.3 of the control unit 3 (which corresponds to zeroing the counter 2 of the device), a single pulse is generated at the output of the comparison unit 32. The latter enters the R-input of the RS-trigger 31, translating it into a zero state. At the same time, at the output of the RS flip-flop 31, a zero level is formed that covers the And 33 element and thereby prevents the passage of clock pulses through the And 33 element. At this, the operation of the control unit 3 (and the device as a whole) is completed.

The elements included in the structural diagram of the control unit 3 are known and described, for example, in the book of V.L. Awl. Popular digital circuits. Directory. - M .: Radio and communications, 1988. So, in the specified source describes the principles of construction and implementation examples
counters 35 and 312 on p. 85 - 86 (can be implemented on the K155IE5 chip);
elements And 33, 34, 38 and 311 on with. 35, fig. 1.19a (can be implemented on the K155LI1 chip);
element NOT 39 (can be implemented on the K155LN1 chip);
RS flip-flops 31 and 310 on p. 62 - 67 (can be implemented on the K155LE1 chip - p. 63, Fig. 1.42).

 In the book of V.L. Awl. Popular digital circuits. Directory. 2nd ed., Rev. , - Chelyabinsk: Metallurgy, 1989 describes the principle of operation of the delay element 314 on p. 181 - 187 (can be implemented on K564AG1 microcircuits, p. 285, Fig. 2.83a), and the procedure for pairing K564 with TTLs is described in the book: Digital Integrated Circuits: Reference Book / P.P. Maltsev, N.S. Dolidze et al. - M.: Radio and Communications, 1994, p. 101 - 103.

 The principle of operation of comparison blocks 32, 36, 38 and 313 is known and described in the book: Yu. V. Gavrilov, A.N. A bunch. Arithmetic devices of high-speed digital computers. - M .: Soviet Radio, 1970, p. 234 - 257. Can be implemented on K561IP2 microcircuits (VN Veniaminov, ON Lebedev, AI Miroshnichenko. Microcircuits and their application. Reference manual. 3rd ed. Revised and supplemented. - M.: Radio and Communications, 1989, p. 114, Fig. 4.12b).

Claims (4)

 1. A spline interpolator containing the first and second memory blocks, a counter, a control unit, the first, second, third and fourth multipliers, an adder and a register, wherein the counter information inputs and address inputs of the first memory block are combined and connected to the first installation bus the interpolator, and the counter outputs are connected to the third group of inputs of the control unit, the first input of which is the clock bus of the spline interpolator, the second input is the trigger bus of the spline interpolator, the tenth output is connected to the control input of the regis tra and a subtracting counter input, and the eighth output of the control unit is connected to the control input of the second memory unit, the first, second, third and fourth groups of outputs of which are connected respectively to the first inputs of the first, second, third and fourth multipliers, the outputs of which are connected respectively to the first, the second, third and fourth groups of information inputs of the adder, the outputs of which are connected to the information inputs of the register, the outputs of which are the outputs of the spline interpolator, characterized in that The fifth and sixth multipliers, the spline parameter generation unit and the spline coefficient generation unit, the first input of which is connected to the ninth output of the control unit, the fourth group of inputs of which is the second installation bus of the spline interpolator, the fifth group of inputs and the third installation bus of the spline interpolator, the sixth group of inputs is the fourth installation bus of the spline interpolator, the seventh group of inputs is the fifth installation bus of the spline interpolator, and the eleventh output of the control unit is connected with the sixth input of the spline parameter forming unit and the adder control input, the fifth and sixth groups of information inputs of which are connected respectively to the outputs of the fifth and sixth multipliers, the first groups of inputs of which are connected respectively to the fifth and sixth groups of outputs of the second memory block, the information inputs of which are connected to the ninth group of outputs of the block forming the spline coefficients, the second group of inputs of which is the sixth installation bus of the spline interpolator, the third group of inputs - with the seventh installation bus of the spline interpolator, the fourth group of inputs - the eighth installation bus of the spline interpolator, the fifth group of inputs - the information bus of the spline interpolator, the sixth group of inputs - the ninth installation bus of the spline interpolator, the seventh group of inputs - the tenth installation bus of the spline interpolator, and the eighth group of inputs is the eleventh installation bus of the spline interpolator, the twelfth installation bus of the spline interpolator is connected to the first group of inputs of the spline parameter generation unit, in The first group of inputs is the thirteenth installation bus of the spline interpolator, the third group of inputs is the fourteenth installation bus of the spline interpolator, the fourth group of inputs is connected to the outputs of the first memory block, the fifth group of inputs is connected to the outputs of the counter, the control input of which is combined with the second input of the control unit , seventh, eighth, ninth, tenth, eleventh and twelfth groups of outputs of the spline parameter forming unit are connected to second groups of inputs of the sixth, fifth, four respectively th, third, second and first multipliers.  2. The spline interpolator according to claim 1, characterized in that the spline coefficient generating unit is configured to comprise first, second, third, fourth, fifth, sixth and seventh multipliers, first, second, third, fourth, fifth, sixth, seventh and eighth delay elements, first, second and third adders, the first group of inputs of the first multiplier combined with the first groups of inputs of the second, third and fourth multipliers, groups of information inputs of the first, third and sixth delay elements, the first group of inputs of the second sum at the same time, it is the fifth group of inputs of the block forming the spline coefficients and information bus of the spline interpolator, the second group of inputs of the first multiplier is the second group of inputs of the block of forming the coefficients of spline and the sixth installation bus of the spline interpolator, and the outputs are connected to the information inputs of the second delay element whose input is combined with the control inputs of the first, third, fourth, fifth, sixth, seventh and eighth delay elements that control the input the first, the second and third adders and at the same time is the first input of the block forming the spline coefficients, and the outputs of the second delay element are connected to the second group of inputs of the first adder, the first group of inputs of which are connected to the outputs of the first delay element, the third group of inputs to the outputs of the third delay element and the outputs are connected to the first group of inputs of the fifth multiplier, the second group of inputs of which is the third group of inputs of the block forming the spline coefficients and the seventh installation th bus of the spline interpolator, and the outputs are connected to the information inputs of the seventh delay element, the outputs of which are connected to the first group of inputs of the third adder, the second group of inputs of which is connected to the outputs of the eighth delay element, the information inputs of which are combined with the third group of inputs of the second adder and the outputs of the fourth a delay element, the information inputs of which are connected to the outputs of the third multiplier, the second group of inputs of which is the fourth group of inputs of the block forming coe spline factors and the eighth installation bus of the spline interpolator, the second group of inputs of the fourth multiplier is combined with the second group of inputs of the second multiplier and is the sixth group of inputs of the block forming the spline coefficients and the ninth installation bus of the spline interpolator, and the outputs of the fourth multiplier are connected to the information inputs of the fifth delay element the outputs of which are connected to the fourth group of inputs of the second adder, the second group of inputs of which is connected to the outputs of the second multiplier, fifth the input group is with the outputs of the sixth delay element, and the outputs are connected to the first group of inputs of the sixth multiplier, the second group of inputs of which is the seventh group of inputs of the block forming the spline coefficients and the tenth installation bus of the spline interpolator, and the outputs are connected to the third group of inputs of the third adder, the outputs which are connected to the first group of inputs of the seventh multiplier, the second group of inputs of which is the eighth group of inputs of the block forming the spline coefficients and the eleventh installation a spline interpolator, and outputs the ninth group are forming unit outputs spline coefficients.  3. The spline interpolator according to claim 1, characterized in that the spline parameter generating unit is configured to comprise first, second, third, fourth, fifth, sixth and seventh multipliers, a converter to an additional code, first, second, third, fourth, fifth, sixth, seventh and eighth adders, first, second, third, fourth, fifth and sixth delay elements, first, second, third, fourth, fifth and sixth erection blocks to the fifth degree, the first group of inputs of the first multiplier being the fifth group of inputs of the forming unit steam spline meters, the second group of inputs is the fourth group of inputs of the spline parameter forming unit, and the outputs are connected to the inputs of the converter in an additional code, the first group of inputs of the first adder and the inputs of the first block of raising to the fifth degree, the outputs of which are connected to the information inputs of the third delay element, the first the group of inputs of the second multiplier and the first group of inputs of the third multiplier, the second group of inputs of which is combined with the second group of inputs of the fourth, fifth and sixth multipliers and is the second group of inputs of the spline parameter forming unit and the thirteenth installation bus of the spline interpolator, and the outputs are connected to the first group of inputs of the fifth adder, the second group of inputs of which is combined with the first group of inputs of the fourth multiplier and the outputs of the second block of raising to the fifth degree, and the outputs of the fifth adder connected to the information inputs of the fourth delay element, the outputs of which are the eleventh group of outputs of the spline parameter forming unit, and the control input is combined with control inputs of the first, second, third, fifth and sixth delay elements and the first, second, third, fourth, fifth, sixth, seventh and eighth adders and is the sixth input of the spline parameter forming unit, the second group of inputs of the second multiplier is combined with the second group of inputs of the seventh multiplier and is the first group of inputs of the spline parameter forming unit and the twelfth installation bus of the spline interpolator, and the outputs are connected to the information inputs of the first delay element, the output which is connected to the first group of inputs of the sixth adder, the second group of inputs of which is connected to the outputs of the fourth multiplier, and the outputs are the tenth group of outputs of the spline parameter forming unit, the second group of inputs of the first adder is combined with the second groups of inputs of the second, third, and fourth adders and is the third the group of inputs of the spline parameter forming unit and the fourteenth installation bus of the spline interpolator, and the outputs of the first adder are connected to the inputs of the second block In the fifth degree and the first group of inputs of the third adder, the outputs of which are connected to the inputs of the fifth block of raising to the fifth degree, the outputs of which are connected to the third group of inputs of the sixth adder, the outputs of the converter into an additional code are connected to the inputs of the fourth block of raising to the fifth degree and the first group the inputs of the second adder, the outputs of which are connected to the inputs of the third block raising to the fifth degree and the first group of inputs of the fourth adder, the outputs of which are connected to the inputs of the sixth block fifth degree, the outputs of which are connected to the first group of inputs of the seventh adder, the second group of inputs of which is connected to the outputs of the fifth multiplier, the first group of inputs of which is connected to the outputs of the third block of raising to the fifth degree and the first group of inputs of the eighth adder, the second group of inputs of which is connected with the outputs of the sixth multiplier, and the outputs are connected to the information inputs of the fifth delay element, the outputs of which are the eighth group of outputs of the spline parameter forming unit, the outputs are the fourth block of raising to the fifth degree are connected to the first group of inputs of the sixth multiplier, the first group of inputs of the seventh multiplier and the information inputs of the sixth delay element, the outputs of which are the seventh group of outputs of the block forming the spline parameters, the outputs of the seventh multiplier are connected to the information inputs of the second delay element, the outputs of which connected to the third group of inputs of the seventh adder, the outputs of which are the ninth group of outputs of the spline parameter forming unit, and the output The third delay element is the twelfth group of outputs of the spline parameter forming unit.  4. The spline interpolator according to claim 1, characterized in that the control unit is made comprising first and second RS flip-flops, first, second, third and fourth elements And, first and second counters, first, second, third and fourth comparison blocks, a delay element and an element NOT, wherein the first group of inputs of the first comparison unit is the third group of inputs of the control unit, the second group of inputs is combined with the information inputs of the second counter and is the fourth group of inputs of the control unit and the second installation bus spline interpo a radiator, and the output is connected to the R-input of the first RS-trigger, the S-input of which is combined with the reset input of the first counter, controlling the input of the second counter, the S-input of the second RS-trigger and at the same time is the second input of the control unit and the trigger bus of the spline interpolator and the output of the first RS-trigger is connected to the first input of the first element And, the second input of which is the first input of the control unit and the clock bus of the spline interpolator, and the output is connected to the second input of the fourth element And and the first input of the second element And, the output is This is the ninth output of the control unit and is simultaneously connected to the first input of the third AND element and the counting input of the first counter, the outputs of which are connected to the first group of inputs of the second comparison unit and the first group of inputs of the third comparison unit, the second group of inputs of which is the sixth group of inputs of the control unit and the fourth installation bus of the spline interpolator, and the output is connected to the second input of the second AND element and the input of the element NOT, the output of which is connected to the R-input of the second RS-trigger, inverse output which is connected to the first input of the fourth element And, the output of which is the eleventh output of the control unit and simultaneously connected to the counting input of the second counter, the outputs of which are connected to the first group of inputs of the fourth comparison unit, the second group of inputs of which is the seventh group of inputs of the control unit and the fifth installation bus spline interpolator, and the output is connected to the reset input of the second counter and the input of the delay element, the output of which is the tenth output of the control unit, the second group odov second block comparisons is the fifth group of control inputs of the third block and the mounting rail spline interpolator and an output coupled to a second input of the third AND gate, whose output is the output of the eighth control unit.

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