RU2127903C1 - Interpolator - Google Patents

Abstract

FIELD: computer engineering, in particular, models of non-linear functions of one variable. SUBSTANCE: device has clock bus, starting bus, information bus, setting buses, counter, memory unit, information bus, converter to additional code, commutator, multipliers, registers, delay gates, adders, fifth power raising units, control unit, which has RS flip-flop, counter, comparison gates, AND gates. EFFECT: increased precision of interpolation for functions of continuous seventh derivative. 2 cl, 2 dwg

Description

 The invention relates to computing, in particular to devices for implementing functions, and can be used to reproduce nonlinear dependencies of one variable.

 Known devices (USSR AS N 1405074 G 06 F 15/353 of 10/27/1986, USSR AS N 1686461 G 06 F 15/353 of 02/13/1989) allow reproducing a wide class of functional dependencies, but have low accuracy.

 Closest to the claimed device in its technical essence is the "Interpolator" (USSR AS N 1405074 G 06 F 13/353 of 10/27/1986), selected as the prototype device.

 The prototype device contains an accumulating adder, a multiplier, a first and second memory unit, a switch, an additional code converter, a counter and a register, the output of which is connected to the first information input of the switch, the output of the first bit of the register connected to the control input of the switch, the second information input of which connected to the output of the converter into an additional code, the input of which is connected to the output of the register, the information input of which is the input of the least significant bits of the interpolator argument, One of the senior bits of which is connected to the input of the initial value of the counter, the output of which is connected to the address input of the first memory block, the output of the multiplier is connected to the information input of the accumulating adder, the output of which is the output of the interpolator, the inputs of entering the counter and register data and the reset input of the accumulating adder are connected to the input of the initial installation of the interpolator, the counting input of the counter and the synchronization input of the accumulating adder are connected to the input of the clock of the interpolator, the output of the second of the second memory block is connected to the input of the first multiplier of the multiplier, the input of the second factor of which is connected to the output of the first memory block, to the output of the switch is connected to the address input of the second memory block.

где

- максимум третьей производной функции f(X);
h - расстояние между отсчетами функции f(X).The known technical solution has insufficient interpolation accuracy, which is characterized by an interpolation error equal to

Where

- the maximum of the third derivative of the function f (X);
h is the distance between the samples of the function f (X).

Moreover, this accuracy is ensured for functions having a continuous third derivative (f (X) ∈ C ³ ). . When interpolating functions having a continuous seventh derivative (f (X) ∈ C ⁷ ), information about the smoothness of functions is not fully taken into account, as a result of which the prototype provides low accuracy of interpolation.

The aim of the invention is to develop a device that provides higher accuracy of interpolation of functions having a continuous seventh derivative (f (X) ∈ C ⁷ ).
This goal is achieved by the fact that in the known interpolator containing the first and second register, the first multiplier, switch, control unit, converter into an additional code, the first adder, memory unit and counter, moreover, the information inputs of the counter are connected to the information bus of the interpolator, the control input is combined with the input of resetting the first register and the first output of the control unit, the first input of the control unit is connected to the clock bus of the interpolator, the second input is connected to the start bus of the interpolator, and the second output is it is single with the control input of the first register, the outputs of the first register are the output bus of the interpolator, and the information inputs are connected to the outputs of the first adder, the first group of information inputs of the first adder is connected to the outputs of the first multiplier, and the address inputs of the memory block are connected to the outputs of the counter, the second third, fourth, fifth, sixth, seventh and eighth and ninth adders, third, fourth, fifth, sixth and seventh registers, first, second, third, fourth, fifth and sixth blocks SIC to the fifth power, the first, second, third, fourth, fifth and sixth delay elements, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh and twelfth multipliers. The inputs of the converter into the additional code are combined with the information inputs of the counter, the inputs of the first block raising to the fifth degree and the first group of inputs of the second adder, and the outputs are connected to the inputs of the fourth block raising to the fifth degree and the first group of inputs of the third adder. The second group of inputs of the third adder is combined with the fifth installation bus of the interpolator, the second group of inputs of the second, fourth and fifth adders. The first group of inputs of the fifth adder is connected to the outputs of the third adder and the inputs of the third block raising to the fifth degree, and the outputs are connected to the inputs of the sixth block raising to the fifth degree. The outputs of the sixth block raising to the fifth degree are connected to the third group of information inputs of the eighth adder. The second group of information inputs of the eighth adder is connected to the outputs of the tenth multiplier. The second group of inputs of the tenth multiplier is combined with the second groups of inputs of the eighth, ninth and eleventh multipliers and connected to the fourth installation bus of the interpolator. The first group of inputs of the tenth multiplier is connected to the outputs of the third block of raising to the fifth degree and the second group of information inputs of the ninth adder. The first group of inputs of the ninth adder is connected to the outputs of the eleventh multiplier, the first group of inputs of which is connected to the outputs of the fourth block of raising to the fifth degree, the information inputs of the sixth delay element and the first group of inputs of the twelfth multiplier. The second group of inputs of the twelfth multiplier is combined with the second group of inputs of the seventh multiplier and the third installation bus of the interpolator, and the outputs are connected to the information inputs of the second delay element. The outputs of the second delay element are connected to the first group of information inputs of the eighth adder. The outputs of the eighth adder are connected to the first group of inputs of the fourth multiplier, the second group of inputs of which are connected to the outputs of the fifth register, and the outputs to the fourth group of information inputs of the first adder. The fifth group of information inputs of the first adder is connected to the outputs of the fifth multiplier. The second group of inputs of the fifth multiplier is connected to the outputs of the sixth register, and the first group of inputs is connected to the outputs of the fifth delay element. The information inputs of the fifth delay element are connected to the outputs of the ninth adder. The control input of the ninth adder is connected to the fourth output of the control unit and the control inputs of the first, second, third, fourth, fifth, sixth, seventh and eighth adders, the first, second, third, fourth, fifth and sixth delay elements. The outputs of the sixth delay element are connected to the first group of inputs of the sixth multiplier. The second group of inputs of the sixth multiplier is connected to the outputs of the seventh register, and the outputs are connected to the sixth group of information inputs of the first adder. The third group of information inputs of the first adder is connected to the outputs of the third multiplier. The second group of inputs of the third multiplier is connected to the outputs of the fourth register, and the first group of inputs is connected to the outputs of the seventh adder. The third group of information inputs of the seventh adder is connected to the outputs of the fifth block of raising to the fifth degree, the inputs of which are connected to the outputs of the fourth adder. The first group of information inputs of the fourth adder is connected to the outputs of the second adder and the inputs of the second block of raising to the fifth degree, the outputs of which are connected to the second group of inputs of the sixth adder and the first group of inputs of the ninth multiplier. The outputs of the ninth multiplier are connected to the second group of information inputs of the seventh adder, the first group of information inputs of which are connected to the outputs of the first delay element. The information inputs of the first delay element are connected to the outputs of the seventh multiplier. The first group of inputs of the seventh multiplier is combined with the information inputs of the third delay element, the outputs of the first block raising to the fifth degree and the first group of inputs of the eighth multiplier. The outputs of the eighth multiplier are connected to the first group of information inputs of the sixth adder. The outputs of the sixth adder are connected to the information inputs of the fourth delay element, the outputs of which are connected to the first group of inputs of the second multiplier. The outputs of the second multiplier are connected to the second group of information inputs of the first adder, and the second group of inputs to the outputs of the third register. The control input of the third register is combined with the control inputs of the second, fourth, fifth, sixth and seventh registers, an even counter input and the fifth output of the control unit. The third group of inputs of the control unit is the first installation bus of the interpolator, the fourth group of inputs is the second installation bus of the interpolator, and the third group of outputs is connected to the control inputs of the switch. The information inputs of the switch are connected to the outputs of the memory block. The first, second, third, fourth, fifth and sixth groups of outputs of the control unit are connected respectively to the information inputs of the seventh, sixth, fifth, fourth, third and second registers. The first group of inputs of the first multiplier is connected to the outputs of the third delay element, and the second group of inputs is connected to the outputs of the second register.

 The control unit includes an RS-trigger, a counter, the first and second comparison units, the first and second elements I. The first input of the first element And is connected to the output of the RS-trigger, the second input is the first input of the control unit and the interpolator clock bus, and the output is the fourth output control unit and is connected to the second input of the second element And and the counting input of the counter. The counter zeroing input is combined with the S-input of the RS-trigger and is the first output of the control unit and at the same time the second input of the control unit and the interpolator bus, and the outputs are the third group of outputs of the control unit and are simultaneously connected to the first group of inputs of the second comparison unit and the first group of inputs of the first block comparison. The second group of inputs of the first comparison unit is the third group of inputs of the control unit and the first installation bus of the interpolator, and the output is connected to the R-input of the RS-flip-flop and at the same time is the second output of the control unit. The second group of inputs of the second comparison unit is the fourth group of inputs of the control unit and the second installation bus of the interpolator. The output of the second comparison unit is connected to the first input of the second AND element, the output of which is the fifth output of the control unit.

The listed new set of essential features of the claimed device provides a higher accuracy of interpolation of functions having a continuous seventh derivative (f (X) ∈ C ⁷ ). This is achieved by the fact that the interpolation is carried out more accurately based on a priori information about the degree of smoothness of the function.

The claimed device is illustrated by drawings:
in FIG. 1 is a structural diagram of the claimed device;
in FIG. 2 is an embodiment of a delay element.

 The interpolator shown in FIG. 1, consists of the first 52, second 39, third 40, fourth 41, fifth 42, sixth 43 and seventh 44 registers, the first 45, second 46, third 47, fourth 48, fifth 49, sixth 50, seventh 21, eighth 22, ninth 23, tenth 26, eleventh 27 and twelfth 28 multipliers, switch 11, control unit 53, converter to additional code 12, first 51, second 13, third 14, fourth 17, fifth 18, sixth 31, seventh 32, eighth 33 and ninth 34 adders, memory block 10, counter 9, first 15, second 16, third 19, fourth 20, fifth 24 and sixth 25 blocks reduction to the fifth degree, first 29, second 30, third 35, fourth 36, fifth 37 and sixth 38 delay elements, clock bus 1, start bus 2, information bus 3, first 7, second 8, third 4, fourth 5 and sixth 6 mounting tires. The information inputs of the counter 9 are connected to the information bus 3 of the interpolator, the control input is combined with the zeroing input of the first register 52 and the first output of the control unit 53. The first input of the control unit 53 is connected to the clock bus 1 of the interpolator, the second input to the start bus 2 of the interpolator, and the second the output is connected to the control input of the first register 52. The outputs of the first register 52 are the output bus of the interpolator, and the information inputs are connected to the outputs of the first adder 51. The first group of information inputs of the first the adder 51 is connected to the outputs of the first multiplier 45, and the address inputs of the memory block 10 are connected to the outputs of the counter 9. The inputs of the Converter in additional code 12 are combined with the information inputs of the counter 9, the inputs of the first block raising to the fifth power 15 and the first group of inputs of the second adder 13, and the outputs are connected to the inputs of the fourth block of raising to the fifth degree 20 and the first group of inputs of the third adder 14. The second group of inputs of the third adder 14 is combined with the fifth installation bus 6 of the interpolator, the second group the inputs of the second 13, fourth 17 and fifth 18 adders. The first group of inputs of the fifth adder 18 is connected to the outputs of the third adder 14 and the inputs of the third block of raising to the fifth degree 19, and the outputs are connected to the inputs of the sixth block of raising to the fifth degree 25. The outputs of the sixth block of raising to the fifth degree 25 are connected to the third group of information inputs of the eighth the adder 33. The second group of information inputs of the eighth adder 33 is connected to the outputs of the tenth multiplier 25. The second group of inputs of the tenth multiplier 25 is combined with the second groups of inputs of the eighth 22, ninth 23 and od of the seventeenth 27 multipliers and connected to the fourth installation bus 5 of the interpolator. The first group of inputs of the tenth multiplier 26 is connected to the outputs of the third fifth raising block 19 and the second group of information inputs of the ninth adder 34. The first group of inputs of the ninth adder 34 is connected to the outputs of the eleventh multiplier 27, the first group of inputs of which is connected to the outputs of the fourth fifth raising block degree 20, the information inputs of the sixth delay element 38 and the first group of inputs of the twelfth multiplier 28. The second group of inputs of the twelfth multiplier 28 is combined with the second group in the odes of the seventh multiplier 21 and the third interpolator installation bus 4, and the outputs are connected to the information inputs of the second delay element 30. The outputs of the second delay element 30 are connected to the first group of information inputs of the eighth adder 33. The outputs of the eighth adder 33 are connected to the first group of inputs of the fourth multiplier 48, the second group of inputs of which is connected to the outputs of the fifth register 42, and the outputs with the fourth group of information inputs of the first adder 51. The fifth group of information outputs of the first adder 51 connected to the outputs of the fifth multiplier 49. The second group of inputs of the fifth multiplier 49 is connected to the outputs of the sixth register 43, and the first group of inputs is connected to the outputs of the fifth delay element 37. The information inputs of the fifth delay element 37 are connected to the outputs of the ninth adder 34. The control input of the ninth adder 34 connected to the fourth output of the control unit 53 and the control inputs of the first 51, second 13, third 14, fourth 17, fifth 18, sixth 31, seventh 32 and eighth 33 adders, first 29, second 30, third 35, fourth 36, fifth 37 a sixth delay elements 38. The outputs of the sixth delay element 38 are connected to the first group of inputs of the sixth multiplier. 50. The second group of inputs of the sixth multiplier 50 is connected to the outputs of the seventh register 44, and the outputs are connected to the sixth group of information inputs of the first adder 51. The third group of information inputs of the first adder 51 is connected to the outputs of the third multiplier 47. The second group of inputs of the third multiplier 47 is connected to the outputs the fourth register 41, and the first group of inputs with the outputs of the seventh adder 32. The third group of information inputs of the seventh adder 32 is connected to the outputs of the fifth block of raising to the fifth power 24, whose inputs are connected are connected to the outputs of the fourth adder 17. The first group of information inputs of the fourth adder 17 is connected to the outputs of the second adder 13 and the inputs of the second block of raising to the fifth power 16, the outputs of which are connected to the second group of inputs of the sixth adder 31 and the first group of inputs of the ninth multiplier 23. Outputs of the ninth the multiplier 23 is connected to the second group of information inputs of the seventh adder 32, the first group of information inputs of which are connected to the outputs of the first delay element 29. Information inputs of the first delay elements 29 are connected to the outputs of the seventh multiplier 21. The first group of inputs of the seventh multiplier 21 is combined with the information inputs of the third delay element 35, the outputs of the first fifth raising block 15 and the first group of inputs of the eighth multiplier 22. The outputs of the eighth multiplier 22 are connected to the first group of information the inputs of the sixth adder 31. The outputs of the sixth adder 31 are connected to the information inputs of the fourth delay element 36, the outputs of which are connected to the first group of the second multiplier 46. The outputs to the second multiplier 46 is connected to the second group of information inputs of the first adder 51, and the second group of inputs to the outputs of the third register 40. The control input of the third register 40 is combined with the control inputs of the second 39, fourth 41, fifth 42, sixth 43 and seventh 44 registers, countable the counter input 9 and the fifth output of the control unit 53. The third group of inputs of the control unit 53 is the first interpolator installation bus 7, the fourth group of inputs is the second interpolator installation bus 8, and the third group of outputs is connected to the control inputs of the switch 11. The information inputs of the switch 11 are connected to the outputs of the memory unit 10. The first, second, third, fourth, fifth, sixth groups of outputs of the control unit 53 are connected respectively to the information inputs of the seventh 44, sixth 43 fifth fifth 42, fourth 41, third 40 and second 39 registers. The first group of inputs of the first multiplier 45 is connected to the outputs of the third delay element 35, and the second group of inputs is connected to the outputs of the second register 39.

 An embodiment of the control unit 53 shown in FIG. 1, consists of an RS trigger 531, a counter 532, a first 533 and a second 536 comparison blocks, a first 534 and a second 535 elements I. The first input of the first element And 534 is connected to the output of the RS trigger 531, the second input is the first input of the control unit 53 and clock bus 1 of the interpolator, and the output is the fourth output of the control unit 53 and is connected to the second input of the second element And 535 and the counting input of the counter 532. The zeroing input of the counter 532 is combined with the S-input of the RS flip-flop 531 and is the first output of the control unit 53 and at the same time, the second input of the control unit 53 and the trigger bus 2 of the interpolator, and the outputs are the third group of outputs of the control unit 53 and are simultaneously connected to the first group of inputs of the second comparison unit 536 and the first group of inputs of the first comparison unit 533. The second group of inputs of the first comparison unit 533 is the third group of inputs of the control unit 53 and the first installation bus 7 of the interpolator, and the output is connected to the R-input of the RS-flip-flop 531 and at the same time is the second output of the control unit 53. The second group of inputs of the second comparison unit 536 is the fourth group sing inputs of the control unit 53 and the second installation bus 8 of the interpolator. The output of the second comparison unit 536 is connected to the first input of the second AND element 535, the output of which is the fifth output of the control unit 53.

где h - шаг между отсчетами функции f(x);
b $\genfrac{}{}{0ex}{}{\text{m}}{\text{h}}$ - - В-сплайн степени m-1:

C $\genfrac{}{}{0ex}{}{\text{m}}{\text{i}}$ - - число сочетаний из m по i:

X = h(N+τ),τ ∈[0,1].
Для сплайна пятой степени m= 6, s=0 коэффициент g $\genfrac{}{}{0ex}{}{\text{m+s}}{\text{n}}$ в выражении (2) вычисляется по формуле

Из (3) можно получить

Из статей: Желудев В.А. Локальная сплайн-аппроксимация на равномерной сетке// Журнал вычислительной математики и математической физики. - 1987. - Том 27. - N 9. - С. 1296-1310 и Желудев В.А. Восстановление функций и их производных по сеточным данным с погрешностью при помощи локальных сплайнов// Журнал вычислительной математики и математической физики. - 1987. - Том 27. - N 1 - С. 22-34 известно, что значение В-сплайна b $\genfrac{}{}{0ex}{}{\text{6}}{\text{h}}$ (x) отлично от нуля на участке (0, 6h) и на различных интервалах наблюдения определяется слудующим образом:

Учитывая, что носитель В-сплайна supp b $\genfrac{}{}{0ex}{}{\text{6}}{\text{h}}$ (x) = (0,6h) и b⁶(X) симметричен относительно точки h•m/2 (за τ можно принять (1-τ)), получим для интервалов

Тогда из выражения (2)

где g_n определяется из (4).The implementation of the claimed device is explained as follows. From the articles: Zheludev V.A. Local spline approximation on a uniform grid // Journal of Computational Mathematics and Mathematical Physics. - 1987. - Volume 27. - N 9. - S. 1296-1310 and Zheludev V.A. Recovery of functions and their derivatives from grid data with an error using local splines // Journal of Computational Mathematics and Mathematical Physics. - 1987. - Volume 27. - N 1 - S. 22-34 it is known that the expression for calculating the s-th derivative of a spline can be written:

where h is the step between the samples of the function f (x);
b $\genfrac{}{}{0ex}{}{\text{m}}{\text{h}}$ - - B-spline of degree m-1:

C $\genfrac{}{}{0ex}{}{\text{m}}{\text{i}}$ - - the number of combinations from m to i:

X = h (N + τ), τ ∈ [0,1].
For a fifth spline, m = 6, s = 0, the coefficient g $\genfrac{}{}{0ex}{}{\text{m + s}}{\text{n}}$ in expression (2) is calculated by the formula

From (3) we can obtain

From the articles: Zheludev V.A. Local spline approximation on a uniform grid // Journal of Computational Mathematics and Mathematical Physics. - 1987. - Volume 27. - N 9. - S. 1296-1310 and Zheludev V.A. Recovery of functions and their derivatives from grid data with an error using local splines // Journal of Computational Mathematics and Mathematical Physics. - 1987. - Volume 27. - N 1 - S. 22-34 it is known that the value of the B-spline b $\genfrac{}{}{0ex}{}{\text{6}}{\text{h}}$ (x) is nonzero in the interval (0, 6h) and at different observation intervals is determined as follows:

Given that the support of the B-spline supp b $\genfrac{}{}{0ex}{}{\text{6}}{\text{h}}$ (x) = (0.6h) and b ⁶ (X) is symmetric with respect to the point h • m / 2 (for τ we can take (1-τ)), we obtain for the intervals

Then from the expression (2)

where g _n is determined from (4).

Точность же устройства-прототипа не лучше

Поэтому, например, для функций f(X)∈ C⁷ при h = 0.1 и в случае f $\genfrac{}{}{0ex}{}{\text{(3)}}{\text{max}}$ ≈ f $\genfrac{}{}{0ex}{}{\text{(6)}}{\text{max}}$ выигрыш β = μ₁/μ₂ может достигать свыше тысячи.Implementation of (5) in the form of a device allows one to calculate functions f (X) ∈ C ⁷ with an accuracy determined by the error (Zheludev V.A. Restoration of functions and their derivatives from grid data with an error using local splines // Journal of Computational Mathematics and Mathematical Physics . - 1987. - Volume 27. - N 1. - p. 24)

The accuracy of the prototype device is no better.

Therefore, for example, for functions f (X) ∈ C ⁷ for h = 0.1 and in the case f $\genfrac{}{}{0ex}{}{\text{(3)}}{\text{max}}$ ≈ f $\genfrac{}{}{0ex}{}{\text{(6)}}{\text{max}}$ the gain β = μ ₁ / μ ₂ can reach over a thousand.

Работа интерполятора на основе выражения (6) и фиг. 1 осуществляется следующим образом.Let X _i be the number formed by K high order bits of the argument X, where 2 ≤ K ≤ m-1; m is the length of the binary code of the number X. The number X _i represents the number of the nodal point. Let ΔX be the number formed by mK the least significant bits of the argument so that X = X _i + ΔX • 2 ^-K , 0≤ΔX≤1. . Then, according to formula (5) for interpolation by splines of the minimum template, we have:

The operation of the interpolator based on expression (6) and FIG. 1 is carried out as follows.

Before starting work, values (1/120) g _n-2 (1/120) • g _n-1 , (1/120) • g _n , (1/120) • g _{n + 1} , ( 1/120) • g _{n + 2} , (1/120) g _{n + 3} with an address shift so that the jth value of the address code corresponds to the value (1/120) • g _i-3 .

 In the initial state, meander pulses are sent to the clock bus 1, the code of the number 6 is present on the second installation bus 8, and the code is the code of 8. The variable X code is sent to the interpolator information bus 3. The code of the third installation bus 4 is the code 15, on the fourth installation bus 5 - the code of the number is 6, on the fifth installation bus 6 - the code of the number 1.

When a positive polarity pulse is applied to the trigger bus 2, the first register 52 is reset, and the high-order code of variable X is written to counter 9 — the value of X _i . At the same time, counter 532 is reset to zero, and the RS flip-flop 531 is set to a single state, at which the logical level “1” is formed at its output. The latter is fed to the first input of the first element And 534, allowing the passage of clock pulses through it. In addition, the code of the number 0 from the output of the counter 532 goes to the first group of inputs of the second comparison unit 536. The code of the number 6 from the second installation bus 8 is received to another group of its inputs. As a result of the comparison operation, a signal with a unit level is generated at the output of block 536.

Clock pulses from the output of the first element And 534 are fed to the counting input of the counter 9 through the second element And 535 (the latter is opened by a unit level supplied to its input from the output of the second comparison unit 536). In this case, the contents of the counter 9 increases each time by one. So, as a result of the influence of the first clock pulse, the contents of the counter 9 takes the value X _i +1. The latter arrives at the address inputs of memory block 10, determining the number of the cell whose contents are (1/120) • g $\genfrac{}{}{0ex}{}{\text{4}}{\text{n-2}}$ fed to the input of the switch 11. Due to the fact that the control inputs of the switch 11 receives the code number 1 from the outputs of the counter 532, the value (1/120) • g $\genfrac{}{}{0ex}{}{\text{4}}{\text{n-2}}$ written in the seventh register 44.

Further, in the same way, in the sixth 43, fifth 42, fourth 41, third 40 and second 39 registers, values are written respectively (1/120) • g _n-1 , (1/120) • g _n , (1/120) • g _{n +1} , (1/120) • g _{n + 2} , (1/120) • g _{n + 3} . Upon completion of recording in the second register 39, the contents of the counter 532 coincides with the number code supplied to the second installation bus 8. As a result, a signal with a zero level is formed at the output of the second comparison unit 536, closing the second AND element 535 and causing the counter 9 to stop.

At the same time, during the above-described clock cycles of the device, the value ΔX (the least significant bits of the code of the variable X) is supplied to the input of the converter in additional code 12, the output of which has the value (1-ΔX). . The value ΔX is also supplied to the first group of inputs of the second adder 13, and to the first group of inputs of the third adder 14, the value (1-ΔX). The second group of inputs of the second 13 and third adders is supplied with a code of number 1. Under the influence of clock pulses from the output of the first element And 534 to the control inputs of which 13 and third 14 adders, the values are formed at the outputs of the second 13 and third 14 adders (1+ ΔX) and (2-ΔX). The latter are fed to the first groups of inputs of the fourth 17 and fifth 18 adders, respectively. A code of the number 1 is supplied to the second groups of inputs of the latter. As a result of the action of clock pulses from the output of the first element And 534 to the control inputs of the fourth 17 and fifth 18 adders, the values of (ΔX + 2) and (3-ΔX) are formed at the outputs of the latter . The indicated values are supplied to the inputs of the fifth 24th and sixth 25th blocks of raising to the fifth degree, respectively. At the inputs of the first block raising to the fifth power 15, the value ΔX is received from the information bus 3. At the inputs of the second block raising to the fifth power 16, there is a value (ΔX + 1) supplied from the outputs of the second adder 13. The inputs of the third block raising to the fifth power 19 the value (2-ΔX) from the outputs of the third adder 14. The inputs of the fourth block of raising to the fifth power of 20 are affected by the value (1-ΔX) generated at the outputs of the converter into additional code 12. At the outputs of the first 15, second 16, fifth 24, sixth 25, third 19 and four 20 of the construction blocks to the fifth power, respectively have values ΔX ^5, (ΔX + 1) ^5, (ΔX + 2) ^5, (3-ΔX) ^5, (2-ΔX) and ⁵ (1-ΔX) ^5. The value of ΔX ⁵ from the outputs of the first block raising to the fifth degree 15 is supplied to the first inputs of the seventh 21 and eighth 22 multipliers. The second inputs of the seventh multiplier 21 are supplied with the code of the number 15 from the third installation bus 4, and the inputs of the eighth multiplier 22 are supplied with the code of the number 6 from the fourth installation bus 5. As a result of the multiplication operation, the values of 15ΔX are generated at the outputs of the seventh 21 and eighth 22 multipliers ⁵ and -6ΔX ⁵ . The values (ΔX + 1) ⁵ and (2-ΔX) ⁵ are supplied to the first inputs of the ninth 23 and tenth 26 multipliers, respectively. The second inputs of these multipliers are supplied with the number code - 6 from the fourth installation bus 5. As a result of the multiplication operation, the outputs of the ninth 23 and tenth 26 multipliers produce values of -6 (ΔX + 1) ⁵ and -6 (2-ΔX) ^5, respectively. The value of (1-ΔX) ⁵ from the outputs of the fourth erection to the fifth power of 20 enters the first groups of inputs of the eleventh 27 and twelfth 28 multipliers. The second inputs of the eleventh multiplier 27 are supplied with the code of the number 6 from the fourth installation bus 5, and the second inputs of the twelfth multiplier 28 with the code of the number 15 from the third installation bus 4. As a result of the multiplication operation, the values of the eleventh 27 and twelfth 28 multipliers are generated, respectively -6 (1-ΔX) ⁵ and 15 (1-ΔX) ⁵ . From the outputs of the eighth multiplier 22, a value of -6ΔX ^{5 is} supplied to the first group of inputs of the sixth adder 31. At the same time, the second group of inputs of the sixth adder 31 receives the value (ΔX + 1) ⁵ from the output of the second block of raising to the fifth power 16. As a result of the action of clock pulses supplied to the control input of the sixth adder 31 from the output of the first AND element 534, at the outputs of the sixth adder 31, the value (ΔX + 1) ⁵ -6ΔX ^{5 is} generated. The latter, through the fourth delay element 36, is supplied to the first group of inputs of the second multiplier 46. The value 15ΔX ⁵ from the outputs of the seventh multiplier 21 is fed through the first delay element 29 to the first group of inputs of the seventh adder 32. At the same time, the value -6 (ΔX + 1) ⁵ from the outputs of the ninth multiplier 23, and to the third group of inputs, the value (ΔX + 2) ⁵ from the outputs of the fifth block of raising to the fifth power 24. As a result, under the influence of clock pulses supplied to the control input of the seventh adder 32 s output and the first element And 534, at the outputs of the seventh adder 32, a value of 15ΔX ⁵ + (ΔX + 2) ⁵ -6 (ΔX + 1) ^{5 is formed} . The latter is fed to the first group of inputs of the third multiplier 47. From the outputs of the eleventh multiplier 27, the value -6 (1-ΔX) ^{5 is} supplied to the first group of inputs of the adder of the ninth 34. At the same time, the second group of inputs of the ninth adder 34 receives the value (2-ΔX) ⁵ from the outputs of the third block of raising to the fifth power 19. As a result, under the influence of clock pulses supplied to the control input of the ninth adder 34 from the output of the first element And 534, at the outputs of the ninth the adder 34 is formed the value of (2-ΔX) ⁵ -6 (1-ΔX) ⁵ . The latter, through the fifth delay element 37, is supplied to the first group of inputs of the fifth multiplier 49. The value 15 (1-ΔX) ⁵ from the outputs of the twelfth multiplier 28 is fed through the second delay element 30 to the first group of inputs of the eighth adder 33. At the same time, the value is supplied to the second group of inputs of the last -6 (2-ΔX) ⁵ from the outputs of the tenth multiplier 26, and to the third group of inputs, the value (3-ΔX) ⁵ from the outputs of the sixth block raising to the fifth power 25. As a result, under the influence of clock pulses supplied to the control input of the eighth adder 33 out ode of the first element And 534, at the outputs of the eighth adder 33, a value of 15 (1-ΔX) ⁵ + (3-ΔX) ⁵ -6 (2-ΔX) ^{5 is formed} . The latter is fed to the first group of inputs of the fourth multiplier 48. The value of ΔX ⁵ from the outputs of the first block raising to the fifth power 15 through the third delay element 35 goes to the first group of inputs of the first multiplier 45. The value (1-ΔX) ⁵ from the outputs of the fourth block of raising to the fifth degree 20 through the sixth delay element 38 enters the first group of inputs of the sixth factor 50. Blocks 29, 30, 35, 36, 37, and 38 are introduced so that the above values arrive at the first inputs of multipliers 45 - 50 simultaneously. The second inputs of the sixth 50, fifth 49, fourth 48, third 47, second 46 and first 45 multipliers receive values, respectively (1/120) g _n-2 (from the outputs of the seventh register 44), (1/120) • g _{n- 1} (from the outputs of the sixth register 43), (1/120) • g _n (from the outputs of the fifth register 42), (1/120) • g _{n + 1} (from the outputs of the fourth register 41), (1/120) • g _{n + 2} (from the outputs of the third register 40), (1/120) • g _{n + 3} (from the outputs of the second register 39).

Then, at the outputs of the first 45, second 46, third 47, fourth 48, fifth 49 and sixth 50 multipliers, the following products are formed, respectively: (1/120) g _{n + 3} ΔX ⁵ , (1/120) g _{n + 2} [(1 + ΔX) ⁵ -6ΔX ⁵ ], (1/120) g _{n + 1} [(ΔX + 2) ⁵ -6 (ΔX + 1) ⁵ + 15ΔX ⁵ ], (1/120) g _n [(3-ΔX ) ⁵ -6 (2-ΔX ⁵ ) +15 (1-ΔX) ⁵ ], (1/120) g _n-1 [(2-ΔX) ⁵ -6 (1-ΔX) ⁵ ] and (1/120 ) g _n-2 (1-ΔX) ⁵ . The indicated values are summed in block 51 under the influence of clock pulses supplied to the control input of the first adder 51 from the output of the first element And 534. As a result, the desired value f (X) is generated at the output of the first adder 51. In this case, the contents of the counter 532 coincides with the number code supplied to the first installation bus 7. As a result, a single pulse is generated at the output of the first comparison unit 533. The latter goes to the control input of the first register 52. The calculated value of the function f (X) from the output of the first adder 51 is recorded in the first register 52. In addition, a single pulse from the output of the first comparison unit 533 is fed to the R-input of the RS-flip-flop 531, translating it to zero state. As a result, the signal with a zero level from the output of the RS-flip-flop 531 closes the first element And 534 and thereby prevents the passage of clock pulses through the first element And 534. This completes the work of the device to calculate the value of the function f (X). The device is ready for a new cycle of work.

The elements included in the structural diagram of the claimed device are known and described, for example, in the book of V. L. Shilo. Popular digital circuits. Directory. -M. : Radio and communication, 1988. So, in the specified source describes the principles of construction and implementation examples:
counters 9, 532 on s. 85-86 (can be implemented on the K155IE5 chip);
memory block 10 s 171-74 (can be implemented on the K155PR6 chip);
elements And 534, 535 with. 35 Fig.1.19a (can be implemented on the K155LI1 chip);
registers 39 - 44, 52 on s. 104-105 (can be implemented on the K155IR13 chip - p. 111 Fig. 1.78);
RS-trigger 531 on page 62-67 (can be implemented on the K155LE1 microcircuit - p. 63 Fig. 1.42).

 The principle of operation of the multipliers 21 - 23, 26 - 28, 45 - 50 is known and described in the book: M. A. Kartsev, V. A. Brick. Computing systems and synchronous arithmetic. - M .: Radio and communications, 1981. p. 163 - 221. They can be implemented on chips SN54284 and SN54285, p. 305, fig. 6.3.12 or on the ADSP1016 microcircuit (S. Kun. Matrix processors on VLSI: Transl. From English. - M.: Mir, 1991. p. 502, table 7.4).

 The principle of operation of comparison blocks 533, 536 is known and described in the book: Yu.V. Gavrilov, A.N. A bunch. Arithmetic devices of high-speed digital computers. - M.: Soviet Radio, 1970. p. 234-257. Can be implemented on chips K561IP2 (V.N. Veniaminov, ON Lebedev, A.I. Miroshnichenko. Chips and their application. Reference manual. 3rd ed. Revised and enlarged. - M.: Radio and communications, 1989.p. 114, Fig. 4.12b).

 The principle of operation of the adders 13, 14, 17, 18, 31 - 34, 51 is known and described in the book: D. Givone, R. Rosset. Microprocessors and microcomputers: Introductory course: Trans. from English - M.: Mir, 1983. 184-198. The full adder is described in the book of V.L. Awl. Popular digital circuits. Directory. 2nd ed., Rev. , - Chelyabinsk: Metallurgy, 1989.S. 152, fig. 1.112, p. 153, fig. 1.113. It can be implemented on the elements of EXCL. OR - K155LP5, AND - K155LI1, OR - from OR-NOT K155LE4 and NOT K155LN1.

 The principle of implementation of the converter into additional code 12 is known and described in the book of L.M. Goldenberg. Pulse and digital devices. M .: Communication, 1973. - p. 462 - 468. Can be implemented on the K155LA3 chip.

 The principle of implementation of the switch 10 is known and described in the book of V.L. Awl. Popular digital circuits. Handbook, 2nd ed., Rev., - Chelyabinsk: Metallurgy, 1989. p. 220. Can be implemented on the chip K561KTZ.

 Fifth degree blocks 15, 16, 19, 20, 24, and 25 can be implemented using multipliers, as shown in FIG. 2.

 Delay elements 29, 30, 35 - 38 can be implemented using registers, as shown in FIG. 3. The control inputs of the registers are combined. The information input of the first register is the input of the delay element, and the output of the second register is the output of the delay element.

Claims (2)

 1. An interpolator comprising first and second registers, a first multiplier, a switch, a control unit, an additional code converter, a first adder, a memory unit and a counter, wherein the counter information inputs are connected to the interpolator information bus, the control input is combined with the zero register input and the first output of the control unit, the first input of which is connected to the clock bus of the interpolator, the second input is connected to the start bus of the interpolator, and the second output is connected to the control input of the first register, the outputs are They are the output bus of the interpolator, and the information inputs are connected to the outputs of the first adder, the first group of information inputs of which are connected to the outputs of the first multiplier, and the address inputs of the memory block are connected to the outputs of the counter, characterized in that a second, third, fourth, fifth, sixth, seventh, eighth and ninth adders, third, fourth, fifth, sixth and seventh registers, first, second, third, fourth, fifth and sixth fifth degree blocks, first, second, third, four the fifth, fifth and sixth delay elements, the second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh and twelfth multipliers, the inputs of the converter in an additional code combined with the information inputs of the counter, the inputs of the first block raising to the fifth degree and the first group of inputs of the second adder, and the outputs are connected to the inputs of the fourth block of raising to the fifth degree and the first group of inputs of the third adder, the second group of inputs of which is combined with the fifth installation bus interpolated RA, by the second groups of inputs of the second, fourth and fifth adders, the first group of inputs of which is connected to the outputs of the third adder and the inputs of the third block of raising to the fifth degree, and the outputs are connected to the inputs of the sixth block of raising to the fifth degree, the outputs of which are connected to the third group of information inputs the eighth adder, the second group of information inputs of which are connected to the outputs of the tenth multiplier, the second group of inputs of which is combined with the second groups of inputs of the eighth, ninth and eleventh multipliers and is connected to the fourth installation bus of the interpolator, and the first group of inputs of the tenth multiplier is connected to the outputs of the third block of raising to the fifth degree and the second group of information inputs of the ninth adder, the first group of inputs of which is connected to the outputs of the eleventh multiplier, the first group of inputs of which is connected to the outputs of the fourth the block of raising to the fifth power, information inputs of the sixth delay element and the first group of inputs of the twelfth multiplier, the second group of inputs of which o combined with the second group of inputs of the seventh multiplier and the third interpolator installation bus, and the outputs are connected to the information inputs of the second delay element, the outputs of which are connected to the first group of information inputs of the eighth adder, the outputs of which are connected to the first group of inputs of the fourth multiplier, the second group of inputs of which is connected with the outputs of the fifth register, and the outputs with the fourth group of information inputs of the first adder, the fifth group of information inputs of which are connected to the outputs the fifth multiplier, the second group of inputs connected to the outputs of the sixth register, and the first group of inputs with the outputs of the fifth delay element, the information inputs of which are connected to the outputs of the ninth adder, the control input of which is connected to the fourth output of the control unit and the control inputs of the first, second, third , fourth, fifth, sixth, seventh and eighth adders, first, second, third, fourth, fifth and sixth delay elements, the outputs of which are connected to the first group of inputs of the sixth mind an oscillator, the second group of inputs of which is connected to the outputs of the seventh register, and the outputs - with the sixth group of information inputs of the first adder, the third group of information inputs of which is connected to the outputs of the third multiplier, the second group of inputs of which is connected to the outputs of the fourth register, and the first group of inputs - the outputs of the seventh adder, the third group of information inputs of which are connected to the outputs of the fifth block of raising to the fifth degree, the inputs of which are connected to the outputs of the fourth adder, the first group and the information inputs of which are connected to the outputs of the second adder and the inputs of the second block of raising to the fifth degree, the outputs of which are connected to the second group of inputs of the sixth adder and the first group of inputs of the ninth multiplier, the outputs of which are connected to the second group of information inputs of the seventh adder, the first group of information inputs of which connected to the outputs of the first delay element, the information inputs of which are connected to the outputs of the seventh multiplier, the first group of inputs of which is combined with inf the radiation inputs of the third delay element, the outputs of the first block raising to the fifth degree and the first group of inputs of the eighth multiplier, the outputs of which are connected to the first group of information inputs of the sixth adder, the outputs of which are connected to the information inputs of the fourth delay element, the outputs of which are connected to the first group of inputs of the second multiplier the outputs of which are connected to the second group of information inputs of the first adder, and the second group of inputs to the outputs of the third register, the control input to it is combined with the control inputs of the second, fourth, fifth, sixth, seventh registers, the counting input of the counter and the fifth output of the control unit, the third group of inputs of which is the first installation bus of the interpolator, the fourth group of inputs - the second installation bus of the interpolator, and the third group of outputs is connected to the control inputs of the switch, the information inputs of which are connected to the outputs of the memory unit, the first, second, third, fourth, fifth and sixth groups of outputs are connected respectively to the information inputs of the seventh, sixth, fifth, fourth, third and second registers, and the first group of inputs of the first multiplier is connected to the outputs of the third delay element, and the second group of inputs is connected to the outputs of the second register.  2. The interpolator according to claim 1, characterized in that the control unit comprises an RS trigger, a counter, first and second comparison units, first and second AND elements, the first input of the first AND element being connected to the output of the RS trigger, the second input is the first the input of the control unit and the clock bus of the interpolator, and the output is the fourth output of the control unit and is connected to the second input of the second element And and the counting input of the counter, the zeroing input of which is combined with the S-input of the RS trigger and is the first output of the control unit and simultaneously w the input of the control unit and the trigger bus of the interpolator, and the outputs are the third group of outputs of the control unit and are simultaneously connected to the first group of inputs of the second comparison unit and the first group of inputs of the first comparison unit, the second group of inputs of which is the third group of inputs of the control unit and the first installation bus of the interpolator , and the output is connected to the R-input of the RS-trigger and at the same time is the second output of the control unit, the second group of inputs of the second comparison unit is the fourth group of inputs b eye control and the second mounting rail interpolator, and the second comparator output is connected to a first input of the second AND gate, whose output is the fifth output of the control unit.

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