RU2148272C1 - Device for double differentiation - Google Patents

Abstract

FIELD: automation and computer engineering. SUBSTANCE: device has generator of second derivative coefficients g², where n=1, 2, ... is index of coefficient, local spline generation unit 2, and B-spline generation unit 3. EFFECT: increased precision of double differentiation of functions with continuous ninth derivative. 4 cl, 7 dwg

Description

 The invention relates to automation and computer engineering and can be used in the construction of systems including double differentiation operations.

 Known devices (USSR AS N 1233152, G 06 F 7/70 from 05.23.86, USSR AS N 1187182, G 06 F 7/18 from 10.23.85) allow differentiation, but do not allow double differentiation.

 Closest to the claimed device in its technical essence is a differentiation device, which is part of the device for estimating the carrier frequency (Patent RU 2100812, published December 27, 1997, Bull. N 12, paragraph 13 of the claims, Fig. 16, p. 89).

The prototype device comprises a second derivative coefficient generator g ² _n , the first group of inputs of which is the first group of inputs of the differentiation unit, a cubic B-spline forming unit and a local cubic spline forming unit, the first group of inputs of which is connected to the outputs of the coefficient generator, the sixth input is combined with the second input of the shaper coefficients and is the second input of the differentiation unit, the outputs are the outputs of the differentiation unit, and the second, third, fourth and the fifth group of inputs are connected respectively to the fourth, third, second and first groups of outputs of the cubic B-spline forming unit, the inputs of which are the third group of inputs of the differentiation unit.

The known technical solution has insufficient interpolation accuracy, which is characterized by an interpolation error equal to [1, p. 24]
μ ₁ = const ₁ • h ⁴ • f $\genfrac{}{}{0ex}{}{\text{(6)}}{\text{max}}$ , (1)
where f ⁽⁶⁾ _max is the maximum of the sixth derivative of the function f (x);
h is the distance between the samples of the function f (x).

Moreover, this accuracy is ensured for functions having a continuous seventh derivative (f (x) ∈ C ⁷ ). When interpolating functions having a continuous ninth derivative (f (x) ∈ C ⁹ ), this device does not fully take into account the smoothness of functions, as a result of which the prototype does not provide the necessary accuracy.

The aim of the invention is to develop a device that provides higher accuracy of double differentiation of functions having a continuous ninth derivative (f (x) ∈ C ⁹ ).

This goal is achieved by the fact that in the differentiation device containing the shaper of the coefficients of the second derivative g ² _n (n = 1, 2, ... is the coefficient number), a local spline forming unit and a B-spline forming unit, the first group of inputs of the coefficient shaper the second derivative g ² _n is the first input information bus of the double differentiation device, the second input of the coefficient former second derivative g ² _{n is} combined with the second input of the local spline forming unit and simultaneously o is the input clock bus of the double differentiation device, and the outputs are connected to the first group of inputs of the local spline forming unit, the outputs of which are the output bus of the double differentiation device, and the third, fourth, fifth, and sixth groups of inputs are connected respectively to the first, second, third, and fourth output groups of the B-spline forming unit, the first group of inputs of which is the second input information bus of the double differentiation device, additionally, the forming unit Ia local spline provided with seventh and eighth groups of inputs that are respectively connected to the fifth and sixth groups forming unit B-spline outputs. The second input of the B-spline forming unit is combined with the second input of the local spline forming unit.

The coefficient generator of the second derivative g ² _{n is} made containing the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh and twelfth multipliers, first, second, third, fourth, fifth, sixth, seventh, eighth, the ninth, tenth, eleventh, twelfth, thirteenth and fourteenth delay elements, the first, second, third, fourth, fifth, sixth, seventh, eighth and ninth elements of the initial installation and the first, second and third adders.

The first group of information inputs of the first adder is the first group of inputs of the former of the coefficients of the second derivative g ² _n and is combined with the first groups of inputs of the first, second, third, fourth, fifth, sixth, seventh, eighth and eleventh multipliers and information inputs of the fifth, sixth, tenth, the twelfth and fourteenth delay elements.

 The second group of information inputs of the first adder is connected to the outputs of the first multiplier. The second group of inputs of the first multiplier is connected to the outputs of the first element of the initial installation and the second group of inputs of the fifth multiplier. The outputs of the fifth multiplier are connected to the information inputs of the fourth delay element. The outputs of the fourth delay element are connected to the sixth group of information inputs of the first adder. The fifth group of information inputs of the first adder is connected to the outputs of the third delay element. The information inputs of the third delay element are connected to the outputs of the fourth multiplier. The second group of inputs of the fourth multiplier is connected to the outputs of the second element of the initial installation and the second group of inputs of the second multiplier. The outputs of the second multiplier are connected to the information inputs of the first delay element. The outputs of the first delay element are connected to a third group of information inputs of the first adder. The fourth group of information inputs of the first adder is connected to the outputs of the second delay element. The information inputs of the second delay element are connected to the outputs of the third multiplier. The second group of inputs of the third multiplier is connected to the outputs of the third element of the initial installation. The seventh group of information inputs of the first adder is connected to the outputs of the fifth delay element. The outputs of the first adder are connected to the second group of inputs of the ninth multiplier. The first group of inputs of the ninth multiplier is connected to the outputs of the sixth element of the initial installation. The outputs of the ninth multiplier are connected to the first group of information inputs of the third adder.

 The third group of information inputs of the third adder is connected to the outputs of the twelfth delay element. The fifth group of information inputs of the third adder is connected to the outputs of the fourteenth delay element. The fourth group of information inputs of the third adder is connected to the outputs of the thirteenth delay element. The information inputs of the thirteenth delay element are connected to the outputs of the eleventh multiplier. The second group of inputs of the eleventh multiplier is connected to the outputs of the eighth element of the initial installation. The outputs of the sixth delay element are connected to the first group of information inputs of the second adder. The second group of information inputs of the second adder is connected to the outputs of the seventh delay element. The information inputs of the seventh delay element are connected to the outputs of the sixth multiplier. The second group of information inputs of the sixth multiplier is connected to the outputs of the fourth element of the initial installation and the second group of inputs of the eighth multiplier. The outputs of the eighth multiplier are connected to the information inputs of the ninth delay element. The outputs of the ninth delay element are connected to the fourth group of information inputs of the second adder.

The third group of information inputs of the second adder is connected to the outputs of the eighth delay element. The information inputs of the eighth delay element are connected to the outputs of the seventh multiplier. The second group of information inputs of the seventh multiplier is connected to the outputs of the fifth element of the initial installation. The fifth group of information inputs of the second adder is connected to the outputs of the tenth delay element. The outputs of the second adder are connected to the second group of inputs of the tenth multiplier. The first group of inputs of the tenth multiplier is connected to the outputs of the seventh element of the initial installation. The outputs of the tenth multiplier are connected to the information inputs of the eleventh delay element. The outputs of the eleventh delay element are connected to the second group of information inputs of the third adder. The outputs of the third adder are connected to the second group of inputs of the twelfth multiplier. The first group of inputs of the twelfth multiplier is connected to the outputs of the ninth element of the initial installation. The outputs of the twelfth multiplier are connected to the outputs of the former of the coefficients of the second derivative g ² _n . The control inputs of the first, second and third adders, the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, twelfth, thirteenth and fourteenth delay elements are combined and connected to the second input of the former of the coefficients of the second derivative g ² _n

 The B-spline forming unit is made containing the first, second, third and fourth elements of the initial installation, the first, second, third, fourth, fifth, sixth and seventh multipliers, the first, second, third, fourth, fifth, sixth, seventh and eighth adders, the first, second, third, fourth, fifth and sixth elements of raising to the fifth degree, the converter into an additional code, the first, second, third, fourth, fifth and sixth delay elements. The first group of inputs of the first multiplier is connected to the first group of inputs of the B-spline forming unit. The second group of inputs of the first multiplier is connected to the outputs of the fourth element of the initial installation. The outputs of the first multiplier are connected to the inputs of the converter in an additional code, the first group of information inputs of the first adder and the inputs of the first element of raising to the fifth degree. The outputs of the first element of raising to the fifth degree are connected to the first groups of inputs of the second and third multipliers and information inputs of the third delay element. The outputs of the third delay element are connected to the first group of outputs of the B-spline forming unit. The second group of outputs of the B-spline forming unit is connected to the outputs of the fourth delay element. The information inputs of the fourth delay element are connected to the outputs of the fifth adder. The second group of information inputs of the fifth adder is connected to the outputs of the second element of raising to the fifth degree and the first group of inputs of the fourth multiplier.

 The first group of information inputs of the fifth adder is connected to the outputs of the third multiplier. The second group of inputs of the third multiplier is connected to the outputs of the second element of the initial installation and the second groups of inputs of the fourth, fifth and sixth multipliers. The outputs of the sixth multiplier are connected to the second group of information inputs of the eighth adder. The first group of inputs of the sixth multiplier is connected to the outputs of the fourth element of raising to the fifth degree, the first group of inputs of the seventh multiplier and the information inputs of the sixth delay element. The outputs of the sixth delay element are connected to the sixth group of outputs of the B-spline forming unit. The fifth group of outputs of the B-spline forming unit is connected to the outputs of the fifth delay element. The information inputs of the fifth delay element are connected to the outputs of the eighth adder. The first group of information inputs of the eighth adder is connected to the outputs of the third element of raising to the fifth degree and the first group of inputs of the fifth multiplier. The outputs of the fifth multiplier are connected to the second group of information inputs of the seventh adder.

 The third group of information inputs of the seventh adder is connected to the output of the second delay element. The information inputs of the second delay element are connected to the outputs of the seventh multiplier. The second group of inputs of the seventh multiplier is connected to the outputs of the first element of the initial installation and the second group of inputs of the second multiplier. The outputs of the second multiplier are connected to the information inputs of the first delay element. The outputs of the first delay element are connected to the first group of information inputs of the sixth adder. The second group of information inputs of the sixth adder is connected to the outputs of the fourth multiplier. The third group of information inputs of the sixth adder is connected to the outputs of the fifth element of raising to the fifth degree. The outputs of the sixth adder are connected to the third group of outputs of the B-spline forming unit. The fourth group of outputs of the B-spline forming unit is connected to the outputs of the seventh adder. The first group of information inputs of the seventh adder is connected to the outputs of the sixth element of raising to the fifth degree. The inputs of the sixth degree raising element are connected to the outputs of the fourth adder. The second group of information inputs of the fourth adder is connected to the outputs of the third element of the initial installation, the second group of information inputs of the first, second and third adders. The first group of information inputs of the fourth adder is connected to the inputs of the third element of raising to the fifth degree and the outputs of the second adder. The first group of information inputs of the second adder is connected to the outputs of the Converter in an additional code and the inputs of the fourth element of raising to the fifth degree.

 The control input of the second adder is connected to the control inputs of the third, fourth, fifth, sixth, seventh and eighth adders, the control inputs of the first, second, third, fourth, fifth and sixth delay elements, the second input of the B-spline forming unit and the control input of the first adder. The outputs of the first adder are connected to the inputs of the second element of raising to the fifth degree and the first group of information inputs of the third adder. The outputs of the third adder are connected to the inputs of the fifth element of raising to the fifth degree.

 The local spline forming unit is made comprising first, second, third, fourth, fifth and sixth multipliers, first, second, third, fourth and fifth delay elements, an adder and a register. The second groups of inputs of the first, second, third, fourth, fifth and sixth multipliers are combined and connected to the first group of inputs of the local spline forming unit. The first group of inputs of the first multiplier is connected to the eighth group of inputs of the local spline forming unit. The outputs of the first multiplier are connected to the first group of information inputs of the adder. The second group of information inputs of the adder is connected to the outputs of the first delay element. The information inputs of the first delay element are connected to the outputs of the second multiplier. The first group of inputs of the second multiplier is connected about the seventh group of inputs of the local spline forming unit. The sixth group of inputs of the local spline forming unit is connected to the first group of inputs of the third multiplier. The outputs of the third multiplier are connected to the information inputs of the second delay element. The outputs of the second delay element are connected to the third group of information inputs of the adder. The fourth group of information inputs of the adder is connected to the outputs of the third delay element. The information inputs of the third delay element are connected to the outputs of the fourth multiplier. The first group of inputs of the fourth multiplier is connected to the fifth group of inputs of the local spline forming unit. The fourth group of inputs of the local spline forming unit is connected to the first group of inputs of the fifth multiplier. The outputs of the fifth multiplier are connected to the information inputs of the fourth delay element. The outputs of the fourth delay element are connected to the fifth group of information inputs of the adder. The sixth group of information inputs of the adder is connected to the outputs of the fifth delay element. The information inputs of the fifth delay element are connected to the outputs of the sixth multiplier. The first group of inputs of the sixth multiplier is connected to the third group of inputs of the local spline forming unit. The second input of the local spline forming unit is connected to the control inputs of the first, second, third, fourth and fifth delay elements, adder and register. Information inputs of the register are connected to the outputs of the adder. The outputs of the register are connected to the outputs of the local spline forming unit.

The listed new set of essential features of the claimed device provides higher accuracy of double differentiation of functions having a continuous ninth derivative (f (x) ∈ C ⁹ ). This is achieved by the fact that the device takes into account a priori information about the degree of smoothness of the function.

где g_n = [(z_n+1 - 2z_n + z_n-1) - (z_n+2 - 4z_n+1 + 6z_n- 4z_n-1 + z_n-2)/3 + 31(z_n+3 - 6z_n+2 + 15z_n+1 - 20z_n + 15z_n-1 - 6z_n-2 + z_n-3)/360]/h²; (3)
z_n - n-й отсчет функции f(x);
τ = m•τ₀;
m=1, 2, ..., M;
M - количество точек дифференцирования;
τ₀∈[0,1].
Реализация (2) в виде устройства позволяет вычислять функции f(x) ∈ C⁹ с точностью, определяемой погрешностью [1, с. 25], [2, c. 1307-1308]
μ₂= const₂•h⁷•f $\genfrac{}{}{0ex}{}{\text{(8)}}{\text{max}}$ , (4)
где f⁽⁸⁾ _max - максимум пятой производной функции f(x);
h - шаг интерполяции.So, from [1, 2] it is known that for double differentiation of a function by splines of a minimal fifth-degree template, one can obtain calculated expressions. As an implementation of the device of double differentiation in accordance with the method of estimating the carrier frequency and a device for its implementation (patent RU 2100812 C1, published 12/27/97, Bull. N 36, S. 29-32, expressions (15 - 24)) and article, described in [2], we consider a fourth-degree spline. For him, m = 6, so r = 4 (the largest even number less than m). Therefore, to calculate the second derivative, it is necessary to use the expression

where g _n = [(z _{n + 1} - 2z _n + z _n-1 ) - (z _{n + 2} - 4z _{n + 1} + 6z _n - 4z _n-1 + z _n-2 ) / 3 + 31 (z _{n + 3} - 6z _{n + 2} + 15z _{n + 1} - 20z _n + 15z _n-1 - 6z _n-2 + z _n-3 ) / 360] / h ² ; (3)
z _n is the n-th sample of the function f (x);
τ = m • τ ₀ ;
m = 1, 2, ..., M;
M is the number of differentiation points;
τ ₀ ∈ [0,1].
Implementation of (2) in the form of a device allows one to calculate the functions f (x) ∈ C ⁹ with an accuracy determined by the error [1, p. 25], [2, p. 1307-1308]
μ ₂ = const ₂ • h ⁷ • f $\genfrac{}{}{0ex}{}{\text{(eight)}}{\text{max}}$ , (4)
where f ⁽⁸⁾ _max is the maximum of the fifth derivative of the function f (x);
h is the interpolation step.

The accuracy of the prototype device is not better than that given in expression (1). Therefore, for example, for functions f ∈ C ⁹ with h = 0.1 and in the case const ₁ • f ⁽⁶⁾ _max ≈ const ₂ • f ⁽⁸⁾ _{max, the} gain μ ₁ / μ ₂ can reach a value of one hundred.

In FIG. 1 shows a structural diagram of the claimed device;
in FIG. 2 is a structural diagram of a coefficient generator of the second derivative g ² _n ;
in FIG. 3 is a structural diagram of a block for generating B-spline parameters;
in FIG. 4 is a structural diagram of a block for forming a local spline;
in FIG. 5 shows one possible implementation of the delay element;
in FIG. 6 shows an embodiment of an initial setup element;
in FIG. 7 shows a variant of implementation of the element of raising to the fifth degree.

The double differentiation device shown in FIG. 1, consists of a factor generator of the second derivative g ² _n 1 (n = 1, 2, ... is the coefficient number), a local spline formation unit 2 and a B-spline formation unit 3. The first group of inputs of the coefficient former of the second derivative g ² _n 1 is the first input information bus of a double differentiation device. The second input of the shaper of the coefficients of the second derivative g ² _n 1 is combined with the second input of the block forming the local spline 2 and at the same time is the input clock bus of the double differentiation device. The outputs of the shaper of the coefficients of the second derivative g ² _n 1 are connected to the first group of inputs of the local spline 2 forming unit. The outputs of the local spline 2 forming unit are the output bus of the double differentiation device. The third, fourth, fifth and sixth groups of inputs of the local spline forming unit 2 are connected respectively to the first, second, third and fourth groups of outputs of the B-spline forming unit 3. The first group of inputs of the B-spline forming unit 3 is the second input information bus of the double differentiation device . The local spline forming unit 2 is provided with seventh and eighth input groups, which are respectively connected to the fifth and sixth output groups of the B-spline forming unit 3. The second input of the B-spline forming unit 3 is combined with the second input of the local spline forming unit 2.

The coefficient generator of the second derivative g ² _n 1 shown in FIG. 2, consists of the first 11, second 13, third 16, fourth 19, fifth 111, sixth 115, seventh 118, eighth 121, ninth 127, tenth 129, eleventh 132 and twelfth 138 multipliers, first 14, second 17, third 110, fourth 112, fifth 113, sixth 114, seventh 116, eighth 119, ninth 122, tenth I23, eleventh 131, twelfth 130, thirteenth 133 and fourteenth 135 delay elements, first 12, second 15, third 18, fourth 117, fifth I20, sixth 126, seventh 128, eighth 134 and ninth 137 elements of the initial installation, first 124, second 125 and third about 136 adders. The first group of information inputs of the first adder 124 is the first group of inputs of the former of the coefficients of the second derivative g ² _n 1 and is combined with the first groups of inputs of the first 11, second 13, third 16, fourth 19, fifth 111, sixth 115, seventh 118, eighth 121 and eleventh 132 multipliers and information inputs of the fifth 113th, sixth 114th, tenth 123th, twelfth 130th and fourteenth 135th delay elements. The second group of information inputs of the first adder 124 is connected to the outputs of the first multiplier 11. The second group of inputs of the first multiplier 11 is connected to the outputs of the first element of the initial setup 12 and the second group of inputs of the fifth multiplier 111. The outputs of the fifth multiplier 111 are connected to the information inputs of the fourth delay element 112. Outputs the fourth delay element 112 is connected to the sixth group of information inputs of the first adder 124. The fifth group of information inputs of the first adder 124 is connected to the outputs of the third delay element 110. The information inputs of the third delay element 110 are connected to the outputs of the fourth multiplier 19. The second group of inputs of the fourth multiplier 19 is connected to the outputs of the second element of the initial setup 15 and the second group of inputs of the second multiplier 13. The outputs of the second multiplier 13 are connected to the information inputs of the first delay element 14. The outputs of the first delay element 14 are connected to the third group of information inputs of the first adder 124. The fourth group of information inputs of the first adder 124 is connected with the outputs of the second delay element 17.

 The information inputs of the second delay element 17 are connected to the outputs of the third multiplier 16. The second group of inputs of the third multiplier 16 is connected to the outputs of the third element of the initial setup 18. The seventh group of information inputs of the first adder 124 is connected to the outputs of the fifth delay element 113. The outputs of the first adder 124 are connected to the second the group of inputs of the ninth multiplier 127. The first group of inputs of the ninth multiplier 127 is connected to the outputs of the sixth element of the initial installation 126. The outputs of the ninth multiplier 127 are connected to the first group of information inputs of the third adder 136. The third group of information inputs of the third adder 136 is connected to the outputs of the twelfth delay element 130. The fifth group of information inputs of the third adder 136 is connected to the outputs of the fourteenth delay element 135. The fourth group of information inputs of the third adder 136 is connected to the outputs of the thirteenth 133 delay element. The information inputs of the thirteenth delay element 133 are connected to the outputs of the eleventh multiplier 132. The second group of inputs of the eleventh multiplier 132 is connected to the outputs of the eighth element of the initial setting 134. The outputs of the sixth delay element 114 are connected to the first group of information inputs of the second adder 125. The second group of information inputs of the second adder 125 connected to the outputs of the seventh delay element 116.

The information inputs of the seventh delay element 116 are connected to the outputs of the sixth multiplier 115. The second group of information inputs of the sixth multiplier 115 is connected to the outputs of the fourth element of the initial installation 117 and the second group of inputs of the eighth multiplier 121. The outputs of the eighth multiplier 121 are connected to the information inputs of the ninth delay element 122. Outputs the ninth delay element 122 is connected to the fourth group of information inputs of the second adder 125. The third group of information inputs of the second adder 125 is connected to the outputs of the eighth delay element 119. The information inputs of the eighth delay element 119 are connected to the outputs of the seventh multiplier 118. The second group of information inputs of the seventh multiplier 118 is connected to the outputs of the fifth element of the initial setup 120. The fifth group of information inputs of the second adder 125 is connected to the outputs of the tenth delay element 123. The outputs of the second adder 125 are connected to the second group of inputs of the tenth multiplier 129. The first group of inputs of the tenth multiplier 129 is connected to the outputs of the seventh element of the th installation 128. The outputs of the tenth multiplier 129 are connected to the information inputs of the eleventh delay element 131. The outputs of the eleventh delay element 131 are connected to the second group of information inputs of the third adder 136. The outputs of the third adder 136 are connected to the second group of inputs of the twelfth multiplier 138. The first group of inputs of the twelfth multiplier 138 is connected to the outputs of the ninth element of the initial setup 137. The outputs of the twelfth multiplier 138 are connected to the outputs of the coefficient former of the second derivative g ² _n 1. The control inputs of the first 124, second 125 and third 136 adders and the first 14, second 17, third 110, fourth 112, fifth 113, sixth 114, seventh 116, eighth 119, ninth 122, tenth 123, eleventh 131, twelfth 130 , thirteenth 133 and fourteenth 135 delay elements are combined and connected to the second input of the former of the coefficients of the second derivative g ² _n 1.

 The B-spline 3 parameter generating unit shown in FIG. 3, consists of the first 31, second 32, third 33 and fourth 35 elements of the initial installation, the first 34, second 315, third 316, fourth 317, fifth 320, sixth 321 and seventh 322 multipliers, first 37, second 38, third 311, fourth 312, fifth 325, sixth 326, seventh 327 and eighth 328 adders, first 39, second 310, third 313, fourth 314, fifth 318 and sixth 319 elements of raising to the fifth degree, converter to additional code 36, first 323, second 324 , third 329, fourth 330, fifth 331, and sixth 332 delay elements. The first group of inputs of the first multiplier 34 is connected to the first group of inputs of the B-spline forming unit 3. The second group of inputs of the first multiplier 34 is connected to the outputs of the fourth element of the initial installation 35. The outputs of the first multiplier 34 are connected to the inputs of the converter into additional code 36, the first group of information inputs the first adder 37 and the inputs of the first element of raising to the fifth degree 39. The outputs of the first element of raising to the fifth degree 39 are connected to the first groups of inputs of the second 315 and third 316 multiplier and information inputs of the third delay element 329. The outputs of the third delay element 329 are connected to the first group of outputs of the B-spline generating unit 3. The second group of outputs of the B-spline forming unit 3 is connected to the outputs of the fourth delay element 330. The information inputs of the fourth delay element 330 are connected to the outputs of the fifth adder 325. The second group of information inputs of the fifth adder 325 is connected to the outputs of the second fifth raising element 310 and the first group of inputs of the fourth multiplier 317.

 The first group of information inputs of the fifth adder 325 is connected to the outputs of the third multiplier 316. The second group of inputs of the third multiplier 316 is connected to the outputs of the second element of the initial installation 32 and second groups of inputs of the fourth 317, fifth 320, and sixth 321 multipliers. The outputs of the sixth multiplier 321 are connected to the second group of information inputs of the eighth adder 328. The first group of inputs of the sixth multiplier 321 is connected to the outputs of the fourth fifth raising element 314, the first group of inputs of the seventh multiplier 322 and the information inputs of the sixth delay element 332. The outputs of the sixth delay element 332 connected to the sixth group of outputs of the B-spline forming unit 3. The fifth group of outputs of the B-spline forming unit 3 is connected to the outputs of the fifth delay element 331. Information inputs of the long delay element 331 are connected to the outputs of the eighth adder 328. The first group of information inputs of the eighth adder 328 is connected to the outputs of the third fifth raising element 313 and the first group of inputs of the fifth multiplier 320. The outputs of the fifth multiplier 320 are connected to the second group of information inputs of the seventh adder 327. The third group of information inputs of the seventh adder 327 is connected to the outputs of the second delay element 324.

 The information inputs of the second delay element 324 are connected to the outputs of the seventh multiplier 322. The second group of inputs of the seventh multiplier 322 is connected to the outputs of the first element of the initial installation 31 and the second group of inputs of the second multiplier 315. The outputs of the second multiplier 315 are connected to the information inputs of the first element delayed 323. The outputs of the first delay elements 323 are connected to the first group of information inputs of the sixth adder 326. The second group of information inputs of the sixth adder 326 is connected to the outputs of the fourth Itel 317. The third group of information inputs of the sixth adder 326 is connected to the outputs of the fifth element of raising to the fifth degree 318. The outputs of the sixth adder 326 are connected to the third group of outputs of the B-spline forming unit 3. The fourth group of outputs of the B-spline forming unit 3 is connected to the outputs of the seventh the adder 327. The first group of information inputs of the seventh adder 327 is connected to the outputs of the sixth element of raising to the fifth degree 319. The inputs of the sixth element of raising to the fifth degree 319 are connected to the outputs of the fourth matora 312. The second group of information inputs of the fourth adder 312 is connected to the outputs of the third element of the initial installation 33, the second groups of information inputs of the first 37, second 38 and third 311 adders. The first group of information inputs of the fourth adder 312 is connected to the inputs of the third element of raising to the fifth degree 313 and the outputs of the second adder 38. The first group of information inputs of the second adder 38 is connected to the outputs of the converter into additional code 36 and the inputs of the fourth element of raising to the fifth degree 314. Control input the second adder 36 is connected to the control inputs of the third, fourth, fifth, sixth, seventh 327 and eighth 328 adders, controlling the inputs of the first 323, second 324, third 329, even grated 330, fifth 331 and sixth 332 delay elements, the second input of the B-spline forming unit 3 and the control input of the first adder 37. The outputs of the first adder 37 are connected to the inputs of the second raising element to the fifth degree 310 and the first group of information inputs of the third adder 311. Outputs the third adder 311 is connected to the inputs of the fifth element of raising to the fifth degree 318.

 The local spline forming unit 2 shown in FIG. 4 consists of the first 21, second 22, third 23, fourth 24, fifth 25 and sixth 26 multipliers, the first 27, second 28, third 29, fourth 210 and fifth 211 delay elements, the adder 212 and register 213. The second groups of inputs of the first 21, second 22, third 23, fourth 24, fifth 25 and sixth 26 multipliers are combined and connected to the first group of inputs of the local spline forming unit 2. The first group of inputs of the first multiplier 21 is connected to the eighth group of inputs of the local spline forming unit 2. The outputs of the first multiplier 21 connected to lane the first group of information inputs of the adder 212. The second group of information inputs of the adder 212 is connected to the outputs of the first delay element 27. The information inputs of the first delay element 27 are connected to the outputs of the second multiplier 22. The first group of inputs of the second multiplier 22 is connected to the seventh group of inputs of the local spline forming unit 2 The sixth group of inputs of the local spline forming unit is connected to the first group of inputs of the third multiplier 23. The outputs of the third multiplier 23 are connected to the information inputs of the second holding element 28. The outputs of the second delay element 28 are connected to the third group of information inputs of the adder 212. The fourth group of information inputs of the adder 212 is connected to the outputs of the third delay element 29. The information inputs of the third delay element 29 are connected to the outputs of the fourth multiplier 24. The first group of inputs of the fourth the multiplier 24 is connected to the fifth group of inputs of the local spline forming unit 2. The fourth group of inputs of the local spline forming unit 2 is connected to the first input group s of the fifth multiplier 25. The outputs of the fifth multiplier 25 are connected to the information inputs of the fourth delay element 210. The outputs of the fourth delay element 210 are connected to the fifth group of information inputs of the adder 212. The sixth group of information inputs of the adder 212 is connected to the outputs of the fifth delay element 211. Information inputs of the fifth element delays 211 are connected to the outputs of the sixth multiplier 26. The first group of inputs of the sixth multiplier 26 is connected to the third group of inputs of the local spline forming unit 2. Second input the local spline forming unit 2 is connected to the control inputs of the first 27, second 28, third 29, fourth 210 and fifth 211 delay elements, the adder 212 and the register 213. The information inputs of the register 213 are connected to the outputs of the adder 212. The outputs of the register 213 are connected to the outputs of the forming unit local spline 2.

 The claimed device operates as follows.

с первой, второй, третьей, четвертой, пятой и шестой групп выходов блока формирования В-сплайна 3. Далее в блоке формирования локального сплайна 2 происходит умножение указанных значений на коэффициенты второй производной g² _n и суммирование полученных произведений (см. выражение (2)). В результате на выходе устройства формируется значение производной функции f''(x).In the initial state, the value of the parameter τ ₀ is supplied to the second information bus of the device. The clock bus receives clock pulses of the meander type, under the influence of which, upon receipt of the discrete values of the function f (x) on the first information bus, the unit 1 generates the values of the coefficients of the second derivative g ² _n . These values are alternately supplied to the first group of inputs of the local spline formation block 2. The corresponding values are supplied to the second, third, fourth, fifth, sixth and seventh groups of inputs of the latter:

from the first, second, third, fourth, fifth and sixth groups of outputs of the B-spline 3 forming unit. Next, in the local spline 2 forming unit, these values are multiplied by the coefficients of the second derivative g ² _n and the resulting products are summed (see expression (2) ) As a result, the value of the derivative of the function f '' (x) is formed at the output of the device.

The operation of the shaper coefficients of the second derivative g ² _{n is} carried out in accordance with expression (3).

In the initial state, at the outputs of the first 12, second 15, third 18, fourth 117, fifth 120, sixth 126, seventh 128, eighth 134 and ninth 137 elements of the initial setting, codes of numbers are generated, respectively -6, 15, -20, -4, 6 , 31/360, -1/3, -2, 1/120. When applying to the second input of block 1 control pulses to the information input of block 1, the values of the function f (x) are received: z _n-3 , z _n-2 , ..., z _{n + 3} . The latter alternately follow: the first inputs of the first 11, second 13, third 16, fourth 19, fifth 111, sixth 115, seventh 118, eighth 121 and eleventh 132 multipliers, inputs of the fifth 113, sixth 114, tenth 123, eleventh 131 and fourteenth 135 delay elements and the first information input of adder 124. Elements 11 through 113 form six terms that arrive at the information inputs of the first adder 124 at the same time. The seventh term comes from the input of block 1 to the first information input of the first adder 124 directly. The calculation result in the second adder 125 is the value (z _{n + 3} - 6z _{n + 2} + 15z _{n + 1} - 20z _n + 15z _n-1 - 6z _n-2 + z _n-3 ). Elements 114 - 123 form five terms for the second adder 125. All five terms are fed to the information inputs of the second adder 125 at the same time. As a result of the addition operation, the value (z _{n + 2} + 4z _{n + 1} + 6z _n - 4z _n-1 + z _n-2 ) is generated at the output of the second adder 125. The value (z _{n + 3} - 6z _{n + 2} + 15z _{n + 1} - 20z _n + 15z _n-1 - 6z _n-2 + z _n-3 ), multiplied by 31/360 in the ninth multiplier 127, is the first term for the third adder 136. The second term is the value (z _{n + 2} - 4z _{n + 1} + 6z _n - 4z _n-1 + z _n-2 ) multiplied in the tenth multiplier 129 by the number -1/3 and delayed in the twelfth delay element 130. The third term is the z _n-1 value _{of the} function f (x) delayed in the eleventh delay element 130. The fourth term is the z _n- value of the function f (x) multiplied in the eleventh multiplier 132 by -2 and delayed in the thirteenth delay element 133 Fifth th term is the value of z _{n + 1} retained in the fourteenth delay element 135. The output of the third adder 136 is multiplied by the summation operation in the twelfth multiplier 138 by the number of 1/120. As a result, at the output of block 1, the desired value of the coefficient of the second derivative g ² _{n is formed} .

One of the possible options for constructing delay elements
14, 17, 110, 112, 113, 114, 116, 119, 122, 123, 130, 131, 133, 135 are shown in FIG. 5. The indicated elements are of the same type. For delay elements 14, 114, 116 and 130 n = 2. For delay elements 17 and 119 n = 3. For delay elements 110 and 122 n = 4. For delay element 112 n = 5, for delay element 123 n = 6, for a delay element 131 n = 8. For a delay element 135 n = 6. Can be implemented on K155IR13 microcircuits.

The elements included in the structural diagram of the claimed device are known and described, for example, in [3] - [7]. So, in [3] construction principles and examples of register implementation are described on p. 104-105 (can be implemented on the K155IR13 microcircuit - p. 111, Fig. 1.78);
The principle of operation of multipliers is known and described in [4] on p. 163-221. They can be implemented on SN54284 and SN54285 microcircuits (see [4], p. 305, Fig. 6.3.12) or on the ADSP1016 microcircuit (see [5] p. 502, Table 7.4).

 The principle of operation of adders is known and described in [6] on p. 184-198. The full adder is described in [7] us. 152, fig. 1.112 and c. 153, fig. 1.113. It can be implemented on the elements of EXCL. OR - K155LP5, AND - K155LI1, OR - from OR-NOT - K155JE4 and NOT - K155LN1.

 One possible embodiment of the initial installation blocks is shown in FIG. 6.

 Block forming a B-spline 3 works as follows.

In the initial state, at the outputs of the elements of the initial installation 31, 32, 33, codes of numbers are formed, respectively, 15, -6, 1. At the output of the element of the initial installation 35, a code of the number m corresponding to the number of the differentiation point is generated. The control input of block 3 receives control signals from the device clock bus. At the second information input of block 3, the value τ ₀ is supplied.

The indicated value goes to the first group of inputs of the multiplier 34, and to another group of its inputs - the value m from the output of the initial setting element 35. As a result of the multiplication operation, the values of τ = m • τ _{0 are} generated at the outputs of the multiplier 34. The latter is fed to the input of the converter in additional code 36, at the output of which we have the value (1-τ). The value τ of the output of the multiplier 34 is also supplied to the first input of the adder 37, and to the first input of the adder 38 the value (1-τ). At the second inputs of adders 37 and 38, the code of number 1 is supplied. Under the influence of control signals received via the clock bus, the values of (1 + τ) and (2-τ) are generated at the outputs of adders 37 and 38. The latter are fed to the first inputs of adders 311 and 312, respectively. The second inputs of these adders are supplied with the code of the number 1. As a result of the summation operation, the outputs of adders 311 and 312 generate values (τ + 2) and (3-τ), respectively.

. Значение (1-τ)⁵ c выхода элемента возведения в пятую степень 314 поступает на первые входы умножителей 321 и 3S2. На второй вход умножителя 321 подается код числа -6, а на второй вход умножителя 322 - код числа 15. В результате выполнения операции умножения на выходах умножителей 321 и 322 формируются значения соответственно -6(1-τ)⁵ и 15(1-τ)⁵. С выхода умножителя 316 на первый вход сумматора 325 поступает значение -6τ⁵.The indicated values are supplied to the inputs of the corresponding elements of raising to the fifth power 318 and 319. The value of τ from the output of the multiplier 51 is input to the element of the raising to the fifth power 39. The value of (τ + 1) from the output of the adder 37 is input to the element of the raising to the fifth power 310. The value of (2-τ) from the output of the adder 38 is received at the input of the element of raising to the fifth degree 313. The value of (1-τ) from the output of the converter to the additional code 36 is received at the input of the element of raising to the fifth degree 31. At the outputs of the elements of raising to the fifth degree 39, 310, 318 , 319, 313 and 314, we have the values τ ⁵ , (τ + 1) ⁵ , (τ + 2) ⁵ , (3-) τ ⁵ , (2-τ ⁵ ) and (1-τ) ^5, respectively. The value of τ ⁵ from the output of the fifth stepping element 39 is supplied to the first inputs of the multipliers 315 and 316. The code of the number 15 is supplied to the second input of the multiplier 315, and the code of the number -6 is sent to the second input of the multiplier 316. As a result of the multiplication operation, the outputs of the multipliers 315 and 316 generate values of 15τ ⁵ and -6τ ^5, respectively. The values of (τ + 1) ⁵ and (2-τ) ⁵ are fed to the first inputs of the multipliers 317 and 320, respectively. At the second inputs of these multipliers, the code of the number -6 is supplied. As a result of the operation of multiplication at the outputs of the multipliers 317 and 320, values of -6 (τ + 1) ⁵ and

. The value (1-τ) ⁵ c of the output of the element of raising to the fifth power 314 is supplied to the first inputs of the multipliers 321 and 3S2. The code of the number -6 is supplied to the second input of the multiplier 321, and the code of the number 15 is sent to the second input of the multiplier 322. As a result of the multiplication operation, the values of -6 (1-τ) ⁵ and 15 (1-τ) are generated at the outputs of the multipliers 321 and 322 ) ⁵ . From the output of the multiplier 316, the value -6τ ^{5 is} supplied to the first input of the adder 325.

At the same time, the value (τ + 1) ⁵ arrives at the second input of the adder 325 from the output of the element of raising to the fifth power 310. As a result of the summation operation, the value (τ + 1) ⁵ -6τ ⁵ is generated at the output of the adder 325. The latter, through the delay element 330, is supplied to the second output of the B-spline forming unit 3. The value of 15τ ⁵ from the output of the multiplier 315 is fed through the delay element 323 to the first input of the adder 326. At the same time, the value -6 (τ + 1) ⁵ s is supplied to the second input of the last one. the output of the multiplier 317, and to the third input, the value (τ + 2) ⁵ from the output of the element of raising to the fifth power 318. As a result of the summation operation, the value 15τ ⁵ + (τ + 2) ⁵ -6 (τ + 1) ⁵ . The latter is fed to the third output of block 3. From the output of multiplier 321, the value -6 (1-τ) ^{5 is} supplied to the first input of adder 328. At the same time, the value (2-τ) ⁵ arrives at the second input of adder 328 from the output of the element of raising to the fifth power 313. As a result of the summation operation, the value (2-τ) ⁵ -6 (1-τ) ⁵ is generated at the output of adder 328. The latter through the delay element 331 is fed to the fifth output of the B-spline forming unit 3. The value 15 (1-τ) ⁵ from the output of the multiplier 322 is fed through the delay element 324 to the first input of the adder 327. At the same time, the value -6 (2 -τ) ⁵ from the output of the multiplier 320, and to the third input, the value (3-τ) ⁵ from the output of the element of raising to the fifth power 319. As a result of the operation of summation, the value 15 (1-τ) ⁵ + ( 3-τ) ⁵ -6 (2-τ) ⁵ . The latter is fed to the fourth output of block 3. The value of τ ⁵ from the output of the element of raising to the fifth power 39 through the delay element 329 is supplied to the first output of block 3. The value (1-τ) ⁵ from the output of the element of raising to the fifth power 314 through the delay element 332 is received to the sixth output of block 3. Thus, the indicated values of the B-spline parameters are formed at the outputs of block 3 at the same time.

 The principle of implementation of the converter into additional code 36 is known and described in [8] on p. 462 - 468. Can be implemented on chips K155LA3, K155LP5, K155LE4 and K155LN1. Multipliers can be implemented on the SN54284 and SN54285 chips or on the ADSP1016 chip. Adders can be implemented on the elements of the ISKL. OR - K155LP5, AND - K155LI1, OR - from OR-NOT - K155LE4 and NOT - K155LN1. Elements of the initial installation are implemented in accordance with FIG. 6. One of the possible embodiments of the elements of raising to the fifth degree is shown in FIG. 7.

 The delay elements included in block 3 are implemented in accordance with FIG. 5, moreover, for elements 323, 324, 330, 331, n = 2 is selected, and for elements 329 and 332 n = 4.

Block forming a local spline 2 operates as follows. From the output of block 1, the coefficients of the second derivative g ² _n simultaneously arrive at the first groups of inputs of the multipliers 21 - 26. The values of the B-spline from the outputs of block 3 are sent to the second groups of inputs of the latter. As a result, the output from the multiplier 21 gives the value of the first information input of adder 212 (1/120) g _n-2 (1-τ) ⁵ , from the output of the multiplier 22 through the delay element 27 to the second information input of the adder 212 - the value (1/120) g _n-1 [(2-τ) ⁵ -6 (1-τ) ⁵ ], from the output of the multiplier 23 through the delay element 28 to the third information input of the adder 212 - the value (1/120) g _n [(3-τ) ⁵ -6 (2-τ) ⁵ +15 (1-τ) ⁵ ], from the output of the multiplier 24 through the delay element 29 to the fourth information input of the adder 212 - the value (1/120) g _{n + 1} [(τ + 2) ⁵ -6 (τ + 1) ⁵ + 15τ ² ], from the output of the multiplier 25 through the delay element 212 to the fifth information input of the adder 212 - the value (1/120) g _{n + 2} [1 + τ) ⁵ -6τ ⁵ ], from the output of the multiplier 26 through the delay element 211 to the sixth information input of the adder 212 is the value (1/120) g _{n + 3} • τ ⁵ . The result of the summation in the adder 212 - the desired value of the second derivative of the function f '' (x) - is written to the register 213 under the influence of a pulse supplied to its control input.

 The delay elements included in block 2 are implemented in accordance with FIG. 5, where n = 2 is selected for element 27, n = 3 for element 28, n = 4 for element 29, n = 5 for element 210, and n = 6 for element 211. Multipliers can be implemented on SN64284 and SN54285 microcircuits or microchip ADSP1016. The adder can be implemented on the elements of the ESCL. OR - K155LP5, AND - K155LI1, OR - from OR-NOT - K155LE4 and NOT - K155LN1. The register can be implemented on the chip K155IR13.

Literature
1. Zheludev V. A. Restoration of functions and their derivatives from grid data with an error using local splines. // Journal of Computational Mathematics and Mathematical Physics. - 1987. - Volume 27. - N 1. - S. 22-34.

 2. Zheludev V.A. Local spline approximation on a uniform grid. // Journal of Computational Mathematics and Mathematical Physics. - 1987. - Volume 27. - N 9. - S. 1296-1310.

 3. V.-CH. Awl. Popular digital circuits. Directory. - M.: Radio and Communications, 1988.

 4. M.A. Kartsev, V.A. Brick. Computing systems and synchronous arithmetic. - M.: Radio and Communications, 1981.

 6. D. Givone, R. Rosset. Microprocessors and microcomputers: Introductory course: Trans. from English - M.: Mir, 1983.

 7. V. L. Shilo. Popular digital circuits. Directory. 2nd ed., Rev. - Chelyabinsk: Metallurgy, 1989.

 8. L.M. Goldenberg. Pulse and digital devices. M .: Communication, 1973.

Claims (4)

1. The device of double differentiation, containing the driver of the coefficients of the second derivative g ² _n (n = 1,2, ... is the coefficient number), the local spline forming unit and the B-spline forming unit, the first group of inputs of the coefficient former of the second derivative g ² _n is a first input data line double differentiation device, the second input of the coefficients of the second derivative of g _n ² is combined with a second input unit for generating a local spline and is simultaneously input clock w double differentiation device, and the outputs are connected to the first group of inputs of the local spline forming unit, the outputs of which are the output bus of the double differentiation device, and the third, fourth, fifth and sixth groups of inputs are connected to the first, second, third and fourth groups of outputs of the forming unit B-spline, the first group of inputs of which is the second input information bus of the double differentiation device, characterized in that the local spline forming unit nabzhen seventh and eighth groups of inputs that are respectively connected to the fifth and sixth groups forming unit outputs a B-spline, the second input of which is combined with a second input unit for generating a local spline. 2. The double differentiation device according to claim 1, characterized in that the coefficient generator of the second derivative g ² _{n is} made containing the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh and twelfth multipliers, the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, twelfth, thirteenth and fourteenth delay elements, first, second, third, fourth, fifth, sixth, seventh, eighth and ninth initial installation blocks, and first, second and tr there are adders, and the first group of information inputs of the first adder is combined with the first groups of inputs of the first, second, third, fourth, fifth, sixth, seventh, eighth and eleventh multipliers and information inputs of the fifth, sixth, tenth, twelfth and fourteenth delay elements and the first group inputs of the second derivative shaper coefficients g ² _n, a second group of information inputs of the first adder connected to the outputs of the first multiplier, a second group of inputs of which is connected with vyho the first installation unit and the second group of inputs of the fifth multiplier, the outputs of which are connected to the information inputs of the fourth delay element, the outputs of which are connected to the sixth group of information inputs of the first adder, the fifth group of information inputs of which is connected to the outputs of the third delay element, the information inputs of which are connected to the outputs of the fourth multiplier, the second group of inputs of which is connected to the outputs of the second block of the initial installation and the second group of inputs of the second smart a resident whose outputs are connected to the information inputs of the first delay element, the outputs of which are connected to the third group of information inputs of the first adder, the fourth group of information inputs of which is connected to the outputs of the second delay element, information inputs of which are connected to the outputs of the third multiplier, the second group of inputs of which is connected to the outputs of the third block of the initial installation, the seventh group of information inputs of the first adder is connected to the outputs of the fifth delay element, and the outputs The inputs are connected to the second group of inputs of the ninth multiplier, the first group of inputs of which is connected to the outputs of the sixth unit of the initial installation, and the outputs are connected to the first group of information inputs of the third adder, the third group of information inputs of which are connected to the outputs of the twelfth delay element, the fifth group of information inputs - the outputs of the fourteenth delay element, and the fourth group of information inputs is connected to the outputs of the thirteenth delay element, the information inputs of which are connected s with the outputs of the eleventh multiplier, the second group of inputs connected to the outputs of the eighth block of the initial installation, the outputs of the sixth delay element are connected to the first group of information inputs of the second adder, the second group of information inputs of which are connected to the outputs of the seventh delay element, the information inputs of which are connected to the outputs of the sixth a multiplier, the second group of information inputs of which are connected to the outputs of the fourth block of the initial installation and the second group of inputs of the eighth multiply Spruce, the outputs of which are connected to the information inputs of the ninth delay element, the outputs of which are connected to the fourth group of information inputs of the second adder, the third group of information inputs of which is connected to the outputs of the eighth delay element, the information inputs of which are connected to the outputs of the seventh multiplier, the second group of information inputs of which is connected with the outputs of the fifth block of the initial installation, the fifth group of information inputs of the second adder is connected to the outputs of the tenth element of the back arches, and the outputs are connected to the second group of inputs of the tenth multiplier, the first group of inputs of which is connected to the outputs of the seventh unit of the initial installation, and the outputs are connected to the information inputs of the eleventh delay element, the outputs of which are connected to the second group of information inputs of the third adder, the outputs of which are connected to the second the group of inputs of the twelfth multiplier, the first group of inputs of which is connected to the outputs of the ninth block of the initial installation, and the outputs are connected to the outputs of the shaper coefficients The second derivative is g ² _n , and the control inputs of the first, second and third adders, the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, twelfth, thirteenth and fourteenth delay elements are combined and connected to the second input of the shaper coefficients of the second derivative g ² _n .  3. The differentiation device according to claim 1, characterized in that the B-spline forming unit is made comprising first, second, third and fourth elements of the initial installation, first, second, third, fourth, fifth, sixth and seventh multipliers, first, second, the third, fourth, fifth, sixth, seventh and eighth adders, the first, second, third, fourth, fifth and sixth elements of raising to the fifth degree, the converter into an additional code, the first, second, third, fourth, fifth and sixth delay elements, and first group of inputs first the first multiplier is connected to the first group of inputs of the B-spline forming unit, the second group of inputs is connected to the outputs of the fourth element of the initial installation, and the outputs are connected to the inputs of the converter in an additional code, the first group of information inputs of the first adder and the inputs of the first element of raising to the fifth power, outputs which are connected to the first groups of inputs of the second and third multipliers and information inputs of the third delay element, the outputs of which are connected to the first group of outputs of the block a B-spline, the second group of outputs connected to the outputs of the fourth delay element, the information inputs of which are connected to the outputs of the fifth adder, the second group of information inputs of which are connected to the outputs of the second raising element to the fifth degree and the first group of inputs of the fourth multiplier, and the first group of information the inputs are connected to the outputs of the third multiplier, the second group of inputs of which is connected to the outputs of the second element of the initial installation and second groups of inputs of the fourth, fifth of the sixth multiplier, the outputs of which are connected to the second group of information inputs of the eighth adder, and the first group of inputs is connected to the outputs of the fourth element of raising to the fifth degree, the first group of inputs of the seventh multiplier and the information inputs of the sixth delay element, the outputs of which are connected to the sixth group of outputs of the block forming a B-spline, the fifth group of outputs of which is connected to the outputs of the fifth delay element, the information inputs of which are connected to the outputs of the eighth adder, the first the group of information inputs of which is connected to the outputs of the third element of raising to the fifth degree and the first group of inputs of the fifth multiplier, the outputs of which are connected to the second group of information inputs of the seventh adder, the third group of information inputs of which are connected to the outputs of the second delay element, the information inputs of which are connected to the outputs of the seventh a multiplier, the second group of inputs of which is connected to the outputs of the first element of the initial installation and the second group of inputs of the second multiplier, the output which is connected to the information inputs of the first delay element, the outputs of which are connected to the first group of information inputs of the sixth adder, the second group of information inputs of which are connected to the outputs of the fourth multiplier, the third group of information inputs - with the outputs of the fifth element of raising to the fifth degree, and the outputs are connected to the third the group of outputs of the B-spline forming unit, the fourth group of outputs of which is connected to the outputs of the seventh adder, the first group of information inputs of which dinene with the outputs of the sixth element of raising to the fifth degree, the inputs of which are connected to the outputs of the fourth adder, the second group of information inputs of which are connected to the outputs of the third element of the initial installation, the second groups of information inputs of the first, second and third adders, and the first group of information inputs connected to the inputs the third element of raising to the fifth power and the outputs of the second adder, the first group of information inputs of which are connected to the outputs of the Converter in additional the fourth code and the inputs of the fourth element of raising to the fifth degree, and the control input is connected to the control inputs of the third, fourth, fifth, sixth, seventh and eighth adders, the control inputs of the first, second, third, fourth, fifth and sixth delay elements, the second block input the formation of the B-spline and the control input of the first adder, the outputs of which are connected to the inputs of the second element of raising to the fifth degree and the first group of information inputs of the third adder, the outputs of which are connected to the input the fifth element of raising to the fifth degree.  4. The differentiation device according to claim 1, characterized in that the local spline forming unit is made comprising first, second, third, fourth, fifth and sixth multipliers, first, second, third, fourth and fifth delay elements, an adder and a register, the second the groups of inputs of the first, second, third, fourth, fifth and sixth multipliers are combined and connected to the first group of inputs of the local spline forming unit, the first group of inputs of the first multiplier is connected to the eighth group of inputs of the local forming unit spline, and the outputs are connected to the first group of information inputs of the adder, the second group of information inputs of which are connected to the outputs of the first delay element, the information inputs of which are connected to the outputs of the second multiplier, the first group of inputs of which is connected to the seventh group of inputs of the local spline forming unit, the sixth group the inputs of which are connected to the first group of inputs of the third multiplier, the outputs of which are connected to the information inputs of the second delay element, the outputs of which are connected inens with the third group of information inputs of the adder, the fourth group of information inputs of which is connected to the outputs of the third delay element, the information inputs of which are connected to the outputs of the fourth multiplier, the first group of inputs of which is connected to the fifth group of inputs of the local spline forming unit, the fourth group of inputs of which are connected to the first the group of inputs of the fifth multiplier, the outputs of which are connected to the information inputs of the fourth delay element, the outputs of which are connected to the fifth a solder of information inputs of the adder, the sixth group of information inputs of which is connected to the outputs of the fifth delay element, the information inputs of which are connected to the outputs of the sixth multiplier, the first group of inputs of which is connected to the third group of inputs of the local spline forming unit, the second input of which is connected to the control inputs of the first, second , the third, fourth and fifth delay elements, the adder and the register, the information inputs of which are connected to the outputs of the adder, and the outputs are connected to the output and forming unit a local spline.

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