RU2143724C1 - Device for differentiation - Google Patents

Abstract

FIELD: automation and computer engineering. SUBSTANCE: device has g1n coefficients generator 1, local spline generator 2, B-spline generator 3. EFFECT: increased precision of differentiation of functions with continuous seventh-order derivative. 4 cl, 7 dwg

Description

 The invention relates to automation and computer engineering and can be used in the construction of systems including differentiation operations.

 Known devices (USSR AS N 1233152 G 06 F 7/70 from 05.23.86, USSR AS N 1187182 G 06 F 7/18 from 10.23.85) allow differentiation, but have low accuracy due to incomplete accounting of information about the smoothness of the differentiable process.

 Closest to the claimed device in its technical essence is a differentiation device, which is part of the device for estimating the carrier frequency (Patent RU 2100812, published December 27, 1997, Bull. N 12, paragraph 13 of the claims, Fig. 16, p. 89).

The prototype device contains a coefficient generator g _n ¹ , the first group of inputs of which is the first group of inputs of the differentiation unit, a cubic B-spline forming unit and a local cubic spline forming unit, the first group of inputs of which is connected to the outputs of the coefficient generator, the sixth input is combined with the second input coefficient shaper and is the second input of the differentiation unit, the outputs are the outputs of the differentiation unit, and the second, third, fourth and fifth groups of inputs in are connected respectively with the fourth, third, second and first groups of outputs of the cubic B-spline forming unit, the inputs of which are the third group of inputs of the differentiation unit.

The known technical solution has insufficient accuracy of differentiation of the function, which is characterized by an error equal to [1]
μ ₁ = const ₁ • h ⁴ • f $\genfrac{}{}{0ex}{}{\text{(5)}}{\text{max}}$ , (1)
where f _max ⁽⁵⁾ is the maximum of the fifth derivative of the function f (x);
h is the distance between the samples of the function f (x).

Moreover, this accuracy is ensured for functions having a continuous sixth derivative (f (x) ∈ C ⁶ ). When differentiating functions having a continuous seventh derivative (f (x) ∈ C ⁷ ), information on the smoothness of functions is not fully taken into account in this device, as a result of which the prototype does not provide the necessary accuracy.

The aim of the invention is to develop a device that provides more, high accuracy of differentiation of functions having a continuous seventh derivative (f (x) ∈ C ⁷ ).
This goal is achieved by the fact that in the known differentiation device containing the shaper coefficients g _n ¹ , a local spline forming unit and a B-spline forming unit, the first group of inputs of the coefficient shaper g _n ¹ is the first input information bus of the differentiation device, and the second input of the shaper of the coefficients g _n ^{1 is} combined with the seventh input of the local spline forming unit and is the input clock bus of the differentiation device, and the outputs of the coefficient shaper Entries g _n ^{1 are} connected to the first group of inputs of the local spline forming unit, the outputs of which are the output bus of the differentiation device, and the second, third, fourth and fifth groups of inputs are connected respectively to the first, second, third and fourth groups of outputs of the B-spline forming unit, the first group of inputs of which is the second input information bus of the differentiation device, the second input of the factor shaper g _n ^{1 is} connected to the second input of the B-spline forming unit. The fifth group of outputs of the B-spline forming unit is connected to the sixth group of inputs of the local spline forming unit.

The coefficient generator g _n ^{1 is} made containing the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh and twelfth multipliers, the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, the tenth, eleventh and twelfth elements of the initial installation, the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth and eleventh delay elements and the first, second and third adders. The first groups of inputs of the first, second, third, fourth, fifth, sixth, seventh, eighth and eleventh multipliers, the information inputs of the fifth and ninth delay elements and the first group of information inputs of the first adder are combined with the first group of inputs of the generator of coefficients g _n ¹ . The second group of inputs of the first multiplier is connected to the outputs of the first element of the initial installation. The outputs of the first multiplier are connected to the second group of information inputs of the first adder. The third group of information inputs of the first adder is connected to the outputs of the first delay element. The information inputs of the first delay element are connected to the outputs of the second multiplier. The second group of inputs of the second multiplier is connected to the outputs of the second element of the initial installation. The second group of inputs of the third multiplier is connected to the outputs of the third element of the initial installation, and the outputs are connected to the information inputs of the second delay element. The outputs of the second delay element are connected to the fourth group of information inputs of the first adder. The fifth group of information inputs of the first adder is connected to the outputs of the third delay element. The information inputs of the third delay element are connected to the outputs of the fourth multiplier. The second group of inputs of the fourth multiplier is connected to the outputs of the fourth element of the initial installation. The second group of information inputs of the fifth multiplier is connected to the outputs of the fifth block of the initial installation. The outputs of the fifth multiplier are connected to the information inputs of the fourth delay element. The outputs of the fourth delay element are connected to the sixth group of information inputs of the first adder. The outputs of the first adder are connected to the second group of inputs of the ninth multiplier. The first group of inputs of the ninth multiplier is connected to the outputs of the ninth element of the initial installation. The outputs of the ninth multiplier are connected to the first group of information inputs of the third adder. The third group of information inputs of the third adder is connected to the outputs of the ninth delay element. The fourth group of information inputs of the third adder is connected to the outputs of the eleventh delay element. The information inputs of the eleventh delay element are connected to the outputs of the eleventh multiplier. The second group of inputs of the eleventh multiplier is connected to the outputs of the eleventh element of the initial installation. The second group of information inputs of the third adder is connected to the outputs of the tenth delay element. The information inputs of the tenth delay element are connected to the outputs of the tenth multiplier. The second group of inputs of the tenth multiplier is connected to the outputs of the tenth element of the initial installation. The first group of inputs of the tenth multiplier is connected to the outputs of the second adder, the first group of information inputs of the second adder is connected to the outputs of the fifth delay element. The second group of information inputs of the second adder is connected to the outputs of the sixth delay element. The information inputs of the sixth delay element are connected to the outputs of the sixth multiplier. The second group of inputs of the sixth multiplier is connected to the outputs of the sixth element of the initial installation. The second group of inputs of the seventh multiplier is connected to the outputs of the seventh element of the initial installation. The outputs of the seventh multiplier are connected to the information inputs of the seventh delay element. The outputs of the seventh delay element are connected to a third group of information inputs of the second adder. The fourth group of information inputs of the second adder is connected to the outputs of the eighth delay element. The information inputs of the eighth delay element are connected to the outputs of the eighth multiplier. The second group of information inputs of the eighth multiplier is connected to the outputs of the eighth element of the initial installation. The control inputs of the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth and eleventh delay elements, the first, second and third adders are combined and connected to the second input of the factor generator g _n ¹ . The outputs of the third adder are connected to the second group of inputs of the twelfth multiplier. The first group of inputs of the twelfth multiplier is connected to the outputs of the twelfth element of the initial installation. The outputs of the twelfth multiplier are the outputs of the shaper coefficients g _n ¹ .

 The B-spline forming unit is made comprising first, second, third and fourth multipliers, an additional code conversion unit, first, second, third, fourth, fifth and sixth adders, first, second, third, fourth and fifth fourth degree raising blocks, the first, second, third, fourth and fifth delay elements and the first, second, third, fourth and fifth blocks of the initial installation. The first group of inputs of the first multiplier is connected to the first group of inputs of the B-spline forming unit. The second group of inputs of the first multiplier is connected to the outputs of the fifth element of the initial installation. The outputs of the first multiplier are connected to the inputs of the first fourth degree block, the first group of information inputs of the first adder, the first group of information inputs of the second adder and the inputs of the conversion unit to the additional code. The outputs of the conversion unit to the additional code are connected to the first group of information inputs of the third adder and the inputs of the fifth block of raising to the fourth degree. The outputs of the fifth fourth degree block are connected to the information inputs of the fifth delay element and the first group of inputs of the fourth multiplier. The second group of inputs of the fourth multiplier is connected to the outputs of the first element of the initial installation and the second group of inputs of the third multiplier. The first group of inputs of the third multiplier is connected to the outputs of the first block raising to the fourth degree, the information inputs of the fourth delay element and the first group of inputs of the second multiplier. The second group of inputs of the second multiplier is connected to the outputs of the second element of the initial installation. The outputs of the second multiplier are connected to the first group of information inputs of the fifth adder. The third group of information inputs of the fifth adder is connected to the outputs of the fourth multiplier and the second group of information inputs of the sixth adder. The first group of information inputs of the sixth adder is connected to the outputs of the third delay element. The outputs of the sixth adder are connected to the fourth group of outputs of the B-spline forming unit. The first group of outputs of the B-spline forming unit is connected to the outputs of the fourth delay element. The fifth group of outputs of the B-spline forming unit is connected to the outputs of the fifth delay element. The outputs of the fourth element of the initial installation are connected to the second group of information inputs of the third adder and the second group of information inputs of the second adder. The outputs of the second adder are connected to the inputs of the third block raising to the fourth degree. The outputs of the third fourth degree block are connected to the information inputs of the second delay element. The outputs of the second delay element are connected to the second group of information inputs of the fourth adder. The first group of inputs of the fourth adder is connected to the outputs of the third multiplier. The outputs of the fourth adder are connected to the second group of outputs of the B-spline forming unit. The third group of outputs of the B-spline forming unit is connected to the outputs of the fifth adder. The second group of information inputs of the fifth adder is connected to the outputs of the first delay element. The information inputs of the first delay element are connected to the outputs of the second fourth degree block. The inputs of the second block raising to the fourth degree are connected to the outputs of the first adder. The second group of inputs of the first adder is connected to the outputs of the third element of the initial installation. The outputs of the third adder are connected to the inputs of the fourth block raising to the fourth degree. The outputs of the fourth fourth degree block are connected to the information inputs of the third delay element. The control input of the third delay element is combined with the control inputs of the first, second, fourth and fifth delay elements, the first, second, third, fourth, fifth and sixth adders and the second input of the B-spline forming unit. The local spline forming unit is made containing the first, second, third, fourth and fifth multipliers, the first, second, third and fourth delay elements, an adder and a register. The second groups of inputs of the first, second, third, fourth and fifth multipliers are combined and connected to the first group of inputs of the local spline forming unit. The first groups of inputs of the fifth, fourth, third, second and first multipliers are respectively connected to the sixth, fifth, fourth, third and second groups of inputs of the local spline forming unit. The outputs of the first multiplier are connected to the first group of information inputs of the adder. The second group of information inputs of the adder is connected to the outputs of the first delay element. The information inputs of the first delay element are connected to the outputs of the second multiplier. The outputs of the third multiplier are connected to the information inputs of the second delay element. The outputs of the second delay element are connected to the third group of information inputs of the adder. The fourth group of information inputs of the adder is connected to the outputs of the third delay element. The information inputs of the third delay element are connected to the outputs of the fourth multiplier. The outputs of the fifth multiplier are connected to the information inputs of the fourth delay element. The outputs of the fourth delay element are connected to the fifth group of information inputs of the adder. The control input of the fourth delay element is combined with the control inputs of the first, second and third delay elements, the adder and the register. Information inputs of the register are connected to the outputs of the adder. The outputs of the register are connected to the outputs of the local spline forming unit.

The listed new set of essential features of the claimed device provides a higher accuracy of differentiation of functions having a continuous seventh derivative (f (x) ∈ C ⁷ ). This is achieved by the fact that the device takes into account a priori information about the degree of smoothness of the function.

(2)
где g_n = [z_n+1 - z_n - (z_n+2 - 3z_n+1 + 3z_n - z_n-1)/4 + 13(z_n+3 - 5z_n+2 + 10z_n+1 - 10z_n + 5z_n-1 - z_2-n)/240]/h; (3)
z_n - n-й отсчет функции f(x);
τ = m•τ_o;
m = 1, 2,..., M;
M - количество точек дифференцирования;
τ_o∈ [-0,5, 0,5].
Реализация (2) в виде устройства позволяет вычислять производные функций f(x) ∈ C⁷ с точностью, определяемой погрешностью [2]
μ₂= const₂•h⁵•f $\genfrac{}{}{0ex}{}{\text{(6)}}{\text{max}}$ , (4)
где f_max ⁽⁶⁾ - максимум шестой производной функции f(x).So, from [1, 2] it is known that for differentiating a function with splines of a minimal fourth-degree template, one can obtain calculated expressions. As an implementation of a device for a single differentiation in accordance with the method of estimating the carrier frequency and a device for its implementation (patent RU 2100812 C1, published 12.27.97, Bull. N 36, S. 29-32, expressions (15-24)) and article, described in [2], we consider a fourth-degree spline. For him, m = 5, so r = 4 (the largest even number less than m). Therefore, to calculate the first derivative (s = 1) based on the given sources, we can obtain the following expression:

(2)
where g _n = [z _{n + 1} - z _n - (z _{n + 2} - 3z _{n + 1} + 3z _n - z _n-1 ) / 4 + 13 (z _{n + 3} - 5z _{n + 2} + 10z _{n + 1} - 10z _n + 5z _n-1 - z _2-n) / 240] / h; (3)
z _n is the n-th sample of the function f (x);
τ = m • τ _o ;
m = 1, 2, ..., M;
M is the number of differentiation points;
τ _o ∈ [-0.5, 0.5].
Implementation of (2) in the form of a device allows us to calculate the derivatives of functions f (x) ∈ C ⁷ with an accuracy determined by the error [2]
μ ₂ = const ₂ • h ⁵ • f $\genfrac{}{}{0ex}{}{\text{(6)}}{\text{max}}$ , (4)
where f _max ⁽⁶⁾ is the maximum of the sixth derivative of the function f (x).

The accuracy of the prototype device is not better than that given in expression (1). Therefore, for example, for functions f ∈ C ⁷ with h = 0.1 and in the case const ₁ • f _max ⁽⁵⁾ ≈ const ₂ • f _max ^{(6), the} gain μ ₁ / μ ₂ can reach a value of ten.

The claimed device is illustrated by drawings, in which:
in FIG. 1 shows a structural diagram of the claimed device;
in FIG. 2 is a structural diagram of a shaper of coefficients g _n ¹ ;
in FIG. 3 is a structural diagram of a block for generating B-spline parameters;
in FIG. 4 is a structural diagram of a block for forming a local spline;
in FIG. 5 shows one possible implementation of the delay element;
in FIG. 6 shows an embodiment of an initial setup element;
in FIG. 7 shows a variant of the implementation of the element of raising to the fourth degree.

The differentiation device shown in FIG. 1, consists of a factor generator g _n ¹ 1, a local spline forming unit 2, and a B-spline forming unit 3. The first group of inputs of the coefficient shaper g _n ¹ 1 is the first input information bus of the differentiation device. The second input of the shaper coefficients g _n ¹ 1 is the input clock bus of the differentiation device. The outputs of the shaper coefficients g _n ¹ 1 are connected to the first group of inputs of the block forming the local spline 2. The outputs of the block forming the local spline 2 are the output bus of the differentiation device. The second, third, fourth and fifth groups of inputs of the local spline forming unit 2 are connected respectively to the first, second, third and fourth group of outputs of the B-spline forming unit 3. The first group of inputs of the B-spline forming unit 3 is the second input information bus of the differentiation device. The local spline forming unit 2 is equipped with a seventh input, which is connected to the second input of the coefficient former g _n ¹ 1 and to the second input of the B-spline forming unit 3. The fifth group of outputs of the B-spline forming unit 3 is connected to the sixth group of inputs of the local spline forming unit 2 .

The coefficient generator g _n ¹ 1 shown in FIG. 2, consists of the first 11, second 13, third 16, fourth 19, fifth 112, sixth 116, seventh 119, eighth 122, ninth 128, tenth 130, eleventh 133 and twelfth 138 multipliers, first 12, second 15, third 18, fourth 111, fifth 114, sixth 118, seventh 121, eighth 124, ninth 127, tenth 129, eleventh 135 and twelfth 137 elements of the initial setup, the first 14, second 17, third 110, fourth 113, fifth 115, sixth 117, seventh 120 , eighth 123, ninth 132, tenth 131 and eleventh 134 delay elements, first 125, second 126 and third 136 s mmatorov. The first groups of inputs of the first 11, second 13, third 16, fourth 19, fifth 112, sixth 116, seventh 119, eighth 122 and eleventh 133 multipliers, information inputs of the fifth 115 and ninth 132 delay elements and the first group of information inputs of the first adder 125 are combined with the first group of inputs of the shaper coefficients g _n ¹ 1. The second group of inputs of the first multiplier 11 is connected to the outputs of the first element of the initial installation 12. The outputs of the first multiplier 11 are connected to the second group of information inputs of the first adder 125. Third the ith group of information inputs of the first adder 125 is connected to the outputs of the first delay element 14. The information inputs of the first delay element 14 are connected to the outputs of the second multiplier 13. The second group of inputs of the second multiplier 13 is connected to the outputs of the second element of the initial setup 15. The second group of inputs of the third multiplier 16 is connected with the outputs of the third element of the initial setup 18, and the outputs are connected to the information inputs of the second delay element 17. The outputs of the second delay element 17 are connected to the fourth group oh the information inputs of the first adder 125. The fifth group of information inputs of the first adder 125 is connected to the outputs of the third delay element 110. The information inputs of the third delay element 110 are connected to the outputs of the fourth multiplier 19. The second group of inputs of the fourth multiplier 19 is connected to the outputs of the fourth element of the initial setup 111. The second group of information inputs of the fifth multiplier 112 is connected to the outputs of the fifth element of the initial installation 114. The outputs of the fifth multiplier 112 are connected to the information input the fourth delay element 113. The outputs of the fourth delay element 113 are connected to the sixth group of information inputs of the first adder 125. The outputs of the first adder 125 are connected to the second group of inputs of the ninth multiplier 128. The first group of inputs of the ninth multiplier 128 is connected to the outputs of the ninth initial setting element 127. Outputs the ninth multiplier 128 is connected to the first group of information inputs of the third adder 136. The third group of information inputs of the third adder 136 is connected to the outputs of the ninth back element levers 132. The fourth group of information inputs of the third adder 136 is connected to the outputs of the eleventh delay element 134. The information inputs of the eleventh delay element 134 are connected to the outputs of the eleventh multiplier 133. The second group of inputs of the eleventh multiplier 133 is connected to the outputs of the eleventh element of the initial setup 135. The second group of information inputs the third adder 136 is connected to the outputs of the tenth delay element 131. The information inputs of the tenth delay element 131 are connected to the outputs of the decimal about the multiplier 130. The second group of inputs of the tenth multiplier 130 is connected to the outputs of the tenth element of the initial setup 129. The first group of inputs of the tenth multiplier 130 is connected to the outputs of the second adder 126. The first group of information inputs of the second adder 126 is connected to the outputs of the fifth delay element 115. The second group of information the inputs of the second adder 126 is connected to the outputs of the sixth delay element 117. The information inputs of the sixth delay element 117 are connected to the outputs of the sixth multiplier 116. The second group of inputs the second multiplier 116 is connected to the outputs of the sixth element of the initial installation 118. The second group of inputs of the seventh multiplier 119 is connected to the outputs of the seventh element of the initial installation 121. The outputs of the seventh multiplier 119 are connected to the information inputs of the seventh delay element 120. The outputs of the seventh delay element 120 are connected to the third group of information the inputs of the second adder 126. The fourth group of information inputs of the second adder 126 is connected to the outputs of the eighth delay element 123. Information inputs of the eighth element This delay 123 is connected to the outputs of the eighth multiplier 122. The second group of information inputs of the eighth multiplier 122 is connected to the outputs of the eighth element of the initial setup 124. The control inputs of the first 14, second 17, third 110, fourth 113, fifth 115, sixth 117, seventh 120, eighth 123, 132 of the ninth, tenth and eleventh 131 delay elements 134 and first 125, second 126 and third 136 adders are combined and connected to the second input of the coefficient g _n ¹ 1. The outputs of the third adder 136 connected to a second group of inputs dvena tsatogo multiplier 138. The first group of inputs of the twelfth multiplier 138 is connected to the outputs of the twelfth element 137. The outputs of the initial installation of the twelfth multiplier 138 is the output of coefficient g _n ^{1 January.}

 The B-spline 3 parameter generating unit shown in FIG. 3, consists of the first 31, second 311, third 312 and fourth 316 multipliers, a converter to additional code 32, first 33, second 34, third 35, fourth 318, fifth 319 and sixth 320 adders, first 36, second 37, third 38 , fourth 39 and fifth 320 elements of raising to the fourth degree, the first 313, second 314, third 315, fourth 317 and fifth 312 delay elements, and the first 322, second 323, third 324, fourth 325 and fifth 326 elements of the initial installation. The first group of inputs of the first multiplier 31 is connected to the first group of inputs of the B-spline forming unit 3. The second group of inputs of the first multiplier 31 is connected to the outputs of the fifth element of the initial installation 326. The outputs of the first multiplier 31 are connected to the inputs of the first element of raising to the fourth degree 36, the first group information inputs of the first adder 33, the first group of information inputs of the second adder 34 and the inputs of the converter in the additional code 32. The outputs of the converter in the additional code 32 are connected to the first the group of information inputs of the third adder 35 and the inputs of the fifth element of raising to the fourth degree 310. The outputs of the fifth element of raising to the fourth degree 310 are connected to the information inputs of the fifth delay element 321 and the first group of inputs of the fourth multiplier 316. The second group of inputs of the fourth multiplier 316 is connected to the outputs of the first element of the initial installation 322 and the second group of inputs of the third multiplier 312. The first group of inputs of the third multiplier 312 is connected to the outputs of the first element of the construction in the fourth degree 36, by the information inputs of the fourth delay element 317 and the first group of inputs of the second multiplier 311. The second group of inputs of the second multiplier 311 is connected to the outputs of the second element of the initial installation 323. The outputs of the second multiplier 311 are connected to the first group of information inputs of the fifth adder 319. The third group of information inputs the fifth adder 319 is connected to the outputs of the fourth multiplier 318 and the second group of information inputs of the sixth adder 320. The first group of information inputs of the sixth adder 320 is connected inen with the outputs of the third delay element 315. The outputs of the sixth adder 320 are connected to the fourth group of outputs of the B-spline forming unit 3. The first group of outputs of the B-spline forming unit 3 is connected to the outputs of the fourth delay element 317. The fifth group of outputs of the B-spline forming unit 3 connected to the outputs of the fifth delay element 321. The outputs of the fourth element of the initial setup 325 are connected to the second group of information inputs of the third adder 35 and the second group of information inputs of the second adder 34. The outputs to of the third adder 34 are connected to the inputs of the third fourth degree element 38. The outputs of the third fourth degree element 38 are connected to the information inputs of the second delay element 314. The outputs of the second delay element 314 are connected to the second group of information inputs of the fourth adder 318. The first group of inputs of the fourth the adder 318 is connected to the outputs of the third multiplier 312. The outputs of the fourth adder 318 are connected to the second group of outputs of the B-spline forming unit 3. The third group of outputs of the block and the formation of the B-spline 3 is connected to the outputs of the fifth adder 319. The second group of information inputs of the fifth adder 319 is connected to the outputs of the first delay element 313. The information inputs of the first delay element 313 are connected to the outputs of the second raising element to the fourth degree 37. The inputs of the second raising element to the fourth degree 37 is connected to the outputs of the first adder 33. The second group of inputs of the first adder 33 is connected to the outputs of the third element of the initial installation 324. The outputs of the third adder 35 are connected to the odes of the fourth fourth degree raising element 39. The outputs of the fourth fourth degree raising element 39 are connected to the information inputs of the third delay element 315. The control input of the third delay element 315 is combined with the control inputs of the first 313, second 214, fourth 317 and fifth 321 delay elements, the first 33, second 34, third 35, fourth 318, fifth 319 and sixth 320 adders and the second input of the B-spline forming unit 3.

 The local spline forming unit 2 shown in FIG. 4, consists of the first 21, second 22, third 23, fourth 24 and fifth 25 multipliers, the first 26, second 27, third 28 and fourth 29 delay elements, adder 210 and register 211. The second group of inputs of the first 21, second 22, third 23, fourth 24 and fifth 25 multipliers are combined and connected to the first group of inputs of the local spline forming unit 2. The first groups of inputs of the fifth 25, fourth 24, third 23, second 22 and first 21 multipliers are respectively connected to the sixth, fifth, fourth, third and second groups of inputs of the forming unit I of the local spline 2. The outputs of the first multiplier 21 are connected to the first group of information inputs of the adder 210. The second group of information inputs of the adder 210 is connected to the outputs of the first delay element 26. The information inputs of the first delay element 26 are connected to the outputs of the second multiplier 22. The outputs of the third multiplier 23 are connected with the information inputs of the second delay element 27. The outputs of the second delay element 27 are connected to the third group of information inputs of the adder 210. The fourth group of information inputs the matrix 210 is connected to the outputs of the third delay element 28. The information inputs of the third delay element 28 are connected to the outputs of the fourth multiplier 24. The outputs of the fifth multiplier 25 are connected to the information inputs of the fourth delay element 29. The outputs of the fourth delay element 29 are connected to the fifth group of information inputs of the adder 210. The control input of the fourth delay element 29 is combined with the control inputs of the first 26, second 27 and third 28 delay elements, the adder 210 and the register 211. Information inputs regis pa 211 are connected to the outputs of the adder 210. Outputs of register 211 are connected to the outputs of a local spline forming unit 2.

 The claimed device operates as follows.

с первой, второй, третьей, четвертой и пятой групп выходов блока формирования В-сплайна 3. Далее в блоке формирования локального сплайна 2 про исходит умножение указанных значений на коэффициенты g_n ¹ и суммирование полученных произведений (см. выражение (2)). В результате на выходе устройства формируется значение производной функции f'(x).In the initial state, the parameter τ _o is supplied to the second information bus of the device. The clock bus receives clock pulses of the meander type, under the influence of which, upon receipt of the discrete values of the function f (x) on the first information bus, the unit 1 generates the values of the coefficients g _n ¹ . These values are alternately supplied to the first group of inputs of the local spline 2 forming unit. Corresponding values are supplied to the second, third, fourth, fifth and sixth groups of inputs of the last

from the first, second, third, fourth and fifth groups of outputs of the B-spline 3 forming unit. Next, in the local spline 2 forming unit, these values are multiplied by the coefficients g _n ¹ and the resulting products are summed (see expression (2)). As a result, the value of the derivative of the function f '(x) is formed at the output of the device.

The operation of the shaper coefficients g _n ^{1 is} carried out in accordance with the expression (3).

In the initial state, at the outputs of the first 12, second 15, third 18, fourth 111, fifth 114, sixth 118, seventh 121, eighth 124, ninth 127, tenth 129, eleventh 135 and twelfth 137 elements of the initial setting, number codes are generated, respectively: -5 , 10, -10, 5, -1, -3, 3, -1, 13/240, - 1/4, -1, 1/24. When applying to the second input of block 1 control pulses to the information input of block 1, the values of the function f (x) are received: z _n-2 , z _n-1 , ..., z _{n + 3} . The latter alternately follow: at the first inputs of the multipliers 11, 13, 16, 19, 112, 116, 119, 122 and 133, the inputs of the delay elements 115, 131 and 132 and the first information input of the adder 125. Elements 11 - 114 form five terms, which arrive at the information inputs of the adder 125 at the same time. The sixth term comes from the input of block 1 to the first information input of the adder 125 directly. The result of calculation in adder 125 is the value (z _{n + 3} - 5z _{n + 2} + 10z _{n + 1} - 10z _n + 5z _n-1 - z _n-2 ). Elements 115 - 124 form four terms for the adder 126. All four terms are served on the information inputs of the adder 126 at the same time. As a result of the addition operation, the values (z _{n + 2} - 3z _{n + 1} + 3z _n - z _n-1 ) are generated at the output of the adder 126. The value (z _{n + 3} - 5z _{n + 2} + 10z _{n + 1} - 10z _n + 5z _n-1 - z _n-2 ), multiplied by 13/240 in block 128, is the first term for adder 136. The second term is the value (z _{n + 2} - 3z _{n + 1} + 3z _n - z _n-1 ) multiplied in the multiplier 130 by the number - 1/4 and delayed in the delay element 131. The third term is the value z _{n + 1 of the} function f (x ) delayed in block 132. The fourth term is the value 2z of the function f (x) multiplied in block 133 by -1 and delayed in the delay element 134. The result of the summation operation in the adder 136 is multiplied in the multiplier 138 by the number 1/24. As a result, at the output of block 1, the desired value of the coefficient g _n ^{1 is formed} .

 One of the possible options for constructing delay elements 14, 17, 110, 113, 117, 120, 123, 131, 132 and 134 is shown in FIG. 5. The indicated blocks are of the same type. For delay elements 14, 115, 117 and 131 n = 2. For delay elements 17 and 120 n = 3. For delay elements 110 and 123 n = 4. For delay element 132 n = 8. For delay element 134 n = 6. It can be implemented on K155IR13 microcircuits.

 The elements included in the structural diagram of the claimed device are known and described, for example, in [3] - [7]. So, in [3] construction principles and examples of register implementation are described on p. 104-105 (can be implemented on the K155IR13 chip - p. 111 Fig. 1.78).

 The principle of operation of the multipliers is known and described in [4] on p.163-221. They can be implemented on the SN54284 and SN54285 microcircuits (see [4] p. 305, Fig. 6.3.12) or on the ADSP1016 microcircuit (see [5] p. 502, Table 7.4).

 The principle of operation of adders is known and described in [6] on p. 184-198. The full adder is described in [7] on p. 152, fig. 1.112 and p. 153, fig. 1.113. It can be implemented on the elements of EXCL. OR - K155LP5, AND - K155LI1, OR - from OR-NOT K155LE4 AND NOT K155LN1.

 One possible embodiment of the initial installation elements is shown in FIG. 6.

 Block forming a B-spline 3 works as follows.

Указанные величины поступают соответственно на второй, третий и четвертый выходы блока формирования В-сплайна 3. На первый и пятый выходы блока 3 подаются значения соответственно τ⁴ (с выходов элемента возведения в четвертую степень 36 через элемент задержки 317) и (1-τ)⁴ (с выходов элемента возведения в четвертую степень 310 через элемент задержки 321). Таким образом, указанные значения формируются на выходах блока 3 одновременно.In the initial state, at the outputs of the elements of the initial installation 322 - 325, codes of numbers are generated, respectively: -5, 10, 2, 1. At the output of the element of the initial installation 326, a code of the number m corresponding to the number of the differentiation point is generated. The control input of block 3 receives control signals from the device clock bus. The second information input of block 3 is fed with the value of τ _o . The indicated value goes to the first group of inputs of the multiplier 31, and to another group of its inputs - the value m from the output of the initial setting element 326. As a result of the multiplication operation, the values of τ = m • τ _{o are} formed at the outputs of the multiplier 31. The latter goes to the inputs of the converter in additional code 32, at the outputs of which we have the value (1-τ). The value τ c of the outputs of the multiplier 31 is also supplied to the first group of information inputs of the adders 33 and 34, and the value (1-τ) is sent to the first group of inputs of the adder 35. The code of the number 1 is supplied to the second groups of inputs of the adders 34 and 35, and the code of the number 2 is fed to the second group of the inputs of the adder 33. Values are generated at the outputs of the adders 33, 34, and 35, respectively, under the influence of the signals received via the clock bus (2 + τ) , (1 + τ) and (2-τ). The indicated values are supplied to the inputs of the corresponding elements of raising to the fourth degree 37, 38 and 39. To the inputs of the element of raising to the fourth degree 36, the value τ is supplied from the outputs of the multiplier 31. The inputs of the element of raising to the fourth degree 310 are (1-τ) from the output of the converter into the additional code 32. At the outputs of the fourth-degree raising elements 36, 37, 38, 39 and 310, we have the values τ ⁴ , (τ + 2) ⁴ , (τ + 1) ⁴ , (2-τ) ⁴ and (1, respectively -τ) ⁴ . The value of τ ⁴ from the outputs of the element of raising to the fourth power 36 is supplied to the first group of inputs of the multipliers 311 and 312. The code of the number 10 is supplied to the second group of inputs of the multiplier 311, and the code of the number -5 is sent to the second group of inputs of the multiplier 312. As a result of the multiplication operation, the outputs of the multipliers 311 and 312 generate values of 10τ ⁴ and -5τ ^4, respectively. The latter arrive at the first groups of information inputs of adders 319 and 318, respectively. The values of (τ + 1) ⁴ (via delay element 314) and (τ + 2) ⁴ (via delay element 313) are supplied to the second groups of information inputs of adders 318 and 319) . The value (1-τ) ⁴ from the outputs of the element of raising to the fourth power 310 goes to the first group of inputs of the multiplier 316, the second group of inputs of which the code of the number -5 is supplied. As a result of the multiplication operation, the values of -5 (1-τ) ^{4 are} generated at the outputs of the multiplier 316. The latter is fed to the second group of information inputs of the adder 320. The value (2-τ) of the ⁴ outputs of the fourth degree raising element 39 via the delay element 315 is supplied to the first group of information inputs of the adder 320. As a result of the summation operations in the elements 318, 319 and 320, the outputs of the latter have values, respectively

The indicated values are supplied respectively to the second, third and fourth outputs of the B-spline 3 forming unit. The values of τ ^4, respectively, are supplied to the first and fifth outputs of block 3 (from the outputs of the element of raising to the fourth power 36 through the delay element 317) and (1-τ) ⁴ (from the outputs of the fourth exponentiation 310 through the delay element 321). Thus, these values are formed at the outputs of block 3 at the same time.

 The principle of implementation of the converter into additional code 32 is known and described in [8] on p. 462 - 468. Can be implemented on K155LAZ, K155LP5, K155LE4 and K155LN1 microcircuits. Multipliers can be implemented on the SN54284 and SN54285 chips or on the ADSP1016 chip. Adders can be implemented on the elements of the ISKL. OR - K155LP5, AND - K155LI1, OR - from OR-NOT K155LE4 and NOT K155LN1. Elements of the initial installation are implemented in accordance with FIG. 6. One of the possible embodiments of the elements of raising to the fourth degree is shown in FIG. 7.

 The delay elements included in block 3 are implemented in accordance with FIG. 5, with n = 2 selected for elements 313 - 315, and n = 3 for elements 317 and 321.

с выхода умножителя 22 через элемент задержки 26 на второй информационный вход сумматора 210 - значение (1/24)g_n-1[(2-τ)⁴-5(1-τ)⁴], с выхода умножителя 23 через элемент задержки 27 на третий информационный вход сумматора 210 - значение (1/24)g_n[(τ+2)⁴-5(τ+1)⁴+10τ⁴], с выхода умножителя 24 через элемент задержки 28 на четвертый информационный вход сумматора 210 - значение (1/24)g_n+1[(1+τ)⁴-5τ⁴], с выхода умножителя 25 через элемент задержки 29 на четвертый информационный вход сумматора 210 - значение (1/24)g_n+2•τ⁴. Результат суммирования в сумматоре 210 - искомое значение производной функции f'(x) записывается в регистр 211 под воздействием импульса, подаваемого на его управляющий вход. Элементы задержки, входящие в состав блока 2, реализуются в соответствии с фиг. 5, причем для элемента 26 выбирается n = 2, для элемента 27 n = 3, для элемента 28 n = 4, для элемента 29 n = 5. Умножители могут быть реализованы на микросхемах SN54284 и SN54285 или на микросхеме ADSP1016. Сумматор можно реализовать на элементах ИСКЛ. ИЛИ - К155ЛП5, И - К155ЛИ1, ИЛИ - из ИЛИ-НЕ К155ЛЕ4 и НЕ К155ЛН1. Регистр можно реализовать на микросхеме К155ИР13.Block forming a local spline 2 operates as follows. From the output of block 1, the coefficients g _n ¹ simultaneously arrive at the first groups of inputs of the multipliers 21–25. The values of the spline B from the outputs of block 3 are sent to the second groups of inputs of the latter. As a result, from the output of the multiplier 21 to the first information input of the adder 210, the value

from the output of the multiplier 22 through the delay element 26 to the second information input of the adder 210 - the value (1/24) g _n-1 [(2-τ) ⁴ -5 (1-τ) ⁴ ], from the output of the multiplier 23 through the delay element 27 to the third information input of adder 210 - the value (1/24) g _n [(τ + 2) ⁴ -5 (τ + 1) ⁴ + 10τ ⁴ ], from the output of the multiplier 24 through the delay element 28 to the fourth information input of the adder 210 - value (1/24) g _{n + 1} [(1 + τ) ⁴ -5τ ⁴ ], from the output of the multiplier 25 through the delay element 29 to the fourth information input of the adder 210 - the value (1/24) g _{n + 2} • τ ⁴ . The result of the summation in the adder 210 - the desired value of the derivative of the function f '(x) is recorded in the register 211 under the influence of a pulse supplied to its control input. The delay elements included in block 2 are implemented in accordance with FIG. 5, with n = 2 selected for element 26, n = 3 for element 27, n = 4 for element 28, and n = 5 for element 29. Multipliers can be implemented on SN54284 and SN54285 microcircuits or on ADSP1016 microcircuit. The adder can be implemented on the elements of the ESCL. OR - K155LP5, AND - K155LI1, OR - from OR-NOT K155LE4 and NOT K155LN1. The register can be implemented on the chip K155IR13.

Literature
1. Zheludev V. A. Restoration of functions and their derivatives from grid data with an error using local splines. // Journal of Computational Mathematics and Mathematical Physics. -1987. - Volume 27. - N 1. - S. 22-34.

 2. Zheludev V. A. Local spline approximation on a uniform grid. // Journal of Computational Mathematics and Mathematical Physics. - 1987.- Volume 27. -N 9. -C. 1296-1310.

 3. V.L. Awl. Popular digital circuits. Directory. - M.: Radio and Communications, 1988.

 4. M.A. Kartsev, V.A. Brick. Computing systems and synchronous arithmetic. - M.: Radio and Communications, 1981.

 5. D. Givone, R. Rosset. Microprocessors and microcomputers: Introductory course: Trans. from English - M.: Mir, 1983.

 6. V. L. Shilo. Popular digital circuits. Directory. 2nd ed., Rev. - Chelyabinsk: Metallurgy, 1989.

 8. L.M. Goldenberg. Pulse and digital devices. M .: Communication, 1973.

Claims (4)

1. Differentiation device containing a shaper of coefficients g ¹ n, a local spline forming unit and a B-spline forming unit, the first group of inputs of the shaper g ¹ n being the first input information bus of the differentiating device, and the second input of the coefficient shaper g ¹ n combined with seventh input unit form a local input spline and a bus clock derivation device, and outputs shaper coefficients g ¹ n are connected to the inputs of the first group unit forming a local spline, the outputs of which are the output bus of the differentiation device, and the second, third, fourth and fifth groups of inputs are connected respectively to the first, second, third and fourth group of outputs of the B-spline forming unit, the first group of inputs of which is the second input information bus of the device differentiation, characterized in that the second input of the shaper coefficients g ¹ n connected to the second input of the block forming a B-spline, the fifth group of outputs of which is connected to the sixth group of inputs of the block forming the local spline. 2. The differentiation device according to claim 1, characterized in that the shaper coefficients g ¹ n is made containing the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh and twelfth multipliers, the first, second, third , fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh and twelfth elements of the initial installation, first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth and eleventh delay elements and the first, second and third adders, with the first r uppy inputs of the first, second, third, fourth, fifth, sixth, seventh, eighth and eleventh multipliers, data inputs of the fifth and the ninth delay elements and the first group of information inputs of the first adder are combined with the first group of inputs shaper coefficients g ¹ n, a second group of first inputs the multiplier is connected to the outputs of the first element of the initial installation, and the outputs are connected to the second group of information inputs of the first adder, the third group of information inputs of which are connected to the output the first delay element, the information inputs of which are connected to the outputs of the second multiplier, the second group of inputs of which is connected to the outputs of the second initial setup element, the second group of inputs of the third multiplier is connected to the outputs of the third initial setup block, and the outputs are connected to the information inputs of the second delay element, outputs which is connected to the fourth group of information inputs of the first adder, the fifth group of information inputs of which is connected to the outputs of the third back element a rzhka whose information inputs are connected to the outputs of the fourth multiplier, the second group of inputs of which is connected to the outputs of the fourth element of the initial installation, the second group of information inputs of the fifth multiplier is connected to the outputs of the fifth element of the initial installation, and the outputs are connected to the information inputs of the fourth delay element, the outputs of which are connected with the sixth group of information inputs of the first adder, the outputs of which are connected to the second group of inputs of the ninth multiplier, the first group of inputs which is connected to the outputs of the ninth element of the initial installation, and the outputs are connected to the first group of information inputs of the third adder, the third group of information inputs of which are connected to the outputs of the ninth delay element, the fourth group of information inputs is connected to the outputs of the eleventh delay element, information inputs of which are connected to the outputs of the eleventh a multiplier, the second group of inputs of which is connected to the outputs of the eleventh element of the initial installation, and the second group of information the inputs of the third adder is connected to the outputs of the tenth delay element, the information inputs of which are connected to the outputs of the tenth multiplier, the second group of inputs of which is connected to the outputs of the tenth element of the initial setup, and the first group of inputs is connected to the outputs of the second adder, the first group of information inputs of which is connected to the outputs of the fifth delay element, the second group of information inputs is connected to the outputs of the sixth delay element, the information inputs of which are connected to the outputs of the sixth multiply an amplifier, the second group of inputs of which is connected to the outputs of the sixth element of the initial installation, the second group of inputs of the seventh multiplier is connected to the outputs of the seventh element of the initial installation, and the outputs are connected to the information inputs of the seventh delay element, the outputs of which are connected to the third group of information inputs of the second adder, the fourth group the information inputs of which are connected to the outputs of the eighth delay element, the information inputs of which are connected to the outputs of the eighth multiplier, the second group pa information inputs which is connected to the outputs of the eighth element of the initial installation, the control inputs of the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth and eleventh delay elements, the first, second and third adders are combined and connected to the second input coefficient shaper g ¹ n, and the outputs of the third adder are connected to the second group of inputs of the twelfth multiplier, the first group of inputs of which are connected to the outputs of the twelfth element of the initial installation, and the outputs are the outputs of the shaper coefficients g ¹ n.  3. The differentiation device according to claim 1, characterized in that the B-spline forming unit is made up of first, second, third and fourth multipliers, a converter into an additional code, first, second, third, fourth, fifth and sixth adders, first, second , the third, fourth and fifth elements of raising to the fourth degree, the first, second, third, fourth and fifth delay elements, the first, second, third, fourth and fifth elements of the initial installation, the first group of inputs of the first multiplier connected to the first group of input the odes of the B-spline forming unit, the second group of inputs is with the outputs of the fifth element of the initial installation, and the outputs are connected to the inputs of the first element of raising to the fourth degree, the first group of information inputs of the first adder, the first group of information inputs of the second adder and the inputs of the converter the outputs of which are connected to the first group of information inputs of the third adder and the inputs of the fifth element of raising to the fourth degree, the outputs of which are connected to information inputs the fifth delay element and the first group of inputs of the fourth multiplier, the second group of inputs of which is connected to the outputs of the first element of the initial installation and the second group of inputs of the third multiplier, the first group of inputs of which is connected with the outputs of the first element of raising to the fourth degree, the information inputs of the fourth delay element and the first group the inputs of the second multiplier, the second group of inputs of which is connected to the outputs of the second element of the initial installation, and the outputs are connected to the first group of information the inputs of the fifth adder, the third group of information inputs of which are connected to the outputs of the fourth multiplier and the second group of information inputs of the sixth adder, the first group of information inputs of which is connected to the outputs of the third delay element, and the outputs are connected to the fourth group of outputs of the B-spline forming unit, the first group the outputs of which are connected to the outputs of the fourth delay element, and the fifth group of outputs - with the outputs of the fifth delay element, the outputs of the fourth element of the initial installation and connected to the second group of information inputs of the third adder and the second group of information inputs of the second adder, the outputs of which are connected to the inputs of the third element of raising to the fourth degree, the outputs of which are connected to the information inputs of the second delay element, the outputs of which are connected to the second group of information inputs of the fourth adder, the first group of inputs of which is connected to the outputs of the third multiplier, and the outputs are connected to the second group of outputs of the B-spline forming unit, third the group of outputs of which is connected to the outputs of the fifth adder, the second group of information inputs of which is connected to the outputs of the first delay element, the information inputs of which are connected to the outputs of the second element of raising to the fourth degree, the inputs of which are connected to the outputs of the first adder, the second group of inputs of which is connected to the outputs of the third element of the initial installation, the outputs of the third adder are connected to the inputs of the fourth element of raising to the fourth degree, the outputs of which are connected to inform tional inputs of the third delay element, a control input of which is combined with the control inputs of the first, second, fourth and fifth delay elements, first, second, third, fourth, fifth and sixth adders, and a second input unit for generating a B-spline.  4. The differentiation device according to claim 1, characterized in that the local spline forming unit is made comprising first, second, third, fourth and fifth multipliers, first, second, third and fourth delay elements, an adder and a register, the second input groups of the first, the second, third, fourth and fifth multipliers are combined and connected to the first group of inputs of the local spline forming unit, the first groups of inputs of the fifth, fourth, third, second and first multipliers are respectively connected to the sixth, fifth, h the third, second and second groups of inputs of the local spline forming unit, and the outputs of the first multiplier are connected to the first group of information inputs of the adder, the second group of information inputs of which are connected to the outputs of the first delay element, the information inputs of which are connected to the outputs of the second multiplier, the outputs of the third multiplier are connected to information inputs of the second delay element, the outputs of which are connected to the third group of information inputs of the adder, the fourth group of information inputs the ode of which is connected to the outputs of the third delay element, the information inputs of which are connected to the outputs of the fourth multiplier, and the outputs of the fifth multiplier are connected to the information inputs of the fourth delay element, the outputs of which are connected to the fifth group of information inputs of the adder, and the control input is combined with the control inputs of the first, second and the third delay elements, the adder and the register, the information inputs of which are connected to the outputs of the adder, and the outputs are connected to the outputs of the forming unit local spline.

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