RU2132568C1 - Interpolator - Google Patents

Abstract

FIELD: computer engineering, in particular, modeling non-linear functions of single variable. SUBSTANCE: device has clock bus, starting bus, information bus, setting buses, counter, memory unit, commutators, additional code converter, multipliers, registers, delay gates, adders, fourth power raising unit, control unit, which has RS flip-flop, counter, comparison units, and AND gates. EFFECT: increased precision of interpolation for functions with continuous sixth derivative. 2 cl, 3 dwg

Description

 The invention relates to computing, in particular to devices for implementing functions, and can be used to reproduce nonlinear dependencies of one variable.

 Known devices (USSR AS N 1405074 G 06 F 15/353 of 10/27/1986, USSR AS N 1686461 Q 06 F 15/353 of 02/13/1989) allow reproducing a wide class of functional dependencies, but have low accuracy.

 Closest to the claimed device in its technical essence is the "Interpolator" (USSR AS N 1405074 G 06 F 15/353 of 10/27/1986), selected as the prototype device.

 The prototype device contains an accumulating adder, a multiplier, the first and second memory blocks, a switch, an additional code converter, a counter and a register, the output of which is connected to the first information input of the switch, the output of the first bit of the register connected to the control input of the switch, the second information input of which connected to the output of the converter in an additional code, the input of which is connected to the output of the register, the information input of which is the input of the least significant bits of the interpolator argument, in the course of the upper bits of which is connected to the input of the initial value of the counter, the output of which is connected to the address input of the first memory block, the output of the multiplier is connected to the information input of the accumulating adder, the output of which is the output of the interpolator, the inputs of the counter and register data and the reset input of the accumulating adder are connected to the input of the initial installation of the interpolator, the counting input of the counter and the synchronization input of the accumulating adder are connected to the clock input of the interpolator The first memory block is connected to the input of the first multiplier factor, the input of the second factor of which is connected to the output of the first memory block, and the output of the switch is connected to the address input of the second memory block.

где f $\genfrac{}{}{0ex}{}{\text{(3)}}{\text{max}}$ - - максимум третьей производной функции f(X);
h - расстояние между отсчетами функции f(X).The known technical solution has insufficient interpolation accuracy, which is characterized by an interpolation error equal to

where f $\genfrac{}{}{0ex}{}{\text{(3)}}{\text{max}}$ - is the maximum of the third derivative of the function f (X);
h is the distance between the samples of the function f (X).

Moreover, this accuracy is ensured for functions having a continuous third derivative (f (x) ∈ C ³ ). When interpolating functions having a continuous sixth derivative (f (x) ∈ C ⁶ ), information about the smoothness of functions is not fully taken into account, as a result of which the prototype provides low accuracy of interpolation.

The aim of the invention is to develop a device that provides higher accuracy of interpolation of functions having a continuous sixth derivative (f (x) ∈ C ⁶ ).
This goal is achieved by the fact that in the known interpolator containing the first and second registers, the first adder, the converter to additional code, control unit, the first switch, the first multiplier, counter and memory unit, the second, third, fourth, fifth, sixth and seventh adders, first, second, third, fourth and fifth fourth degree blocks, first, second, third, fourth and fifth delay elements, second, third, fourth, fifth, sixth, seventh and eighth multipliers, third, fourths Fifth and sixth registers and a second switch. The information inputs of the counter are connected to the information bus of the interpolator. The outputs are connected to the address inputs of the memory unit, and the control input is combined with the zeroing input of the first register and the first output of the control unit. The first input of the control unit is the interpolator clock bus, the second input is the interpolator start bus, and the second output is connected to the control input of the first register. The outputs of the first register are the output bus of the interpolator, and the information inputs are connected to the outputs of the first adder. The first group of information inputs of the first adder is connected to the outputs of the first multiplier. The first group of information inputs of the second adder is combined with the first group of information inputs of the third adder, the inputs of the converter into an additional code, the inputs of the first block raising to the fourth degree and the information inputs of the counter. The second group of information inputs of the second adder is connected to the third installation bus of the interpolator, and the outputs are connected to the inputs of the second block raising to the fourth degree. The outputs of the second fourth degree block are connected to the information inputs of the first delay element. The outputs of the first delay element are connected to the second group of information inputs of the sixth adder. The first group of information inputs of the sixth adder is connected to the outputs of the second multiplier. The second group of inputs of the second multiplier is connected to the second installation bus of the interpolator, and the first group of inputs is combined with the first group of inputs of the third multiplier, the outputs of the first block raising to the fourth degree and the information inputs of the fourth delay element. The outputs of the fourth delay element are connected to the first group of inputs of the first multiplier. The second group of inputs of the first multiplier is connected to the outputs of the second register. The information inputs of the second register are connected to the first group of outputs of the first switch. The second, third, fourth and fifth groups of outputs of the first switch are connected respectively to the information inputs of the third, fourth, fifth and sixth registers, the outputs of which are connected respectively to the second groups of inputs of the fifth, sixth, seventh and eighth multipliers, the outputs of which are connected respectively to the second, third , the fourth and fifth groups of information inputs of the first adder. The control input of the first adder is combined with the control inputs of the second, third, fourth, fifth, sixth and seventh adders, the first, second, third, fourth and fifth delay elements, and the fourth output of the control unit. The third group of outputs of the control unit is connected to the address inputs of the second and first switches. The information inputs of the first switch are connected to the outputs of the memory block. The third group of inputs of the control unit is connected to the fifth interpolator installation bus, the fourth group of inputs is connected to the sixth interpolator installation bus, and the fifth output is connected to the counter counter input and the information input of the second switch. The first, second, third, fourth and fifth outputs of the second switch are connected respectively to the control inputs of the second, third, fourth, fifth and sixth registers. The outputs of the converter into an additional code are connected to the first group of information inputs of the fourth adder and the inputs of the fifth block of raising to the fourth degree. The outputs of the fifth fourth degree block are connected to the first group of inputs of the fourth multiplier and the information inputs of the fifth delay element. The outputs of the fifth delay element are connected to the first group of inputs of the eighth multiplier. The second group of information inputs of the third adder is connected to the fourth installation bus of the interpolator and the second group of information inputs of the fourth adder. The outputs of the fourth adder are connected to the inputs of the fourth block raising to the fourth degree. The outputs of the fourth fourth degree block are connected to the information inputs of the third delay element. The outputs of the third delay element are connected to the first group of information inputs of the seventh adder. The second group of information inputs of the seventh adder is connected to the outputs of the fourth multiplier and the third group of information inputs of the sixth adder. The outputs of the sixth adder are connected to the first group of inputs of the sixth multiplier. The second group of inputs of the third multiplier is connected to the first installation bus of the interpolator and the second group of inputs of the fourth multiplier, and the outputs are connected to the first group of information inputs of the fifth adder. The second group of inputs of the fifth adder through the second delay element and the third block raising to the fourth degree is connected to the outputs of the third adder, and the outputs are connected to the first group of inputs of the fifth multiplier. The outputs of the seventh adder are connected to the first group of inputs of the seventh multiplier.

 The control unit includes the first and second comparison units, the first and second AND elements, a counter and an RS trigger. The S-input of the RS-flip-flop is the second input of the control unit and simultaneously the trigger bus of the interpolator. S-input of the RS-flip-flop connected to the input of zeroing the counter and the first output of the control unit. The R-input is the second output of the control unit and is connected to the output of the first comparison unit. The first group of inputs of the first comparison unit is the third group of inputs of the control unit and simultaneously the fifth installation bus of the interpolator. The second group of inputs of the first comparison unit is the third group of outputs of the control unit and is simultaneously connected to the outputs of the counter and the first group of inputs of the second comparison unit. The second group of inputs of the second comparison unit is the fourth group of inputs of the control unit and simultaneously the sixth interpolator installation bus, and the output is connected to the second input of the second element I. The output of the second element And is the fifth output of the control unit, and the first input is the fourth output of the control unit and is simultaneously connected with the counter counter input and the output of the first element I. The first input of the first element And is connected to the output of the RS-trigger, and the second input is the first input of the control unit and at the same time about the clock bus of the interpolator.

The listed new set of essential features of the claimed device provides a higher accuracy of interpolation of functions having a continuous sixth derivative (f (x) ∈ C ⁶ ). This is achieved by the fact that the interpolation is carried out more accurately based on a priori information about the degree of smoothness of the function.

где

f(x) - интерполируемая функция;
f_i - i-й отсчет функции f(x);
τ ∈ [-0,5, 0,5].
Реализация (1) в виде устройства позволяет вычислять функции f(x) ∈ C⁶ с точностью, определяемой погрешностью [2]

где f $\genfrac{}{}{0ex}{}{\text{(5)}}{\text{max}}$ - максимум пятой производной функции f(X);
h - шаг интерполяции.So, from [1, 2] it is known that to interpolate a function with splines of a minimal fourth-degree template, we can obtain the following expression

Where

f (x) is the interpolated function;
f _i - i-th sample of the function f (x);
τ ∈ [-0.5, 0.5].
Implementation of (1) in the form of a device allows us to calculate the functions f (x) ∈ C ⁶ with an accuracy determined by the error [2]

where f $\genfrac{}{}{0ex}{}{\text{(5)}}{\text{max}}$ - the maximum of the fifth derivative of the function f (X);
h is the interpolation step.

Поэтому, например, для функций f(x) ∈ C⁶ при h = 0,1 и в случае f $\genfrac{}{}{0ex}{}{\text{(3)}}{\text{max}}$ ≈ f $\genfrac{}{}{0ex}{}{\text{(5)}}{\text{max}}$ выигрыш μ₁/μ₂ может принимать значение, превышающее пятьсот.The accuracy of the prototype device is no better.

Therefore, for example, for functions f (x) ∈ C ⁶ for h = 0.1 and in the case f $\genfrac{}{}{0ex}{}{\text{(3)}}{\text{max}}$ ≈ f $\genfrac{}{}{0ex}{}{\text{(5)}}{\text{max}}$ the gain μ ₁ / μ ₂ may take a value in excess of five hundred.

 The claimed device is illustrated by drawings, in which in FIG. 1 shows a structural diagram of the claimed device, FIG. 2 shows one of the possible embodiments of the fourth degree block; FIG. 3 shows an embodiment of a delay element.

 The interpolator shown in FIG. 1, consists of the first 44, second 33, third 34, fourth 35, fifth 36 and sixth 37 registers, the first 43, second 13, third 14, fourth 15, fifth 29, sixth 30 and seventh 31 adders, the converter to additional code 12 , the first 27 and second 45 switches, the first 38, the second 21, the third 22, the fourth 26, the fifth 39, the sixth 40, the seventh 41 and the eighth 42 multipliers, the first 16, the second 17, the third 18, the fourth 19 and the fifth 20 building blocks fourth degree, first 23, second 24, third 25, fourth 28 and fifth 32 delay elements, control unit 4 6, the counter 10 and the memory unit 11. The information inputs of the counter 10 are connected to the information bus 3 of the interpolator, the outputs are connected to the address inputs of the memory unit 11, and the control input is combined with the zeroing input of the first register 44 and the first output of the control unit 46. The first input of the control unit 46 is the interpolator clock bus 1, the second input is the interpolator trigger bus 2, and the second output is connected to the control input of the first register 44. The outputs of the first register 44 are the interpolator output bus, and the information inputs are connected are connected to the outputs of the first adder 43. The first group of information inputs of the first adder 43 is connected to the outputs of the first multiplier 38. The first group of information inputs of the second adder 13 is combined with the first group of information inputs of the third adder 14, the inputs of the converter to the additional code 12, the inputs of the first block of construction the fourth degree 16 and the information inputs of the counter 10. The second group of information inputs of the second adder 13 is connected to the third installation bus 6 of the interpolator, and the outputs are connected to the strokes of the second fourth degree block 17. The outputs of the second fourth degree block 17 are connected to the information inputs of the first delay element 23. The outputs of the first delay element 23 are connected to the second group of information inputs of the sixth adder 30. The first group of information inputs of the sixth adder 30 is connected to the outputs of the second multiplier 21. The second group of inputs of the second multiplier 21 is connected to the second installation bus 5 of the interpolator, and the first group of inputs is combined with the first group of inputs t its multiplier 22, the outputs of the first fourth degree block 16 and the information inputs of the fourth delay element 28. The outputs of the fourth delay element 28 are connected to the first group of inputs of the first multiplier 38. The second group of inputs of the first multiplier 38 is connected to the outputs of the second register 33. Information inputs of the second register 33 connected to the first group of outputs of the first switch 27. The second, third, fourth and fifth groups of outputs of the first switch 27 are connected respectively to the information inputs of the third 34 , fourth 35, fifth 36 and sixth 37 registers, the outputs of which are connected respectively to the second groups of inputs of the fifth 39, sixth 40, seventh 41 and eighth 42 multipliers, the outputs of which are connected respectively to the second, third, fourth and fifth groups of information inputs of the first adder 43 The control input of the first adder 43 is combined with the control inputs of the second 13, third 14, fourth 15, fifth 29, sixth 30 and seventh 31 adders, the first 23, second 24, third 25, fourth 28 and fifth 32 delay elements, and the fourth output ohm control unit 46. The third group control unit 46 outputs coupled to address inputs of the first 45 and second 27 switches. The information inputs of the first switch 27 are connected to the outputs of the memory unit 11. The third group of inputs of the control unit 46 is connected to the fifth installation bus 8 of the interpolator, the fourth group of inputs is connected to the sixth installation bus 9 of the interpolator, and the fifth output is connected to the counting input of the counter 10 and the information input of the second switch 45. The first, second, third, fourth and fifth outputs of the second switch 45 are connected respectively to the control inputs of the second 33, third 34, fourth 35, fifth 36 and sixth 37 registers. The outputs of the converter to the additional code 12 are connected about the first group of information inputs of the fourth adder 15 and the inputs of the fifth block of raising to the fourth power 20. The outputs of the fifth block of raising to the fourth power of 20 are connected to the first group of inputs of the fourth multiplier 26 and the information inputs of the fifth delay element 32. Outputs of the fifth delay element 32 are connected about the first group of inputs of the eighth multiplier 42. The second group of information inputs of the third adder 14 is connected to the fourth interpolation installation bus 7 a second and a group of information inputs of the fourth adder 15. The outputs of the fourth adder 15 are connected to the inputs of the fourth block of fourth degree 19. The outputs of the fourth block of fourth degree 19 are connected to the information inputs of the third delay element 25. The outputs of the third delay element 25 are connected to the first the group of information inputs of the seventh adder 31. The second group of information inputs of the seventh adder 31 is connected to the outputs of the fourth multiplier 26 and the third group of information the moves of the sixth adder 30. The outputs of the sixth adder 30 are connected to the first group of inputs of the sixth multiplier 40. The second group of inputs of the third multiplier 22 is connected to the first installation bus 4 of the interpolator and the second group of inputs of the fourth multiplier 26, and the outputs are connected to the first group of information inputs of the fifth adder 29 The second group of inputs of the fifth adder 29 through the second delay element 24 and the third block raising to the fourth degree 18 is connected to the outputs of the third adder 14, and the outputs are connected to the first group of inputs of the heel th multiplier 39. The outputs of the seventh adder 31 are connected to the first group of inputs of the seventh multiplier 41.

 The control unit 46, also shown in FIG. 1, consists of the first 463 and second 466 comparison blocks, the first 464 and the second 465 And elements, the counter 462 and the RS-flip-flop 461. The S-input of the RS-flip-flop 461 is the second input of the control unit 46 and simultaneously the trigger bus 2 of the interpolator. The S-input of the RS flip-flop 461 is connected to the counter zeroing input 462 and the first output of the control unit 46. The R-input is the second output of the control unit 46 and is connected to the output of the first comparison unit 464. The first group of inputs of the first comparison unit 464 is the third group of inputs of the block control 46 and at the same time the fifth installation bus 8 of the interpolator. The second group of inputs of the first comparison unit 463 is the third group of outputs of the control unit 46 and is simultaneously connected to the outputs of the counter 462 and the first group of inputs of the second comparison unit 466. The second group of inputs of the second comparison unit 466 is the fourth group of inputs of the control unit 46 and at the same time the sixth installation bus 9 interpolator, and the output is connected to the second input of the second element And 465. The output of the second element And 465 is the fifth output of the control unit 46, and the first input is the fourth output of the control unit 46 and simultaneously connected to the counting input of the counter 462 and the output of the first AND element 464. The first input of the first AND element 464 is connected to the output of the RS flip-flop 461, and the second input is the first input of the control unit 46 and simultaneously the clock bus 1 of the interpolator.

 The fourth exponentiation block 16 shown in FIG. 2, consists of the first 161 and second 162 multipliers. The first and the group of inputs of the first multiplier 161 is combined with the second group of its inputs and is simultaneously the group of inputs of block 16. The group of outputs of the first multiplier 161 is connected about the first and second groups of inputs of the second multiplier 162, the group of outputs of which is the group of outputs of block 16.

 The delay element 23 shown in FIG. 3, consists of the first 231 and second 232 registers connected in series. The information inputs of the first register 231 are the information inputs of block 23, and the outputs of the second register 232 are the outputs of block 23. The control input of the first register 231 is connected to the control input of the second register 232 and is the control input of block 23.

 The claimed device operates as follows.

Перед началом работы в блок памяти 11 записываются значения коэффициентов сплайна (1/24)•g_-2, (1/24)•g_-1, (1/24)•g₀, (1/24)•g₁, (1/24)•g₂, со сдвигом адреса так, что j-му значению кода адреса соответствует значение (1/24)•g_j-3.Let X _i be the number formed by K high order bits of the argument X, where 2 ≤ K ≤ m-1; m is the length of the binary code of the number X. The number X _i represents the number of the nodal point. Let ΔX be the number formed by mK by the least significant bits of the argument such that X = X _i + ΔX • 2 ^-K , 0 ≤ ΔX ≤ 1. Then, by formula (1), for interpolation by splines of the minimum pattern, we have

Before starting work, the values of the spline coefficients (1/24) • g _-2 , (1/24) • g _-1 , (1/24) • g ₀ , (1/24) • g ₁ , ( 1/24) • g ₂ , with the address shifted so that the jth value of the address code corresponds to the value (1/24) • g _j-3 .

 In the initial state, meander pulses are sent to clock bus 1, the code number 7 is present on the setup bus 8, and the code 5 is on the setup bus 9. The variable code X is sent to the interpolator information bus 3. The code number 5 is sent to the setup bus 4 , on the installation bus 5 - code number 10, on the installation bus 6 - code number 2, on the installation bus 7 - code number 1.

When a positive polarity pulse is applied to the start bus 2, register 44 is reset to zero, and the high-order code of variable X is written to counter 10 — the value of X _i . At the same time, counter 462 is reset, and the RS-flip-flop 461 is set to a single state, at which the logic level “1” is formed at its output. The latter is fed to the first input of the first element And 464, allowing the passage of clock pulses through it. In addition, the code of the number 0 from the output of the counter 462 goes to the first group of inputs of the second comparison unit 466. The code of the number 5 from the installation bus 9 is received to another group of its inputs. As a result of the comparison operation, a signal with a unit level is generated at the output of block 466.

Clock pulses from the output of the first element And 464 are fed to the counting input of the counter 10 through the second element And 465 (the latter is opened by the unit level supplied to its second input from the output of the second comparison unit 466). In this case, the contents of the counter 10 increases each time by one. So, as a result of the influence of the first clock pulse, the contents of the counter 10 takes the value X _i +1. The latter enters the address inputs of the memory block 11, determining the cell number, the contents of which (1/24) • g _-2 is supplied to the information input of the input of the switch 27. Due to the fact that the control inputs of the switches 27 and 45 receive a code of 1 s counter outputs 462, the value (1/24) • g _-2 from the first group of outputs of block 45 is fed to the information inputs of register 33 and is recorded in register 33 under the influence of a control pulse. This pulse is supplied from the output of the second element And 465 through the switch 45 to the control input of the register 33.

Then, in the same way, in the registers 34, 35, 36 and 37, the values are written respectively (1/24) • g _-1 , (1/24) • g ₀ , (2/24) • g ₁ , (1/24) • g ₂ . Upon completion of writing to the register 37, the contents of the counter 462 (number 5 code) coincides with the number code supplied to the installation bus 9. As a result, a signal with a zero level is formed at the output of the second block, comparison 466, closing the second AND element 465 and causing the counter to stop ten.

Указанные величины, а также значения ΔX⁴ (с выхода блока возведения в четвертую степень 16 через элемент задержки 28) и (1-ΔX)⁴ (с выхода блока возведения в четвертую степень 20 через элемент задержки 32) одновременно поступают на соответствующие первые группы входов умножителей 38-42. В данных блоках происходит умножение этих величин на значения коэффициентов сплайна, подаваемые на вторые группы входов умножителей 38 - 42 с выходов регистров 33 - 37. В результате получаем произведения

Последние поступают на соответствующие группы информационных входов сумматора 43. Под воздействием сигналов, поступающих со второго выхода блока 46 на управляющий вход сумматора 43, на выходе последнего получаем значение функции f(X). При этом содержимое счетчика 462 совпадает с кодом числа 7, подаваемым на установочную шину 8. В результате на выходе первого блока сравнения 463 формируется единичный импульс. Последний поступает на управляющий вход регистра 44. Вычисленное значение функции f(X) с выхода сумматора 43 записывается в регистр 44. Кроме того, единичный импульс с выхода первого блока сравнения 463 подается на R-вход RS-триггера, 461, переводя его в нулевое состояние. В результате сигнал с нулевым уровнем с выхода RS-триггера 461 закрывает первый элемент И 464 и препятствует тем самым прохождению тактовых импульсов через первый элемент И 464. На этом работа устройства по вычислению значения функции f(X) завершается. Устройство готово к новому циклу работы.At the same time, during the above-described clock cycles of the device, the value ΔX (the least significant bits of the code of the variable X) is supplied to the input of the converter in an additional code 12, at the output of which we have the value (1-ΔX). The value ΔX is also supplied to the first group of information inputs of the adders 13 and 14, and to the first group of information inputs of the adder 15 is the value (1-ΔX). The code of number 1 is supplied to the second group of information inputs of the adders 14 and 15, and the code of number 2 is fed to the second group of information inputs of the adder 13. Under the influence of the signals supplied to the control inputs of the adders 13, 14 and 15 from the second output of the control unit 46, the outputs adders 13, 14 and 15 are formed values, respectively (2 + ΔX), (1 + ΔX) and (2-ΔX). The indicated values are supplied to the inputs of the corresponding fourth degree blocks 17, 18 and 19. The value of ΔX c of the information bus is received at the input of the fourth level block 16. At the input of the block of raising to the fourth power of 20 is the value (1-ΔX) from the output of the converter to the additional code 12. At the outputs of the blocks of raising to the fourth power of 16, 17, 18, 19 and 20 we have the values ΔX ⁴ , (ΔX + 2), respectively ⁴ , (ΔX + 1) ⁴ , (2-ΔX) ⁴ and (1-ΔX) ⁴ . The value ΔX ⁴ from the output of the fourth degree raising block 16 goes to the first groups of inputs of the multipliers 21 and 22. The code of the number 10 is supplied to the second group of inputs of the multiplier 21, and the code of the number -5 is sent to the second group of inputs of the multiplier 22. As a result of the multiplication operation, the values of 10ΔX ⁴ and -5ΔX ^4, respectively, are generated at the outputs of the multipliers 21 and 22. The latter go to the first groups of information inputs of adders 30 and 29, respectively. The values of (ΔX + 1) ⁴ (via delay element 24) and (ΔX + 2) ⁴ (via delay element 23) are supplied to the second groups of information inputs of adders 29 and 30, respectively . The value (1-ΔX) ⁴ from the output of the fourth degree raising block 20 goes to the first group of inputs of the multiplier 26, to the second group of inputs of which the code is the number - 5. As a result of the multiplication operation, the value of -5 (1- ΔX) ⁴ . The latter is fed to the third group of information inputs of the adder 30 and the second group of information inputs of the adder 31. The value (2-ΔX) ⁴ from the output of the block raising to the fourth power 19 through the delay element 25 is supplied to the first group of information inputs of the adder 31. Delay elements 23, 24 and 25 are designed to ensure the simultaneous receipt of code combinations for all inputs of adders 29, 30 and 31. As a result of the summation operations in blocks 29, 30 and 31 at the outputs of the latter, we have values, respectively

The indicated values, as well as the ΔX ⁴ values (from the output of the fourth degree block 16 through the delay element 28) and (1-ΔX) ⁴ (from the output of the fourth degree block 20 through the delay element 32) simultaneously arrive at the corresponding first groups of inputs multipliers 38-42. In these blocks, these values are multiplied by the values of the spline coefficients supplied to the second groups of inputs of the multipliers 38–42 from the outputs of the registers 33–37. As a result, we obtain the products

The latter arrive at the corresponding groups of information inputs of the adder 43. Under the influence of the signals from the second output of block 46 to the control input of the adder 43, at the output of the latter we obtain the value of the function f (X). In this case, the contents of the counter 462 coincides with the number 7 code supplied to the installation bus 8. As a result, a single pulse is generated at the output of the first comparison unit 463. The latter goes to the control input of the register 44. The calculated value of the function f (X) from the output of the adder 43 is written to the register 44. In addition, a single pulse from the output of the first comparison unit 463 is fed to the R-input of the RS-flip-flop, 461, translating it to zero state. As a result, a signal with a zero level from the output of the RS-flip-flop 461 closes the first element And 464 and thereby prevents the passage of clock pulses through the first element And 464. This completes the work of the device to calculate the value of the function f (X). The device is ready for a new cycle of work.

 The elements included in the structural diagram of the claimed device are known and described, for example, in [3]. So, in the specified source describes the principles of construction and implementation examples: counters 10, 462 on p. 85 - 86 (can be implemented on the K155IE5 chip), memory block 11 on p. 171 - 174 (can be implemented on the K155PR6 chip), I 464, 465 elements per page. 35 pic. 1.19a (can be implemented on the K155LI1 chip), registers 33 - 37, 44 on p. 104 - 105 (can be implemented on the K155IR13 chip - p. 111 Fig. 1.78).

 The RS-trigger 461 can be implemented on the K155LE4 chip, as shown in [4] on p. 280, fig. 4.20 a.

 The principle of operation of the multipliers 21, 22, 25, 38 - 42 is known and described in [5] on c. 163 - 221. They can be implemented on chips SN54284 and SN54285, p. 305, fig. 6.3.12 or on the ADSP1016 microcircuit (see [6] on page 502, table 7.4).

 The principle of operation of comparison blocks 463, 466 is known and described in [7] on p. 234 - 257. Can be implemented on K561IP2 microcircuits (see [8], p. 114, Fig. 4.12 b).

 The principle of operation of the adders 13 - 15, 29 - 31, 43 is known and described in [9] on p. 184 - 198. The full adder is described in [10] on p. 152, fig. 1.112 and p. 153, fig. 1.113. It can be implemented on the elements of EXCL. OR - K155LP5, AND - K155LI1, OR - from OR-NOT K155LE4 and NOT K155LN1.

 The principle of implementation of the converter into additional code 12 is known and described in [4] on p. 462 - 468. Can be implemented on the K155LA3 chip.

 The implementation principle of switches 27 and 45 is known and described in [10] on p. 220. They can be implemented on K561KT3 microcircuits.

 The fourth exponentiation blocks 16-20 can be implemented using multipliers, as shown in FIG. 2, on chips SN54284 and SN54285.

 Delay elements 23 - 25, 28, 32 can be implemented using registers (chip K155IR13), as shown in FIG. 3.

Literature
1. Zheludev V.A. Local spline approximation on a uniform grid. // Journal of Computational Mathematics and Mathematical Physics. - 1987. - Volume 27. - N 9. - S. 1296-1310.

 2. Zheludev V. A. Restoration of functions and their derivatives from grid data with an error using local splines. // Journal of Computational Mathematics and Mathematical Physics. - 1987. - Volume 27. - N 1.- S. 22-34.

 3. V.L. Awl. Popular digital circuits. Directory. - M.: Radio and Communications, 1988.

 4. L. M. Goldenberg. Pulse and digital devices. - M.: Communication, 1973.

 5. M.A. Kartsev, V.A. Brick. Computing systems and synchronous arithmetic. - M.: Radio and Communications, 1981.

 6. S. Kun. Matrix processors on VLSI: Per. from English - M.: Mir, 1991.

 7. Yu. V. Gavrilov, A.N. A bunch. Arithmetic devices of high-speed digital computers. - M.: Soviet Radio, 1970.

 8. V.N. Veniaminov, O.N. Lebedev, A.I. Miroshnichenko. Microcircuits and their application. Reference Guide, 3rd ed. reslave. and add. - M .: Radio and communications, 1989.

 9. D. Givone, R. Rosset. Macroprocessors and microcomputers: Introductory course: Per. from English - M.: Mir, 1983.

 10. V. L. Shilo. Popular digital circuits. Directory. 2nd ed., Rev. - Chelyabinsk: Metallurgy, 1989.

Claims (2)

 1. An interpolator comprising first and second registers, a first adder, an additional code converter, a control unit, a first switch, a first multiplier, a counter and a memory unit, the information inputs of the counter connected to the information bus of the interpolator, the outputs connected to the address inputs of the memory unit, and the control input is combined with the zeroing input of the first register and the first output of the control unit, the first input of which is the interpolator clock bus, the second input is the interpolator trigger bus, and the second output with is single with the control input of the first register, the outputs of which are the output bus of the interpolator, and the information inputs are connected to the outputs of the first adder, the first group of information inputs of which are connected to the outputs of the first multiplier, characterized in that the second, third, fourth, fifth, sixth and seventh adders, first, second, third, fourth and fifth fourth degree blocks, first, second, third, fourth and fifth delay elements, second, third, fourth, fifth, sixth, seventh th and eighth multipliers, third, fourth, fifth and sixth registers and a second switch, the first group of information inputs of the second adder combined with the first group of information inputs of the third adder, the inputs of the converter into an additional code, the inputs of the first block raising to the fourth degree and information inputs of the counter , the second group of information inputs of the second adder is connected to the third installation bus of the interpolator, and the outputs are connected to the inputs of the second block raising to the fourth degree, the outputs of which are connected to the information inputs of the first delay element, the outputs of which are connected to the second group of information inputs of the sixth adder, the first group of information inputs of which are connected to the outputs of the second multiplier, the second group of inputs of which is connected to the second installation bus of the interpolator, and the first group of inputs is combined with the first the group of inputs of the third multiplier, the outputs of the first block raising to the fourth degree and the information inputs of the fourth delay element, the outputs of which the second are connected to the first group of inputs of the first multiplier, the second group of inputs of which is connected to the outputs of the second register, the information inputs of which are connected to the first group of outputs of the first switch, the second, third, fourth and fifth groups of outputs of which are connected respectively to the information inputs of the third, fourth, fifth and sixth registers, the outputs of which are connected respectively to the second groups of inputs of the fifth, sixth, seventh and eighth multipliers, the outputs of which are connected respectively to the second , the third, fourth and fifth groups of information inputs of the first adder, the control input of which is combined with the control inputs of the second, third, fourth, fifth, sixth and seventh adders, the first, second, third, fourth and fifth delay elements, and the fourth output of the control unit, the third group of outputs of which is connected to the address inputs of the second switch and the first switch, the information inputs of which are connected to the outputs of the memory unit, the third group of inputs of the control unit is connected to the fifth with the interpolator bus, the fourth group of inputs is connected to the sixth interpolator installation bus, and the fifth output is connected to the counter counter input and the information input of the second switch, the first, second, third, fourth, and fifth outputs of which are connected respectively to the control inputs of the second, third, fourth, of the fifth and sixth registers, the outputs of the converter into an additional code are connected to the first group of information inputs of the fourth adder and the inputs of the fifth block of raising to the fourth degree, the outputs of which are connected to the first group of inputs of the fourth multiplier and the information inputs of the fifth delay element, the outputs of which are connected to the first group of inputs of the eighth multiplier, the second group of information inputs of the third adder is connected to the fourth installation bus of the interpolator and the second group of information inputs of the fourth adder, the outputs of which are connected to the inputs of the fourth block raising to the fourth degree, the outputs of which are connected to the information inputs of the third delay element, output whose odes are connected to the first group of information inputs of the seventh adder, the second group of information inputs of which are connected to the outputs of the fourth multiplier and the third group of information inputs of the sixth adder, the outputs of which are connected to the first group of inputs of the sixth multiplier, the second group of inputs of the third multiplier is connected to the first installation bus of the interpolator and the second group of inputs of the fourth multiplier, and the outputs are connected to the first group of information inputs of the fifth adder, the second group of inputs which, through the second delay element and the third fourth degree block, is connected to the outputs of the third adder, and the outputs are connected to the first group of inputs of the fifth multiplier, and the outputs of the seventh adder are connected to the first group of inputs of the seventh multiplier.  2. The interpolator according to claim 1, characterized in that the control unit is configured to comprise first and second comparison units, first and second elements AND, a counter and an RS trigger, the S-input of the RS trigger being the second input of the control unit and simultaneously the start bus interpolator, connected to the counter zeroing input and the first output of the control unit, the R-input is the second output of the control unit and connected to the output of the first comparison unit, the first group of inputs of which is the third group of inputs of the control unit and at the same time the fifth interpolator bus, and the second group of inputs is the third group of outputs of the control unit and is simultaneously connected to the outputs of the counter and the first group of inputs of the second comparison unit, the second group of inputs of which is the fourth group of inputs of the control unit and simultaneously the sixth interpolator installation bus, and the output is connected to the second the input of the second element And, the output of which is the fifth output of the control unit, and the first input is the fourth output of the control unit and is simultaneously connected to the counting input counter house and output of the first AND gate whose first input coupled to an output RS-flip-flop and the second input is the first input of the control unit while the bus clock interpolator.

Images