RU2029352C1 - Data input/output device - Google Patents

Abstract

FIELD: computer engineering. SUBSTANCE: device has interface units 1,7, synchronizing unit 2, pulse shapers 3, 5, control unit 4, pulse generator 6, registers 8,14, keyboard 9, coder 10, switch 11, display unit 12, decoder 15, and storage unit 16. EFFECT: improved design. 10 dwg

Description

 The invention relates to automation and computer technology, in particular to devices for input-output of information suitable for processing in computers.

 A device for two-way exchange of information containing a clock, a counter, first and second decoders, call keys, first and second groups of AND elements, memory elements, indicators, answer keys [1].

 The disadvantage of this device is the need to transmit information in parallel code and transmit the strobe on a separate line, which limits the functionality of the device when connected to a local area network using a computer.

 Closest to the invention, the technical solution is a device for input / output of information, comprising a keyboard connected via an encoder and a first register to the first interface unit, a pulse shaper connected to the first interface unit, a switch, a second interface unit connected through the decoder to the display unit, to the first input of which a pulse generator is connected, and the second input is connected to the second output of the second register [2].

 The disadvantage of this device is that the transmission of information in it by amplitude-modulated transmissions does not provide a clock frequency transmission over the information communication line, which reduces the speed of information exchange and the reliability of its recovery, i.e. limits the functionality of the device.

 The purpose of the invention is the expansion of the functionality of the device for input-output of information by providing simultaneous indication of the recorded states of the process, as well as improving the reliability of its operation.

 The proposed constructive implementation of the device for input / output of information leads to the expansion of its functionality, because, unlike the prototype, the introduction of a second pulse shaper and a memory unit allows for simultaneous indication of the recorded states of the process, and the introduction of synchronization and control units increases the reliability of the device due to the exception false operation during a phase incursion on the elements of the device circuit. Using a photo-optical reader allows perforated cards to quickly change information, which also extends the functionality of the device and increases its reliability, as it eliminates mechanical contacts.

 If there is a logical “1” in the eighth category of the information code coming from the second output of the second register to the seventh input of the control unit, according to the proposed block diagram, the device for input-output of information, unlike the prototype, acquires the ability to automatically control its performance on the initiative of a computer without operator intervention by providing the possibility of repeating the cycle of information output, which enhances the effect, expanding the functionality of the device.

 In FIG. 1 shows a block diagram of a device for input-output information; figure 2 shows a timing diagram explaining the operation of the device; figure 3 shows a diagram of a second pairing unit; 4 is a timing chart explaining the operation of the second interface unit; figure 5 shows a diagram of a synchronization unit; figure 6 - diagram of the control unit; Figures 7 and 8 show the operation algorithm of the control unit; figure 9 shows a diagram of a first pairing unit; 10 is a timing chart explaining the operation of the first interface unit.

 The device for inputting and outputting information includes a second pairing unit 1, a synchronization unit 2, a second pulse shaper 3, a control unit 4, a first pulse shaper 5, a pulse generator 6, a first pairing unit 7, a first register 8, a keyboard 9, an encoder 10, a switch 11, a display unit 12, a photo-optical reader 13, a second register 14, a decoder 15, a memory unit 16. Timing diagrams (figure 2) are indicated by positions 17-25.

 To ensure the operation of the device for input-output of information, it is pre-connected to an exchange channel with a computer filled with clock signals generated on the side of the computer (Fig.2, 18). These clock signals are fed to the first input of the second block 1 pairing.

 The second interface unit 1 contains (Fig. 3) an optoelectronic switch 26, a pulse shaper 27, which can be used as two elements NOT, RS-trigger 28 and D-trigger 29.

 The second block 1 pair is as follows.

 Phase-modulated pulse signal in the form of bipolar current pulses from a computer through a two-wire symmetric communication line is fed to the input of an optoelectronic switch 26, which provides galvanic isolation between the computer and the device for inputting, outputting information and converts bipolar current pulses (Figs. 4, 30) into unipolar pulses voltage (Fig.4, 31 and 32). Unipolar voltage pulses are supplied to the first output of the second interface unit 1 and to the first and second inputs of the pulse shaper 27, which, shortening the duration of the pulse fronts and inverting them in voltage, from their first and second outputs transmits them respectively to the first and second inputs of the RS-flip-flop 28. The RS-trigger 28 at its output captures (Fig. 4, 33) the current value of the phase of the input pulses and transfers it to the first input (D-input) of the D-trigger 29. To the second input of the D-trigger (C-input), which is the second input of the second pairing unit, p the clock signal F 5 (Fig. 4, 34) is released, along the leading edge of which the phase value is recorded, as a result of which, at the output of the D-flip-flop 29, a code of received information is generated in a potential form (Figs. 4, 35), thereby performing phase modulation demodulation signal, and is sent to the second output of the second pairing unit.

 Unipolar voltage pulses from the first output of the second interface unit 1 are fed to the input of the synchronization unit 2 to generate clock signals for the entire device for input-output information, which ensures the reliability of its operation.

 Synchronization block 2 (Fig. 5) contains an EXCLUSIVE OR 36 element connected by an output to an integrating RC circuit 37, elements NOT 38, 39, a binary counter 40 for two, elements OR-NOT 41, 42. It generates clock signals F1, F2, Ф3, Ф4, Ф5, Ф6 and directs the clock signal Ф1 from its first output to the first input of the second pulse shaper 3, made, for example, on the basis of a single vibrator, and the second inputs of the control unit 4 and the first shaper 5, made, for example, on the basis of D trigger, Ф2 clock signal from its second output to the second input of the generator and 6 pulses, for which, for example, a connection of counters can be used, and the third input of the control unit 4, the clock signal Ф3 from its third output to the second inputs of the first block 7, the clock signal Ф4 from its fourth output to the third input of the first block 7 , the clock signal F5 from its fifth output to the second input of the second block 1 of the pair and the fourth input of the first block 7 of the pair, the clock signal F from its sixth output to the second input of the second register 14, which can be used, for example, dvigovy register.

 The EXCLUSIVE OR element 36 and the integrating circuit 37 of the synchronization unit 2 exclude high-frequency interference and phase rotation of the input pulses received from the first output of the second interface unit 1, and output the synchronization signal Ф4 to the fourth output of the synchronization unit 2 (Figs. 2, 19), and to the fifth and the sixth outputs of the synchronization unit receives the same inverse F5 and direct formed F6 signals, respectively.

 Binary counter 40 for two and logical elements OR NOT 41, 42 provide the first and second outputs of synchronization unit 2, signals F1 and F2, respectively (Figs. 2, 20 and 21). Two-phase synchronization of signals Ф1 and Ф2, spaced in time, with mismatching edges allows to increase the reliability of operation of the units of the device for input-output information, eliminating the ambiguity of the generation of control signals during transient switching processes of the used logic elements.

 The binary counter 40 two also gives the signal Ф3 with a duration equal to the distance between the leading edges of the signals Ф1 and Ф2 to the third output of the synchronization block 2, which ensures the functioning of the first register 8 and the first pairing unit 7.

 To change the state of the technological process, it is necessary to transfer a certain command to the computer: "left", "cooling", "turn 90". To do this, the operator presses and releases the button corresponding to this command on the keyboard 9. At the time of pressing, the closed contacts of the button ensure the passage of the voltage pulse through the encoder 10 if there is a clock signal F7 at its second input coming from the second output of the pulse generator 6. On the leading edge of this voltage pulse, the encoder 10 sets up on its first output a binary eight-bit parallel code (one word) of the pressed button, which goes to the information inputs of the first group of the switch 11.

 Simultaneously with the issuance of the code of the keyboard button 9, the encoder 10 from its second output issues a stop command in the form of a logical "1" to the first input of the first pulse shaper 5 (Figs. 2, 22). The gate "STRB 1" logical "1" from the first output of the first pulse shaper 5 (Fig.2, 23) is fed to the third input of the encoder 10, stopping encryption, and to the first inputs of the control unit 4, starting it, the pulse generator 6, starting it . The pulse generator 6 from its first output sends a signal to the first input of the display unit 12, made, for example, on an LED, including an indication of the operation of the pressed button.

 Simultaneously with the output of the strobe "STRB 1" from the first output of the first pulse shaper 5 from its second output, the same strobe enters the fourth input of the control unit 4, but it undergoes inversion - "STRB 2" in the form of a logical "0".

 The control unit 4 (FIG. 6) includes D-flip-flops 43, 47, 50, a four-input AND-NOT 44 element, AND-NOT 45, 49 elements, a three-digit binary counter 46, an OR-NOT 48 element.

 The control unit 4 organizes serial transmission to the first input of the first register 8 from the output of the switch 11 of information in the form of a binary parallel code consisting of three eight-bit words coming from the first output of the encoder 10 about the pressed button code to the first input of the switch 11, and from the outputs of the photo-optical reader 13 of the information specified by its perforated cards, respectively, to the information inputs of the second group of the switch 11 under the control of a two-bit code supplied to the input of the photo-optical reader 13 and the address input of the switch 11 from the first output control unit 4 in accordance with the algorithm of its operation (Figs. 7 and 8).

 The information received under the control of the control unit 4, when the second and third inputs of the clock signals F1 and F2 are available, the information from the output of the switch 11 to the first input of the register 8 is recorded in it under the control of the “Record” signal received at its third input from the second output of the control unit 4, and is converted by register 8 from parallel to serial code. Information in a serial code in the form of a potential signal from the first output of the first register 8 (Fig.2, 17) is fed to the first input of the first block 7 of the pair.

 The first interface unit (Fig. 9) contains the elements EXCLUSIVE OR 51, 52 element AND NOT 53, 54, element NOT 55, element 56 current-carrying resistors.

 The first pairing unit operates as follows.

 The code of the information transmitted to the computer in potential form (Fig. 10, 57) from the first input of the first interface unit 7 is supplied to the first inputs of the EXCLUSIVE OR 51, 52 elements with the simultaneous input of the EXCLUSIVE OR 51 element of the F4 clock signal (Fig. 10, 58 ) At the same time, the same but inverted clock signal Ф5 is supplied to the second input of the EXCLUSIVE OR 52 element. At the outputs of the EXCLUSIVE OR elements 51 and 52, in accordance with their function, signals are generated that differ in phase from the synchronization input signals (phase-modulation occurs), depending on the logical level of information at the first inputs of the elements EXCLUSIVE OR 51 and 52. The presence of logical "1" at these inputs inverts the phase of the synchronization signals by 180 °, and the presence of a logical “0” does not invert the phases of the synchronization signals. At the same time, the input of the FZ synchronization signal arrives at the input of the HE 55 element, which, having undergone inversion (FIGS. 10, 59) in the HE 55 element, goes to the second inputs of the AND-NOT 53 and 54 elements, gating the passage of signals from their first inputs to their outputs ( 10, 60 for the output of the AND-NOT element 53; 61 for the output of the AND-NOT element 54). The signal from the output of AND-NOT elements 53 and 54 is fed to the first and second inputs of the element 56 of the current-setting resistors, followed by the transmission of a phase-modulated pulse signal (Fig. 10, 62) in the form of bipolar current pulses from the output of the first block 7 to the symmetrical two-wire computer line .

 The first register 8, at the end of the transmission of information to the first pairing unit 7, generates a “Ready transmitter” signal, transmitted by it from its second output to the fifth input of the control unit 4, for the control unit to organize another information transfer cycle through the switch 11. This completes the single-word output cycle .

 After the output of three words, the device for inputting, outputting information ends the cycle of outputting information to the computer about the pressed button in accordance with the algorithm of operation (Fig. 7) of the control unit 4 (Fig.6). At the end of the three-word output cycle, the control unit 4, from its third output, sets the resolving potential to the third input of the first pulse shaper 5, due to which at the first and second outputs of the first shaper 5, the gate "STRB 1" goes to logical "0" and the strobe "STRB 2", to the logical "1". Logical "0" at the third input of the encoder 10 allows encryption, and logical "1" at the fourth input of the control unit 4 prepares it for the next cycle of its operation, thereby bringing the device for input-output of information to its original state for the possibility of pressing a button.

 After processing the received information, the computer issues a response or initiative command to indicate the status through the symmetrical two-wire communication line to the device for input-output of information. The command in serial code is supplied to the first input of the second block 1 pairing. If there is a second input block of the second interface block of the clock signal Ф5 coming from the fifth output of the synchronization unit 2, a phase-pulse demodulation of the pulse signal from the second output to the first input of the second register 14 takes place in the second interface unit, where it is converted from serial to parallel upon receipt of the second input of the second register of the synchronization signal F6 from the sixth output of synchronization unit 2. When the second register 14 is filled with the received information (eight-bit word), it generates at its first output a “Ready receiver” signal, which is fed to the sixth input of the control unit 4 and simultaneously to the second input of the second pulse shaper 3, starting it.

 At the moment the second pulse shaper generates, at its first signal output, the strobe "STRB 3" supplied to the first input of the decoder 15, permission to decrypt takes place. In the decoder 15 is the decryption of the eight-bit code received at its second input from the second output of the second register 14.

 If there is a logical “1” in the eighth digit of the code of information coming from the second output of the second register 14 to the seventh input of the control unit 4, a command is generated at the fourth output of the control unit that arrives at the fourth input of the first pulse shaper 5, equivalent to the “stop” command received to the first input of the first driver 5 pulses from the second output of the encoder 10, i.e. the information output cycle from the information input-output device is repeated, but now already at the initiative of the computer, without the participation of the operator and keyboard 9, which ensures an additional effect, namely, to ensure automatic monitoring of the operability of the device for input-output of information using the computer program.

 At the end of the signal "STR 3" the second pulse shaper 3 at its second output generates a signal "End of reading", which, entering the third input of the second register 14, allows it to receive the next information.

 The decrypted code from the decoder 15 is fed to the input of the memory unit 16 and is stored. From the output of the memory unit 16, a signal corresponding to commands from the computer, for example, "cooling", "turn 90", etc., is supplied to the second input of the display unit 12, turning the indicator on or off. This completes the information input cycle.

 The implementation of the device for input-output of information in the manner described above provides an extension of its functionality due to the simultaneous indication of the recorded states of the process, as well as increased reliability due to the use of two-phase synchronization.

Claims (1)

 DEVICE FOR INFORMATION INPUT-OUTPUT, comprising a keyboard, an encoder, a first pulse shaper, a pulse generator, an indication unit, the first and second interface units, first and second registers, a switch, a decoder, the output of the first interface unit is the output of the device, the input of the second interface unit is the device input, characterized in that a second pulse shaper, a control unit, a synchronization unit, a memory unit, a photo-optical reader are introduced into it, and the keyboard outputs are connected to the information input the encoder, the group outputs of which are connected to the information inputs of the first group of the switch, the outputs of which are connected to the information inputs of the first register, the information output of which is connected to the information input of the first pairing unit, the encoder output is connected to the first information input of the first pulse shaper, the first output of which is connected to the first control input of the encoder, the first input of the control unit and the trigger input of the pulse generator, the first output of which is connected to the control in the display unit, the second output is with the second control input of the encoder, the information outputs of the group of the second interface unit are connected to the inputs of the synchronization unit, the information output of the second interface unit is connected to the information input of the second register, the output of which is connected to the first start input of the second pulse shaper and the sixth input of the control unit, the outputs of the second register group are connected to the information inputs of the decoder, the outputs of which are connected to the inputs of the memory unit, the outputs of which are connected to mation inputs of the display unit, one of the outputs of the second register group is connected to the seventh input of the control unit, the first output of the second pulse shaper is connected to the control input of the decoder, and the second output is connected to the control input of the second register, the first output of the synchronization block is connected to the second start input of the second shaper pulses, the second input of the control unit and the clock input of the first pulse shaper, the second output is connected to the control input of the pulse generator and the third input of the control unit the third output is connected to the shift input of the first register and the first control input of the first interface unit, the fourth output is to the second control input of the first interface unit, the fifth output is to the third control input of the first interface unit and the control input of the second interface unit, and the sixth output is with the shift input of the second register, the first output of the control unit is connected to the address input of the switch and the input of the photo-optical reader, the outputs of which are connected to the information inputs of the second group of the switch, w A control unit output is connected to a recording input of the first register, the overflow output of which is connected to the fifth input of the control unit, the third output of which is connected to the reset input of the first pulse shaper, the fourth output is connected to the second information input of the first pulse shaper, the second output of which is connected to the fourth input control unit.

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