KR0137957Y1 - Transcoding circuit - Google Patents

Abstract

The present invention relates to a code conversion circuit, and in the prior art, the F-S ACK, the receiver and the Manchester reciever, and the receiver are different from each other in the form of sending and receiving data. The receiver and the Manchester transmitter and receiver can only be used in pairs, respectively, and the FSC transmitter and the Manchester receiver cannot be connected. In order to solve such a conventional problem, the present invention devises a code conversion circuit that can be connected to other products by converting it to a Manchester code when there is a F-SC coded product.

Description

Transcoding circuit

1 is a block diagram of a code conversion circuit of the present invention.

(A) to (c) of FIG. 2 are diagrams showing waveforms during a code conversion operation.

(a) is F-stay signal waveform diagram.

(b) is a waveform of a Manchester signal.

(c) is an intermediate signal waveform diagram.

(A) to (f) of FIG. 3 are signal waveform diagrams of the respective parts in FIG.

(a) is FSC signal waveform diagram.

(b) is an output waveform diagram of a clock generator.

(c) is an output waveform diagram of a logic converter.

(d) is an output waveform diagram of a clock converter.

(e) is an output waveform diagram of a latch part.

(f) is an output waveform diagram of a waveform forming unit

FIG. 4 is a truth table showing the logical combination of the logic converter in FIG.

* Explanation of symbols for main parts of the drawings

100: 4-bit shift register 101: clock generator

102: logic converter 103: clock converter

104: latch portion 105: waveform forming portion

The present invention relates to a code conversion circuit, and more particularly, to a code conversion circuit adapted to convert a frequency shift key (FSK) code into a Manchester code.

FSC transmitter, receiver and Manchester transmitter and receiver are different in the form of sending and receiving data, and there is no interface circuit between FSC transmitter and Manchester receiver. Therefore, FSC transmitter, receiver and Manchester transmitter and receiver are each paired only. It could only be used, but it was not possible to connect FSC transmitters and Manchester receivers.

It is an object of the present invention to provide a code conversion circuit that can be connected to other control products by replacing them with a Manchester code if there is a F-SC coded product to solve such a conventional problem.

The code conversion circuit for solving the object of the present invention is a shift register for shifting the F-esque data signal in accordance with the clock signal, and outputs a clock signal of a predetermined multiple of the F-esque signal to the shift register to sample the F-esque data. A logic converter for outputting a predetermined logic signal by combining a clock generation unit, an output signal of the shift register, and a clock signal of the clock generation unit to determine the output signal of the FCS signal in order to accurately determine the output data of the logic conversion unit. A clock converting unit for converting a multiple clock signal, a latching unit for synchronizing the output of the logic converting unit with an output waveform of the clock converting unit, and outputting the output of the latching unit as a Manchester signal according to the clock signal of the clock generating unit; It is characterized by consisting of a waveform forming unit.

Hereinafter, with reference to Figures 1 to 4 showing an embodiment with respect to the operation and effects of the present invention in detail as follows.

FIG. 1 is an exemplary embodiment of the present invention, as shown in FIG. 1, a 4-bit shift register 100 for shifting an input FSP data signal according to a clock signal, and a communication rate for sampling the input FSP data. Logic for outputting a predetermined logic signal by combining a clock generator 101 for outputting a clock signal corresponding to four times of the signal to the 4-bit shift register 100 and an output signal of the 4-bit shift register 100. The converter 102 and the clock converter 103 converts the clock signal of the clock generator 101 into a clock signal twice the communication speed in order to accurately determine the output data of the logic converter 102. And a latch unit 104 for synchronizing the output of the logic converter 102 with the output waveform of the clock converter 103 and outputting the output of the latch unit 104 to the clock generator 101. Manchester signal (Msig) according to clock signal of Constitute a waveform forming section 105 for outputting.

Referring to the operation of one embodiment of the present invention configured as described above are as follows.

First, as shown in (a) of FIG. 2, the FSC signal FSK is transmitted in the form of frequency in the form of 10MHZ when the data is '0' and 5MHZ when the data is '1'.

On the other hand, the Manchester signal Msig is an F-esque which transmits data in a logic form of 'high (1)' and 'low (2)' as shown in (b) of FIG.

Therefore, in order to convert the F-SK signal FSK to the Manchester signal Msig, first convert the F-SK signal FSK to a waveform as shown in FIG. Convert to

The reason for converting to the intermediate waveform is that '1' or '0' can be determined only when the input F-esque signal is about 2 cycles.

In FIG. 2, 'low' means changing from OV to 5V for 1/2 cycle of FSC signal having data '1' or '0', and 'high' means changing from 5V to OV for 1/2 cycle. Say.

In more detail, when the F-esque signal FSK as shown in (a) of FIG. 3 is input, the clock generator 101 of FIG. 3 corresponds to four times the speed of the F-esque signal FSK. The clock signal as shown in b) is outputted to the 4-bit shift register 100.

Accordingly, the 4-bit shift register 100 receives the F-esque signal in order up to the rising edge of the first four clocks. Then, the state of the output terminal outO-out3 of the 4-bit shift register 100 is 5V, 0V, 5V, 0V.

The logic converter 102 receiving the output of the 4-bit shift register 100 outputs a 5V, `` high '' signal by the logic combination truth table as shown in FIG. Although applied, the output waveform of the continuous logic converter 102 is as shown in FIG.

On the other hand, the clock converter 103 converts the output waveform of the clock generator 101 into a clock signal corresponding to twice the F-esque signal as shown in FIG. ) Is applied. Therefore, the signal latched to the latch section 104 does not change until the next rising edge of the clock switching section, and its output waveform is as shown in (e) of FIG.

The waveform forming unit 105 which receives the output signal of the latch unit 104 makes the waveform as shown in (f) of FIG. 3 and outputs it as a Manchester signal Msig.

As described in detail above, the present invention can receive the data signal from the FSC signal transmitter in the Manchester signal receiver, and if there is a FSC coded product, it can be used by connecting it to another Manchester signal product by changing it to the Manchester code product. It works.

Claims (1)

A shift register for shifting the input F-esque data signal according to the clock signal, a clock generator for outputting a clock signal faster than the F-esque signal by a predetermined multiple to sample the input F-esque data, to the shift register; A logic converter which outputs a predetermined logic signal by combining the output signal of the shift register, and converts the clock signal of the clock generator into a clock signal that is as fast as a predetermined multiple of the FSC signal to accurately determine the output data of the logic converter. A clock converting section, a latch section for synchronizing the output of the logic converting section with an output waveform of the clock converting section, and a waveform forming section for outputting the latch section output as a Manchester signal according to the clock signal of the clock generating section. Code conversion circuit characterized by.